fhdl.cd: rename ClockDomain signals together with domain.

diff --git a/nmigen/fhdl/cd.py b/nmigen/fhdl/cd.py
index 09d930a4dd96b244fefb1ecc2c849cf8878aa018..85c6b71be66aee20097e82349529a2596fabbf3c 100644 (file)
--- a/nmigen/fhdl/cd.py
+++ b/nmigen/fhdl/cd.py
@@ -30,6 +30,14 @@ class ClockDomain:
     rst : Signal or None, inout
         Reset signal for this domain. Can be driven or used to drive.
     """
+
+    @staticmethod
+    def _name_for(domain_name, signal_name):
+        if domain_name == "sync":
+            return signal_name
+        else:
+            return "{}_{}".format(domain_name, signal_name)
+
     def __init__(self, name=None, reset_less=False, async_reset=False):
         if name is None:
             try:
@@ -40,10 +48,16 @@ class ClockDomain:
             name = name[3:]
         self.name = name
 
-        self.clk = Signal(name=self.name + "_clk", src_loc_at=1)
+        self.clk = Signal(name=self._name_for(name, "clk"), src_loc_at=1)
         if reset_less:
             self.rst = None
         else:
-            self.rst = Signal(name=self.name + "_rst", src_loc_at=1)
+            self.rst = Signal(name=self._name_for(name, "rst"), src_loc_at=1)
 
         self.async_reset = async_reset
+
+    def rename(self, name):
+        self.name = name
+        self.clk.name = self._name_for(name, "clk")
+        if self.rst is not None:
+            self.rst.name = self._name_for(name, "rst")

diff --git a/nmigen/fhdl/xfrm.py b/nmigen/fhdl/xfrm.py
index 2c74e433cff63226fbb12d34e29c04c96302f058..c32083e0d0edf450af0a28770dd6071aceb67594 100644 (file)
--- a/nmigen/fhdl/xfrm.py
+++ b/nmigen/fhdl/xfrm.py
@@ -153,7 +153,7 @@ class DomainRenamer(FragmentTransformer, ValueTransformer, StatementTransformer)
             if domain in self.domain_map:
                 if cd.name == domain:
                     # Rename the actual ClockDomain object.
-                    cd.name = self.domain_map[domain]
+                    cd.rename(self.domain_map[domain])
                 else:
                     assert cd.name == self.domain_map[domain]
             new_fragment.add_domains(cd)

diff --git a/nmigen/test/test_fhdl_cd.py b/nmigen/test/test_fhdl_cd.py
index 8b453dea001b1d9aebc03630ab0f705f59f37b6c..2ec8fb6e7bc065d5fc838244a9ba8d7c95609a90 100644 (file)
--- a/nmigen/test/test_fhdl_cd.py
+++ b/nmigen/test/test_fhdl_cd.py
@@ -4,8 +4,14 @@ from .tools import *
 
 class ClockDomainCase(FHDLTestCase):
     def test_name(self):
+        sync = ClockDomain()
+        self.assertEqual(sync.name, "sync")
+        self.assertEqual(sync.clk.name, "clk")
+        self.assertEqual(sync.rst.name, "rst")
         pix = ClockDomain()
         self.assertEqual(pix.name, "pix")
+        self.assertEqual(pix.clk.name, "pix_clk")
+        self.assertEqual(pix.rst.name, "pix_rst")
         cd_pix = ClockDomain()
         self.assertEqual(pix.name, "pix")
         dom = [ClockDomain("foo")][0]
@@ -31,3 +37,13 @@ class ClockDomainCase(FHDLTestCase):
         self.assertIsNotNone(pix.clk)
         self.assertIsNotNone(pix.rst)
         self.assertTrue(pix.async_reset)
+
+    def test_rename(self):
+        sync = ClockDomain()
+        self.assertEqual(sync.name, "sync")
+        self.assertEqual(sync.clk.name, "clk")
+        self.assertEqual(sync.rst.name, "rst")
+        sync.rename("pix")
+        self.assertEqual(sync.name, "pix")
+        self.assertEqual(sync.clk.name, "pix_clk")
+        self.assertEqual(sync.rst.name, "pix_rst")