(no commit message)

diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index 6b367e1beaeae5647656b80ed77d5b78a7247487..db96851bce6461ff066704a5e562e0c6596bc657 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -227,7 +227,8 @@ Summary so far:
 * failfirst needs to be an illegal exception if all-scalar
 * non-zeroing predication on all-scalar with VL>1 requires
   all relevant bits to be set, this changes to the **first**
-  bit for auto-VL=1
+  bit for auto-VL=1.  requires an extra reduction instruction.
+* sv.branches should not be touched. at all.
 
 ## answers to 2, RM Modes