transport: remove dma_setup and pio_setup_d2h (not needed our controller)

diff --git a/lib/sata/std.py b/lib/sata/std.py
index 038f8d1bb0d86b719efe088faca88bcb9a245b0e..971f0b46455eacd41f5475941424f05c691b28c2 100644 (file)
--- a/lib/sata/std.py
+++ b/lib/sata/std.py
@@ -52,10 +52,7 @@ def transport_tx_layout(dw):
        layout = [
                ("type", 8),
                ("pm_port", 4),
-               ("a", 1),
                ("c", 1),
-               ("d", 1),
-               ("i", 1),
                ("command", 8),
                ("features", 16),
                ("lba", 48),
@@ -63,9 +60,6 @@ def transport_tx_layout(dw):
                ("count", 16),
                ("icc", 8),
                ("control", 8),
-               ("dma_buffer_id", 64),
-               ("dma_buffer_offset", 32),
-               ("dma_transfer_count", 32),
                ("data", dw)
        ]
        return EndpointDescription(layout, packetized=True)
@@ -74,19 +68,32 @@ def transport_rx_layout(dw):
        layout = [
                ("type", 8),
                ("pm_port", 4),
-               ("a", 1),
-               ("d", 1),
                ("i", 1),
                ("status", 8),
                ("error", 8),
                ("lba", 48),
                ("device", 8),
                ("count", 16),
-               ("e_status", 8),
-               ("transfer_count", 16),
-               ("dma_buffer_id", 64),
-               ("dma_buffer_offset", 32),
-               ("dma_transfer_count", 32),
+               ("data", dw)
+       ]
+       return EndpointDescription(layout, packetized=True)
+
+def command_tx_layout(dw):
+       layout = [
+               ("write", 1),
+               ("read", 1),
+               ("address", 32),
+               ("length", 32),
+               ("data", dw)
+       ]
+       return EndpointDescription(layout, packetized=True)
+
+def command_rx_layout(dw):
+       layout = [
+               ("write", 1),
+               ("read", 1),
+               ("success", 1),
+               ("failed", 1),
                ("data", dw)
        ]
        return EndpointDescription(layout, packetized=True)

diff --git a/lib/sata/test/bfm.py b/lib/sata/test/bfm.py
index 1b07705549b196d696df95bf84aa6359526c2947..6a2ea910c5676008013c886006166ee397923294 100644 (file)
--- a/lib/sata/test/bfm.py
+++ b/lib/sata/test/bfm.py
@@ -311,15 +311,6 @@ class FIS_DMA_ACTIVATE_D2H(FIS):
                r += FIS.__repr__(self)
                return r
 
-class FIS_DMA_SETUP(FIS):
-       def __init__(self, packet=[0]*fis_dma_setup_cmd_len):
-               FIS.__init__(self, packet,fis_dma_setup_layout)
-
-       def __repr__(self):
-               r = "FIS_DMA_SETUP\n"
-               r += FIS.__repr__(self)
-               return r
-
 class FIS_DATA(FIS):
        def __init__(self, packet=[0]):
                FIS.__init__(self, packet,fis_data_layout)
@@ -331,15 +322,6 @@ class FIS_DATA(FIS):
                        r += "%08x\n" %data
                return r
 
-class FIS_PIO_SETUP_D2H(FIS):
-       def __init__(self, packet=[0]*fis_pio_setup_d2h_cmd_len):
-               FIS.__init__(self, packet,fis_pio_setup_d2h_layout)
-
-       def __repr__(self):
-               r = "FIS_PIO_SETUP\n"
-               r += FIS.__repr__(self)
-               return r
-
 class FIS_UNKNOWN(FIS):
        def __init__(self, packet=[0]):
                FIS.__init__(self, packet, {})
@@ -366,12 +348,8 @@ class TransportLayer(Module):
                        fis = FIS_REG_D2H(packet)
                elif fis_type == fis_types["DMA_ACTIVATE_D2H"]:
                        fis = FIS_DMA_ACTIVATE_D2H(packet)
-               elif fis_type == fis_types["DMA_SETUP"]:
-                       fis = FIS_DMA_SETUP(packet)
                elif fis_type == fis_types["DATA"]:
                        fis = FIS_DATA(packet)
-               elif fis_type == fis_types["PIO_SETUP_D2H"]:
-                       fis = FIS_PIO_SETUP_D2H(packet)
                else:
                        fis = FIS_UNKNOWN(packet)
                if self.debug:

diff --git a/lib/sata/test/transport_tb.py b/lib/sata/test/transport_tb.py
index 699f359d08057688fad7f54cd25131ba637f031e..392dbdbdc00e972fa78e4cbe0f10715a1069628e 100644 (file)
--- a/lib/sata/test/transport_tb.py
+++ b/lib/sata/test/transport_tb.py
@@ -27,14 +27,6 @@ class TB(Module):
                selfp.transport.sink.type = fis_types["REG_H2D"]
                selfp.transport.sink.lba = 0x0123456789
                yield
-               while selfp.transport.sink.ack == 0:
-                       yield
-               selfp.transport.sink.stb = 1
-               selfp.transport.sink.sop = 1
-               selfp.transport.sink.eop = 1
-               selfp.transport.sink.type = fis_types["DMA_SETUP"]
-               selfp.transport.sink.dma_buffer_id = 0x0123456789ABCDEF
-               yield
                while selfp.transport.sink.ack == 0:
                        yield
 

diff --git a/lib/sata/transport/__init__.py b/lib/sata/transport/__init__.py
index d21ff523ec55f87ee35fc5f6a1b906e5a3ae0be3..705591ba58cf36d0d96fb7be248e0fadb66971e6 100644 (file)
--- a/lib/sata/transport/__init__.py
+++ b/lib/sata/transport/__init__.py
@@ -24,7 +24,7 @@ class SATATransportTX(Module):
 
                ###
 
-               cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_dma_setup_cmd_len, fis_data_cmd_len)
+               cmd_ndwords = max(fis_reg_h2d_cmd_len, fis_data_cmd_len)
                encoded_cmd = Signal(cmd_ndwords*32)
 
                cnt = Signal(max=cmd_ndwords+1)
@@ -49,8 +49,6 @@ class SATATransportTX(Module):
                        If(sink.stb & sink.sop,
                                If(test_type("REG_H2D"),
                                        NextState("SEND_REG_H2D_CMD")
-                               ).Elif(test_type("DMA_SETUP"),
-                                       NextState("SEND_DMA_SETUP_CMD")
                                ).Elif(test_type("DATA"),
                                        NextState("SEND_DATA_CMD")
                                ).Else(
@@ -69,15 +67,6 @@ class SATATransportTX(Module):
                                NextState("IDLE")
                        )
                )
-               fsm.act("SEND_DMA_SETUP_CMD",
-                       _encode_cmd(sink, fis_dma_setup_layout, encoded_cmd),
-                       cmd_len.eq(fis_dma_setup_cmd_len),
-                       cmd_send.eq(1),
-                       If(cmd_done,
-                               sink.ack.eq(1),
-                               NextState("IDLE")
-                       )
-               )
                fsm.act("SEND_DATA_CMD",
                        _encode_cmd(sink, fis_data_layout, encoded_cmd),
                        cmd_len.eq(fis_data_cmd_len),
@@ -142,8 +131,7 @@ class SATATransportRX(Module):
 
                ###
 
-               cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len, fis_dma_setup_cmd_len,
-                                               fis_data_cmd_len, fis_pio_setup_d2h_cmd_len)
+               cmd_ndwords = max(fis_reg_d2h_cmd_len, fis_dma_activate_d2h_cmd_len, fis_data_cmd_len)
                encoded_cmd = Signal(cmd_ndwords*32)
 
                cnt = Signal(max=cmd_ndwords+1)
@@ -169,12 +157,8 @@ class SATATransportRX(Module):
                                        NextState("RECEIVE_REG_D2H_CMD")
                                ).Elif(test_type("DMA_ACTIVATE_D2H"),
                                        NextState("RECEIVE_DMA_ACTIVATE_D2H_CMD")
-                               ).Elif(test_type("DMA_SETUP"),
-                                       NextState("RECEIVE_DMA_SETUP_CMD"),
                                ).Elif(test_type("DATA"),
                                        NextState("RECEIVE_DATA_CMD"),
-                               ).Elif(test_type("PIO_SETUP_D2H"),
-                                       NextState("RECEIVE_PIO_SETUP_D2H_CMD"),
                                ).Else(
                                        # XXX: Better to ack?
                                        link.source.ack.eq(1)
@@ -211,20 +195,6 @@ class SATATransportRX(Module):
                                NextState("IDLE")
                        )
                )
-               fsm.act("RECEIVE_DMA_SETUP_CMD",
-                       cmd_len.eq(fis_dma_setup_cmd_len),
-                       cmd_receive.eq(1),
-                       If(cmd_done,
-                               NextState("PRESENT_DMA_SETUP_CMD")
-                       )
-               )
-               fsm.act("PRESENT_DMA_SETUP_CMD",
-                       source.stb.eq(1),
-                       _decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout, source),
-                       If(source.ack,
-                               NextState("IDLE")
-                       )
-               )
                fsm.act("RECEIVE_DATA_CMD",
                        cmd_len.eq(fis_data_cmd_len),
                        cmd_receive.eq(1),
@@ -238,25 +208,11 @@ class SATATransportRX(Module):
                        _decode_cmd(encoded_cmd, fis_data_layout, source),
                        source.sop.eq(0), # XXX
                        source.eop.eq(link.source.eop),
-                       source.d.eq(link.source.d),
+                       source.data.eq(link.source.d),
                        If(source.stb & source.eop & source.ack,
                                NextState("IDLE")
                        )
                )
-               fsm.act("RECEIVE_PIO_SETUP_D2H_CMD",
-                       cmd_len.eq(fis_pio_setup_d2h_cmd_len),
-                       cmd_receive.eq(1),
-                       If(cmd_done,
-                               NextState("PRESENT_PIO_SETUP_D2H_CMD")
-                       )
-               )
-               fsm.act("PRESENT_PIO_SETUP_D2H_CMD",
-                       source.stb.eq(1),
-                       _decode_cmd(encoded_cmd, fis_pio_setup_d2h_layout, source),
-                       If(source.ack,
-                               NextState("IDLE")
-                       )
-               )
 
                cmd_cases = {}
                for i in range(cmd_ndwords):

diff --git a/lib/sata/transport/std.py b/lib/sata/transport/std.py
index aae053b0300427c24ec2728890596b72f1c22225..b8f53f6e3a9cba3256abdd099850a994a7d06040 100644 (file)
--- a/lib/sata/transport/std.py
+++ b/lib/sata/transport/std.py
@@ -2,9 +2,7 @@ fis_types = {
        "REG_H2D":          0x27,
        "REG_D2H":          0x34,
        "DMA_ACTIVATE_D2H": 0x39,
-       "DMA_SETUP":        0x41,
-       "DATA":             0x46,
-       "PIO_SETUP_D2H":    0x5F
+       "DATA":             0x46
 }
 
 class FISField():
@@ -54,44 +52,7 @@ fis_dma_activate_d2h_layout = {
        "pm_port": FISField(0,  8, 4)
 }
 
-fis_dma_setup_cmd_len = 7
-fis_dma_setup_layout = {
-       "type":               FISField(0,  0, 8),
-       "pm_port":            FISField(0,  8, 4),
-       "d":                  FISField(0, 13, 1),
-       "i":                  FISField(0, 14, 1),
-       "a":                  FISField(0, 15, 1),
-
-       "dma_buffer_id_lsb":  FISField(1, 0, 32),
-
-       "dma_buffer_id_msb": FISField(2, 0, 32),
-
-       "dma_buffer_offset":  FISField(4, 0, 32),
-
-       "dma_transfer_count": FISField(4, 0, 32)
-}
-
 fis_data_cmd_len = 1
 fis_data_layout = {
        "type": FISField(0,  0, 8)
 }
-
-fis_pio_setup_d2h_cmd_len = 5
-fis_pio_setup_d2h_layout = {
-       "type":           FISField(0,  0, 8),
-       "pm_port":        FISField(0,  8, 4),
-       "d":              FISField(0, 13, 1),
-       "i":              FISField(0, 14, 1),
-       "status":         FISField(0, 16, 8),
-       "error":          FISField(0, 24, 8),
-
-       "lba_lsb":        FISField(1, 0, 24),
-       "device":         FISField(1, 24, 8),
-
-       "lba_msb":        FISField(2, 0, 24),
-
-       "count":          FISField(3, 0, 16),
-       "e_status":       FISField(3, 24, 8),
-
-       "transfer_count": FISField(4, 0, 16)
-}