boards/targets/ulx3s: reduce l2_size

diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 0574aa7939ad374592500754c1436773c76a0e87..1e1a300634854ca202edb2b96aca9c73ddff3095 100755 (executable)
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -52,6 +52,7 @@ class BaseSoC(SoCSDRAM):
         platform = ulx3s.Platform(toolchain="prjtrellis")
         sys_clk_freq = int(25e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
+                          l2_size=32,
                           integrated_rom_size=0x8000,
                           **kwargs)