radv: factor out si_emit_wait_fence code.

This code was in a few places, consolidate into one.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2ed93564b96a070dc04c5cfd19564135f5a56eb3..c4d3d7bde797eb7e807a5368e7fb0c1e2b8ca207 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3297,14 +3297,7 @@ void radv_CmdWaitEvents(VkCommandBuffer commandBuffer,
 
                MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);
 
-               radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
-               radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
-               radeon_emit(cs, va);
-               radeon_emit(cs, va >> 32);
-               radeon_emit(cs, 1); /* reference value */
-               radeon_emit(cs, 0xffffffff); /* mask */
-               radeon_emit(cs, 4); /* poll interval */
-
+               si_emit_wait_fence(cs, va, 1, 0xffffffff);
                assert(cmd_buffer->cs->cdw <= cdw_max);
        }
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index a6db5cd4ae0e38621ae63bf54c3f0da76dbdf9e4..54bec4bd659c9da9b46b5bbdc58fc8cb057b5695 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -838,6 +838,9 @@ void si_write_scissors(struct radeon_winsys_cs *cs, int first,
 uint32_t si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
                                   bool instanced_draw, bool indirect_draw,
                                   uint32_t draw_vertex_count);
+void si_emit_wait_fence(struct radeon_winsys_cs *cs,
+                       uint64_t va, uint32_t ref,
+                       uint32_t mask);
 void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs,
                             enum chip_class chip_class,
                             bool is_mec,

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index f79b3e6a313cfb361c3c3c55266dff19adc5dcef..910eedd833cc38ed7094dd0e65bb165657b17310 100644 (file)
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -997,13 +997,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
-                               radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
-                               radeon_emit(cs, avail_va);
-                               radeon_emit(cs, avail_va >> 32);
-                               radeon_emit(cs, 1); /* reference value */
-                               radeon_emit(cs, 0xffffffff); /* mask */
-                               radeon_emit(cs, 4); /* poll interval */
+                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
                        }
                }
                radv_query_shader(cmd_buffer, cmd_buffer->device->meta_state.query.pipeline_statistics_query_pipeline,
@@ -1026,13 +1020,7 @@ void radv_CmdCopyQueryPoolResults(
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;
 
                                /* This waits on the ME. All copies below are done on the ME */
-                               radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
-                               radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
-                               radeon_emit(cs, avail_va);
-                               radeon_emit(cs, avail_va >> 32);
-                               radeon_emit(cs, 1); /* reference value */
-                               radeon_emit(cs, 0xffffffff); /* mask */
-                               radeon_emit(cs, 4); /* poll interval */
+                               si_emit_wait_fence(cs, avail_va, 1, 0xffffffff);
                        }
                        if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
                                uint64_t avail_va = va + pool->availability_offset + 4 * query;

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index d94e23b975f2e38c5f74db2fcec5ebe48ca3478c..3bf1d391cf3ef1ce28dc491a4aa4dab8e70cbcbb 100644 (file)
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -762,6 +762,20 @@ si_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer,
 
 }
 
+void
+si_emit_wait_fence(struct radeon_winsys_cs *cs,
+                  uint64_t va, uint32_t ref,
+                  uint32_t mask)
+{
+       radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
+       radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
+       radeon_emit(cs, va);
+       radeon_emit(cs, va >> 32);
+       radeon_emit(cs, ref); /* reference value */
+       radeon_emit(cs, mask); /* mask */
+       radeon_emit(cs, 4); /* poll interval */
+}
+
 static void
 si_emit_acquire_mem(struct radeon_winsys_cs *cs,
                     bool is_mec,