fcvttg CR0 fields (except SO) are undefined when RT is not written

this can occur even when fp traps are disabled in MSR, so writing
"on exceptions" is incorrect.

diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
index a9c7efaa5be89393de1361776935cbf454863de8..ca1749c2f660143f13de89f43d7130e06d9c97d8 100644 (file)
--- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
+++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn
@@ -590,7 +590,8 @@ if the numerical value of the FP number is not 100% accurately preserved
 (due to truncation or saturation and including when the FP number was
 NaN) then this is considered to be an Integer Overflow condition, and
 CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
-that overflow.
+that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits
+except SO are undefined.
 
 Special Registers altered:
 
@@ -758,7 +759,8 @@ if the numerical value of the FP number is not 100% accurately preserved
 (due to truncation or saturation and including when the FP number was
 NaN) then this is considered to be an Integer Overflow condition, and
 CR0.SO, XER.SO and XER.OV are all set as normal for any GPR instructions
-that overflow.
+that overflow. When `RT` is not written (`vex_flag = 1`), all CR0 bits
+except SO are undefined.
 
 Special Registers altered: