(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index bd7a8df2f94475e7ac6e85e558a54fcfbd975bb9..4aa3abba1cf3231db7733958667745bcb1623d0b 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -537,6 +537,11 @@ can be proposed.  These are:
 
 **ZOLC: Zero-Overhead Loop Control**
 
+Zero-Overhead Looping is the concept of automatically running a set sequence
+of instructions for a predetermined number of times, without requiring
+a branch. This is slightly different from using Power ISA `bc` in `CTR`
+(Counter) Mode, because in ZOLC the branch-back is automatic.
+
 The simplest longest commercially successful deployment of Zero-overhead looping
 has been in Texas Instruments TMS320 DSPs. Up to fourteen sub-instructions
 within the VLIW word may be repeatedly deployed on successive clock