draw_impl(struct fd_context *ctx, const struct pipe_draw_info *info,
struct fd_ringbuffer *ring, unsigned dirty, struct ir3_shader_key key)
{
- fd3_emit_state(ctx, ring, &ctx->prog, dirty, key);
+ fd3_emit_state(ctx, ring, info, &ctx->prog, key, dirty);
if (dirty & FD_DIRTY_VTXBUF)
emit_vertexbufs(ctx, ring, key);
.half_precision = true,
};
- fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
+ fd3_emit_state(ctx, ring, NULL, &ctx->solid_prog, key, dirty);
fd3_emit_vertex_bufs(ring, fd3_shader_variant(ctx->solid_prog.vp, key),
(struct fd3_vertex_buf[]) {{
fd3_clear_binning(ctx, dirty);
/* emit generic state now: */
- fd3_emit_state(ctx, ring, &ctx->solid_prog, dirty, key);
+ fd3_emit_state(ctx, ring, NULL, &ctx->solid_prog, key, dirty);
OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
void
fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
- struct fd_program_stateobj *prog, uint32_t dirty,
- struct ir3_shader_key key)
+ const struct pipe_draw_info *info, struct fd_program_stateobj *prog,
+ struct ir3_shader_key key, uint32_t dirty)
{
struct ir3_shader_variant *vp;
struct ir3_shader_variant *fp;
OUT_RING(ring, val);
}
- if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
+ /* NOTE: since primitive_restart is not actually part of any
+ * state object, we need to make sure that we always emit
+ * PRIM_VTX_CNTL.. either that or be more clever and detect
+ * when it changes.
+ */
+ if (info) {
uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)
->pc_prim_vtx_cntl;
val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
}
+ if (info && info->indexed && info->primitive_restart) {
+ val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
+ }
+
val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
struct ir3_shader_variant *vp,
struct fd3_vertex_buf *vbufs, uint32_t n);
void fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
- struct fd_program_stateobj *prog, uint32_t dirty,
- struct ir3_shader_key key);
+ const struct pipe_draw_info *info, struct fd_program_stateobj *prog,
+ struct ir3_shader_key key, uint32_t dirty);
void fd3_emit_restore(struct fd_context *ctx);
#endif /* FD3_EMIT_H */
case PIPE_CAP_TGSI_TEXCOORD:
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
case PIPE_CAP_CONDITIONAL_RENDER:
- case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_SM3:
return 0;
+ case PIPE_CAP_PRIMITIVE_RESTART:
+ return (screen->gpu_id >= 300) ? 1 : 0;
+
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;