re PR target/28508 (Assembler Error: operand out of range (145 not between -128 and...

PR gcc/28508
* config/m32r/m32r.md (branch_insn): Reduce pc range for short branch.
 (rev_branch_insn): Likewise.

From-SVN: r115773

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6987f9c9b6dafd160dc18314405744352b600f29..31261ce4aac608971047df173c15ed62f270e685 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2006-07-27  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
+
+       PR gcc/28508
+       * config/m32r/m32r.md (branch_insn): Reduce pc range for short
+       branch.
+       (rev_branch_insn): Likewise.
+
 2006-07-27  Jan Hubicka  <jh@suse.cz>
 
        PR rtl-optimization/28071

diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index 9b35d14f74fff3f23d443817cea9971ebf7eec3f..552dd3f0ef343ec916ad7d04519c524c3552364d 100644 (file)
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -1378,15 +1378,16 @@
   return instruction;
 }"
   [(set_attr "type" "branch")
-   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+   ; cf PR gcc/28508
+   ; We use 300/600 instead of 512,1024 to account for inaccurate insn
    ; lengths and insn alignments that are complex to track.
    ; It's not important that we be hyper-precise here.  It may be more
    ; important blah blah blah when the chip supports parallel execution
    ; blah blah blah but until then blah blah blah this is simple and
    ; suffices.
    (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-                                                (const_int 400))
-                                          (const_int 800))
+                                                (const_int 300))
+                                          (const_int 600))
                                      (const_int 2)
                                      (const_int 4)))])
 
@@ -1407,15 +1408,16 @@
   return instruction;
 }"
   [(set_attr "type" "branch")
-   ; We use 400/800 instead of 512,1024 to account for inaccurate insn
+   ; cf PR gcc/28508
+   ; We use 300/600 instead of 512,1024 to account for inaccurate insn
    ; lengths and insn alignments that are complex to track.
    ; It's not important that we be hyper-precise here.  It may be more
    ; important blah blah blah when the chip supports parallel execution
    ; blah blah blah but until then blah blah blah this is simple and
    ; suffices.
    (set (attr "length") (if_then_else (ltu (plus (minus (match_dup 0) (pc))
-                                                (const_int 400))
-                                          (const_int 800))
+                                                (const_int 300))
+                                          (const_int 600))
                                      (const_int 2)
                                      (const_int 4)))])