read_aiger to accept empty string for clk_name, passable only if no latches

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index c8ba1bffdb549ee8097fbff62655ef67f4260128..a64729a2779d811701b450e56228af28755ad83c 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -524,6 +524,7 @@ void AigerReader::parse_aiger_ascii()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
+        log_assert(clk_name != "");
         clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
         log_debug("Creating %s\n", clk_name.c_str());
@@ -654,6 +655,7 @@ void AigerReader::parse_aiger_binary()
     // Parse latches
     RTLIL::Wire *clk_wire = nullptr;
     if (L > 0) {
+        log_assert(clk_name != "");
         clk_wire = module->wire(clk_name);
         log_assert(!clk_wire);
         log_debug("Creating %s\n", clk_name.c_str());

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 90234ea336215b0dba62cfa1a54b8e9273a912f6..68e54f51817bce9ba83332ef951dde30bb8c6843 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -523,8 +523,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                bool builtin_lib = liberty_file.empty();
                RTLIL::Design *mapped_design = new RTLIL::Design;
                //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-               buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
-               AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
+               AigerReader reader(mapped_design, ifs, "\\netlist", "" /* clk_name */, "" /* map_filename */, true /* wideports */);
                reader.parse_xaiger();
 
                ifs.close();