unsigned cb_target_mask;
};
-struct r600_pipe_shader {
- struct r600_shader shader;
- struct r600_pipe_state rstate;
- struct radeon_ws_bo *bo;
-};
-
struct r600_vertex_element
{
unsigned count;
struct pipe_vertex_element elements[32];
};
+struct r600_pipe_shader {
+ struct r600_shader shader;
+ struct r600_pipe_state rstate;
+ struct radeon_ws_bo *bo;
+ struct r600_vertex_element vertex_elements;
+};
+
+
struct r600_pipe_context {
struct pipe_context context;
struct blitter_context *blitter;
if (shader->processor_type != TGSI_PROCESSOR_VERTEX)
return 0;
+ if (!memcmp(&rshader->vertex_elements, rctx->vertex_elements, sizeof(struct r600_vertex_element))) {
+ return 0;
+ }
+ rshader->vertex_elements = *rctx->vertex_elements;
for (i = 0; i < rctx->vertex_elements->count; i++) {
resource_format[nresources++] = rctx->vertex_elements->elements[i].src_format;
}