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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 347a95c1556e2548065dfa2d0a95d0a365e5fd98..f6c88389f57af6dd8456a0d0211104f3ec3dacc5 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -30,7 +30,8 @@ significant apparent speed increases: 3200 mhz DDR4 and even faster DDR5,
 and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI,
 all make an effort (all simply increasing the parallel deployment of
 the underlying 150 mhz bitcells), but these efforts are dwarfed by the
-two nearly three orders of magnitude increase in CPU horsepower. Seymour
+two nearly three orders of magnitude increase in CPU horsepower
+over the same timeframe. Seymour
 Cray, from his amazing in-depth knowledge, predicted that the mismatch
 would become a serious limitation, over two decades ago.  Some systems
 at the time of writing are now approaching a *Gigabyte* of L4 Cache,