Update configs for cpu_id

tests/configs/o3-timing-mp.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
    Update config for cpu_id

--HG--
extra : convert_revision : 32a1971997920473164ba12f2b121cb640bad7ac

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 881c23156af663483101aab7ce835bae6120b1ea..55af8be0dfe9511e16140baee7af471338d8c862 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -54,7 +54,7 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
+cpus = [ DetailedO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
@@ -86,5 +86,5 @@ system.physmem.port = system.membus.port
 
 root = Root( system = system )
 root.system.mem_mode = 'timing'
-root.trace.flags="Bus Cache"
+#root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index cc1a36dda8d2916ec8221c605226123e8c0a12b1..eaa6ec66e42c15b67e72c69afd3b7aaa59627015 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -52,10 +52,10 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ AtomicSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
-system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
+system = System(cpu = cpus, physmem = PhysicalMemory(range = AddrRange('1024MB')), membus =
 Bus())
 
 # l2cache & bus

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 9fc5f3874331a82d8dc8a45fba392cc041fd0599..8f9ab0dde367c52227b7fbe8f3349915c4f711a3 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -52,7 +52,7 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ TimingSimpleCPU() for i in xrange(nb_cores) ]
+cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =