add category descriptions

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 157be782891283815860f559933bf946dc2671a9..478eeb7781a811f46609395c44be7193a1a6dcff 100644 (file)
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -4,7 +4,7 @@ Based on information from Michael Clark's riscv-meta opcodes table, this
 page categorises and identifies the type of parallelism that SimpleV
 indirectly adds on each RISC-V **standard** opcode.
 
-* **-** - no action
+* **-** no action
 * **sv** - a standard contiguous (optionally predicated, optionally
   indirected) multi-register operation where the predication for
   the operation is taken from the **destination** register