re PR target/84876 (ICE on invalid code in lra_assign at gcc/lra-assigns.c:1601 since...

2018-03-16  Vladimir Makarov  <vmakarov@redhat.com>

	PR target/84876
	* lra-assigns.c (lra_split_hard_reg_for): Don't use
	regno_allocno_class_array and sorted_pseudos.
	* lra-constraints.c (spill_hard_reg_in_range): Ignore hard regs in
	insns where regno is used.

2018-03-16  Vladimir Makarov  <vmakarov@redhat.com>

	PR target/84876
	* gcc.target/i386/pr84876.c: New test.

From-SVN: r258602

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 78f492b728cbc0908b7d6585224cd2273c791dbf..b6037d27c80ad9d7fb7376cd5df202c40d8867ca 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2018-03-16  Vladimir Makarov  <vmakarov@redhat.com>
+
+       PR target/84876
+       * lra-assigns.c (lra_split_hard_reg_for): Don't use
+       regno_allocno_class_array and sorted_pseudos.
+       * lra-constraints.c (spill_hard_reg_in_range): Ignore hard regs in
+       insns where regno is used.
+
 2018-03-16  Martin Liska  <mliska@suse.cz>
 
        PR ipa/84833

diff --git a/gcc/lra-assigns.c b/gcc/lra-assigns.c
index 6d16037ab0246f4fe220264e44d1c662bbfd152a..c0e370bbab025f5a9ba8f04ec6776d5c4e7c23ef 100644 (file)
--- a/gcc/lra-assigns.c
+++ b/gcc/lra-assigns.c
@@ -1737,41 +1737,46 @@ find_reload_regno_insns (int regno, rtx_insn * &start, rtx_insn * &finish)
 bool
 lra_split_hard_reg_for (void)
 {
-  int i, regno, n;
+  int i, regno;
   rtx_insn *insn, *first, *last;
   unsigned int u;
   bitmap_iterator bi;
+  enum reg_class rclass;
   int max_regno = max_reg_num ();
   /* We did not assign hard regs to reload pseudos after two
      iterations.  Either it's an asm and something is wrong with the
      constraints, or we have run out of spill registers; error out in
      either case.  */
   bool asm_p = false;
-  bitmap_head failed_reload_insns;
+  bitmap_head failed_reload_insns, failed_reload_pseudos;
   
   if (lra_dump_file != NULL)
     fprintf (lra_dump_file,
             "\n****** Splitting a hard reg after assignment #%d: ******\n\n",
             lra_assignment_iter);
-  for (n = 0, i = lra_constraint_new_regno_start; i < max_regno; i++)
+  bitmap_initialize (&failed_reload_pseudos, &reg_obstack);
+  for (i = lra_constraint_new_regno_start; i < max_regno; i++)
     if (reg_renumber[i] < 0 && lra_reg_info[i].nrefs != 0
-       && regno_allocno_class_array[i] != NO_REGS
+       && (rclass = lra_get_allocno_class (i)) != NO_REGS
        && ! bitmap_bit_p (&non_reload_pseudos, i))
       {
-       sorted_pseudos[n++] = i;
        if (! find_reload_regno_insns (i, first, last))
          continue;
-       if (spill_hard_reg_in_range (i, regno_allocno_class_array[i],
-                                    first, last))
-         return true;
+       if (spill_hard_reg_in_range (i, rclass, first, last))
+         {
+           bitmap_clear (&failed_reload_pseudos);
+           return true;
+         }
+       bitmap_set_bit (&failed_reload_pseudos, i);
       }
   bitmap_initialize (&failed_reload_insns, &reg_obstack);
-  for (i = 0; i < n; i++)
+  EXECUTE_IF_SET_IN_BITMAP (&failed_reload_pseudos, 0, u, bi)
     {
-      regno = sorted_pseudos[i];
+      regno = u;
       bitmap_ior_into (&failed_reload_insns,
                       &lra_reg_info[regno].insn_bitmap);
-      lra_setup_reg_renumber (regno, ira_class_hard_regs[regno_allocno_class_array[regno]][0], false);
+      lra_setup_reg_renumber
+       (regno, ira_class_hard_regs[lra_get_allocno_class (regno)][0], false);
     }
   EXECUTE_IF_SET_IN_BITMAP (&failed_reload_insns, 0, u, bi)
     {
@@ -1805,5 +1810,7 @@ lra_split_hard_reg_for (void)
          fatal_insn ("this is the insn:", insn);
        }
     }
+  bitmap_clear (&failed_reload_pseudos);
+  bitmap_clear (&failed_reload_insns);
   return false;
 }

diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 118b65f6a23c99cbbfb6721595f645fc555150dc..31faefab9c2a083167a0786c3dca819135d41d40 100644 (file)
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -5680,13 +5680,30 @@ spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_i
   int i, hard_regno;
   int rclass_size;
   rtx_insn *insn;
+  unsigned int uid;
+  bitmap_iterator bi;
+  HARD_REG_SET ignore;
   
   lra_assert (from != NULL && to != NULL);
+  CLEAR_HARD_REG_SET (ignore);
+  EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi)
+    {
+      lra_insn_recog_data_t id = lra_insn_recog_data[uid];
+      struct lra_static_insn_data *static_id = id->insn_static_data;
+      struct lra_insn_reg *reg;
+      
+      for (reg = id->regs; reg != NULL; reg = reg->next)
+       if (reg->regno <= FIRST_PSEUDO_REGISTER)
+         SET_HARD_REG_BIT (ignore, reg->regno);
+      for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
+       SET_HARD_REG_BIT (ignore, reg->regno);
+    }
   rclass_size = ira_class_hard_regs_num[rclass];
   for (i = 0; i < rclass_size; i++)
     {
       hard_regno = ira_class_hard_regs[rclass][i];
-      if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno))
+      if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno)
+         || TEST_HARD_REG_BIT (ignore, hard_regno))
        continue;
       for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn))
        if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap,

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e3795cdc8f031663a06cd466c0a61e8d0a16edf6..5d353f4e41f98c8d914a16864188e4810333af8b 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-16  Vladimir Makarov  <vmakarov@redhat.com>
+
+       PR target/84876
+       * gcc.target/i386/pr84876.c: New test.
+
 2018-03-16  Martin Liska  <mliska@suse.cz>
 
        PR ipa/84833

diff --git a/gcc/testsuite/gcc.target/i386/pr84876.c b/gcc/testsuite/gcc.target/i386/pr84876.c
new file mode 100644 (file)
index 0000000..f2d8430
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr84876.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target int128 } } */
+/* { dg-options "-w" } */
+
+__int128 test (__int128 a)
+{
+  asm ("" : "+v" (a) : : "xmm0", "xmm1", "xmm2", "xmm3", /* { dg-error "'asm' operand has impossible constraints" } */
+                        "xmm4", "xmm5", "xmm6", "xmm7",
+                        "xmm8", "xmm9", "xmm10", "xmm11",
+                        "xmm12", "xmm13", "xmm14", "xmm15");
+  return a;
+}