intel/genxml: Add Cache Mode SubSlice Register to gen10.xml

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index a7ae49ae6597b112389332eb94737e33c3aec84b..a6b8f48fda551c72aec3336db941c7650808b4fa 100644 (file)
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3752,4 +3752,16 @@
     <field name="Color Compression Disable Mask" start="31" end="31" type="bool"/>
   </register>
 
+  <register name="CACHE_MODE_SS" length="1" num="0x0e420">
+    <field name="Instruction Level 1 Cache Disable" start="0" end="0" type="bool"/>
+    <field name="Instruction Level 1 Cache and In-Flight Queue Disable " start="1" end="1" type="bool"/>
+    <field name="Float Blend Optimization Enable" start="4" end="4" type="bool"/>
+    <field name="Per Sample Blend Opt Disable"  start="11" end="11" type="bool"/>
+
+    <field name="Instruction Level 1 Cache Disable Mask" start="16" end="16" type="bool"/>
+    <field name="Instruction Level 1 Cache and In-Flight Queue Disable Mask" start="17" end="17" type="bool"/>
+    <field name="Float Blend Optimization Enable Mask" start="20" end="20" type="bool"/>
+    <field name="Per Sample Blend Opt Disable Mask"  start="27" end="27" type="bool"/>
+  </register>
+
 </genxml>