comment out debug code not needed

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index d235ce3bbaa55b02319b5c08e97304381966c97e..64f9fe7aa9fc767e37220add0b35a2b7f9b523f5 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -129,15 +129,14 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #endif
   }
-  // identify which regs have had their CSR entries set as vectorised.
-  // really could do with a macro for-loop here... oh well...
-  // integer ops, RD, RS1, RS2, RS3 (use sv_int_tb)
+#if 0 // useful test at one point...
   if (insn.sv_check_reg(true, 15))
   {
     fprintf(stderr, "reg %s %x rd %ld rs1 %ld rs2 %ld vlen %d\n",
             xstr(INSN), INSNCODE, s_insn.rd(), s_insn.rs1(), s_insn.rs2(),
             vlen);
   }
+#endif
   // if vectorop is set, one of the regs is not a scalar,
   // so we must read the VL CSR and do a loop
   if (vlen == 0)