Fixed "flatten" top-module detection: Only use on fully selected designs

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 7e3ba23ec71aa73f4fe31949faf6abf9bcde56fb..4f9d9c4e4862ed665b89290dce320a420ec0aa96 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -501,9 +501,10 @@ struct FlattenPass : public Pass {
                        celltypeMap[it.first].insert(it.first);
 
                RTLIL::Module *top_mod = NULL;
-               for (auto &mod_it : design->modules)
-                       if (mod_it.second->get_bool_attribute("\\top"))
-                               top_mod = mod_it.second;
+               if (design->full_selection())
+                       for (auto &mod_it : design->modules)
+                               if (mod_it.second->get_bool_attribute("\\top"))
+                                       top_mod = mod_it.second;
 
                bool did_something = true;
                std::set<RTLIL::Cell*> handled_cells;