bit of a mess: attempted to create a complete arithmetic overload

had to back most of it out, and left in a change to the amo* functions
passing in a 2nd parameter to the higher-order-function

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 46d0887e3c762937368f97b3bb2ee1f33a4434e3..c80477ac4e6e2a459a865a54b278c4d8c8279950 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -87,7 +87,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 {
   int xlen = ISASZ;
-  reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
+  reg_t npc = _sext_xlen(pc + insn_length(INSNCODE));
   // messy way to do it: insn_t is used elsewhere in a union,
   // so cannot create virtual functions.
   // a workaround is to grab the bits from the insn_t

diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
index 6090fbc530d078cee63ea31bb78ecf70a1c6a534..009cb213218c1d5b18694ec2341bea31d667d553 100644 (file)
--- a/riscv/insns/amoadd_d.h
+++ b/riscv/insns/amoadd_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs + RS2; }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return lhs + rhs; }));

diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
index 2c6471afbe6e2dcb40fa504c7b4fc77739e72d9f..98bd3edf3cfa39fcd5b80549727d590c79b32be9 100644 (file)
--- a/riscv/insns/amoadd_w.h
+++ b/riscv/insns/amoadd_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs + RS2; })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+                [&](uint32_t lhs, uint32_t rhs) { return lhs + rhs; })));

diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
index 80aea184de5521c64248ded6ff0c2ea79078c6a0..3877e3035b46ca69a6e3bc2c5790d1b0e527eb56 100644 (file)
--- a/riscv/insns/amoand_d.h
+++ b/riscv/insns/amoand_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs & RS2; }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return lhs & rhs; }));

diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
index f7e1ba7c06262b785db4d20ae7a32ab2220f3bb6..fa9e665f9aed2137c307ab80c3f7f8fc1dc2f12a 100644 (file)
--- a/riscv/insns/amoand_w.h
+++ b/riscv/insns/amoand_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs & RS2; })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs) { return lhs & rhs; })));

diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
index 496d8ada9be068e850fc9b0944cbc6e338e8c893..bd798b45bfe6a0f522e201d051b0ce4b17fc97fe 100644 (file)
--- a/riscv/insns/amomax_d.h
+++ b/riscv/insns/amomax_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::max(lhs, int64_t(RS2)); }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](int64_t lhs, uint64_t rhs) { return std::max(lhs, int64_t(rhs)); }));

diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
index 757bdd2ccb7bdab94d6a3fade459acf17f66bd2d..80cc527e209342dcf1b77f118676f270443f81b8 100644 (file)
--- a/riscv/insns/amomax_w.h
+++ b/riscv/insns/amomax_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::max(lhs, int32_t(RS2)); })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](int32_t lhs, int32_t rhs) { return std::max(lhs, int32_t(rhs)); })));

diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
index 12b173313d9e4f1636e13a67fea6785fbae8f8ae..7f6f2522a4ac2c759f1c245be14ae35e64d20633 100644 (file)
--- a/riscv/insns/amomaxu_d.h
+++ b/riscv/insns/amomaxu_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::max(lhs, RS2); }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return (lhs > rhs) ? lhs : rhs; }));

diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
index 538df1c40077dda756ae3b66813f92e5fde0a6d2..62c51102fe9162065cbe33c4a8fddcef04a27afb 100644 (file)
--- a/riscv/insns/amomaxu_w.h
+++ b/riscv/insns/amomaxu_w.h
@@ -1,2 +1,4 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::max(lhs, uint32_t(RS2)); })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs)
+         { return std::max(lhs, uint32_t(rhs)); })));

diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
index 725d9839f8f186aeaec31481cb15fa71fbe72f47..2837cdf52e37c74d06604b25c0ae8471581d0db1 100644 (file)
--- a/riscv/insns/amomin_d.h
+++ b/riscv/insns/amomin_d.h
@@ -1,3 +1,5 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](int64_t lhs) { return std::min(lhs, int64_t(RS2)); }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](int64_t lhs, uint64_t rhs)
+         { return std::min(lhs, int64_t(rhs)); }));

diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
index ee53faa0cd61cad91f5dfaa5d59faaf1cc368ea3..87176d11f9a141dab528fde5475ecd612b24b935 100644 (file)
--- a/riscv/insns/amomin_w.h
+++ b/riscv/insns/amomin_w.h
@@ -1,2 +1,4 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](int32_t lhs) { return std::min(lhs, int32_t(RS2)); })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](int32_t lhs, int32_t rhs)
+         { return std::min(lhs, int32_t(rhs)); })));

diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
index 15b6c0a48bad12e9cafd9738fe7481bc933eb974..1bef71c8a6b3a68f92920cbcf0c74ae8681f494e 100644 (file)
--- a/riscv/insns/amominu_d.h
+++ b/riscv/insns/amominu_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return std::min(lhs, RS2); }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return (lhs < rhs) ? lhs : rhs; }));

diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
index 52e1141b87cd9cce8945e9394bc3bbce7b543d06..c4a55534fd302e612ef1311b4d75af012563a05b 100644 (file)
--- a/riscv/insns/amominu_w.h
+++ b/riscv/insns/amominu_w.h
@@ -1,2 +1,4 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return std::min(lhs, uint32_t(RS2)); })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs)
+         { return std::min(lhs, uint32_t(rhs)); })));

diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
index de8762745b3768a66be72da7c2bbcfc9d6d32b3f..dfcae38545330f21ff1844c3a2ab8dc06d3a4aca 100644 (file)
--- a/riscv/insns/amoor_d.h
+++ b/riscv/insns/amoor_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs | RS2; }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return lhs | rhs; }));

diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
index 3455981d86944802bdea0afae5689e05b7c28de2..ae14a2f02a1a805217ee45847d00a01207fac3a2 100644 (file)
--- a/riscv/insns/amoor_w.h
+++ b/riscv/insns/amoor_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs | RS2; })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs) { return lhs | rhs; })));

diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
index e1bffdeb5cdda44cbc0e9b64f4602bec5eaf1632..b79f0e307b4f249b961d1d155c426797d6b4b9f8 100644 (file)
--- a/riscv/insns/amoswap_d.h
+++ b/riscv/insns/amoswap_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return RS2; }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return rhs; }));

diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
index 0f78369c76eeccec56f4c7e3d48d3687245b2839..94fc2be2aad3cbbb51f06f93faa0dcd4014b03a0 100644 (file)
--- a/riscv/insns/amoswap_w.h
+++ b/riscv/insns/amoswap_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return RS2; })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs) { return rhs; })));

diff --git a/riscv/insns/amoxor_d.h b/riscv/insns/amoxor_d.h
index 1b3c0bf41fb9262a6fd2330772e54029770e3e04..412ecbd778d7d70320258f2c6824a70864d9fd91 100644 (file)
--- a/riscv/insns/amoxor_d.h
+++ b/riscv/insns/amoxor_d.h
@@ -1,3 +1,4 @@
 require_extension('A');
 require_rv64;
-WRITE_RD(MMU.amo_uint64(RS1, [&](uint64_t lhs) { return lhs ^ RS2; }));
+WRITE_RD(MMU.amo_uint64(RS1, RS2,
+         [&](uint64_t lhs, uint64_t rhs) { return lhs ^ rhs; }));

diff --git a/riscv/insns/amoxor_w.h b/riscv/insns/amoxor_w.h
index a1ea82f1d83b9f71e882770915d8c253dbf16e33..8274fde9ca35fb01453f1571514648e96572825a 100644 (file)
--- a/riscv/insns/amoxor_w.h
+++ b/riscv/insns/amoxor_w.h
@@ -1,2 +1,3 @@
 require_extension('A');
-WRITE_RD(sext32(MMU.amo_uint32(RS1, [&](uint32_t lhs) { return lhs ^ RS2; })));
+WRITE_RD(sext32(MMU.amo_uint32(RS1, RS2,
+         [&](uint32_t lhs, uint32_t rhs) { return lhs ^ rhs; })));

diff --git a/riscv/mmu.h b/riscv/mmu.h
index f66eb00fd6d6fb0556d62532a47271f0ce1ffbb9..3f111a3729f4b0c46682ff091c5d9aa7e03bd4ec 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -135,12 +135,12 @@ public:
   // template for functions that perform an atomic memory operation
   #define amo_func(type) \
     template<typename op> \
-    type##_t amo_##type(reg_t addr, op f) { \
+    type##_t amo_##type(reg_t addr, reg_t rhs, op f) { \
       if (addr & (sizeof(type##_t)-1)) \
         throw trap_store_address_misaligned(addr); \
       try { \
         auto lhs = load_##type(addr); \
-        store_##type(addr, f(lhs)); \
+        store_##type(addr, f(lhs, rhs)); \
         return lhs; \
       } catch (trap_load_page_fault& t) { \
         /* AMO faults should be reported as store faults */ \

diff --git a/riscv/processor.h b/riscv/processor.h
index 80d33b6284b710151f164ca4f55775c0e8391d85..1ffdfab6f2512c96ba3a831a08fdc62191fa2251 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -11,8 +11,8 @@
 #include <map>
 #include "debug_rom_defines.h"
 #ifdef SPIKE_SIMPLEV
-#include "sv_decode.h"
 #include "sv_insn_redirect.h"
+#include "sv_decode.h"
 #endif
 
 class processor_t;

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index adbb0d66a16056de61047626248ab47fe05f33f6..b2b73a4a4c2b81ecfca0d555b70b514faf534fcf 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -5,6 +5,7 @@
 
 #include "sv.h"
 #include "decode.h"
+//#include "sv_reg.h"
 //#include "processor.h"
 
 #define REG_RD 0x1
@@ -33,6 +34,10 @@ public:
             prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3),
             save_branch_addr(0) {}
 
+  uint64_t rvc_imm() { return (insn_t::rvc_imm()); }
+  uint64_t u_imm() { return (insn_t::u_imm()); }
+  uint64_t i_imm() { return (insn_t::i_imm()); }
+  uint64_t s_imm() { return (insn_t::s_imm()); }
   uint64_t _rvc_spoffs_imm(uint64_t elwidth, uint64_t baseoffs);
   uint64_t rvc_lwsp_imm() { return _rvc_spoffs_imm(4, insn_t::rvc_lwsp_imm()); }
   uint64_t rvc_ldsp_imm() { return _rvc_spoffs_imm(8, insn_t::rvc_ldsp_imm()); }

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 07eb84f3c1eaf345e9ff27f415da606c9571290a..02edba51b015ff80dbb5ce0552fc2aa0ce454f6c 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -19,16 +19,23 @@ void (sv_proc_t::WRITE_FRD)(freg_t value)
     DO_WRITE_FREG( _insn->rd(), freg(value) );
 }
 
+/*
 void (sv_proc_t::WRITE_RD)(bool value)
 {
     WRITE_REG( _insn->rd(), value ? 1 : 0);
 }
-
 void (sv_proc_t::WRITE_RD)(sv_reg_t value)
 {
     WRITE_REG( _insn->rd(), value.get_data() );
 }
+*/
+
+void (sv_proc_t::WRITE_RD)(uint64_t value)
+{
+    WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly
+}
 
+/*
 void (sv_proc_t::WRITE_RD)(int_fast64_t value)
 {
     WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly
@@ -38,6 +45,7 @@ void (sv_proc_t::WRITE_RD)(uint_fast64_t value)
 {
     WRITE_REG( _insn->rd(), value ); // XXX TODO: replace properly
 }
+*/
 
 /*
 reg_t (sv_proc_t::READ_REG)(uint64_t i)
@@ -46,82 +54,94 @@ reg_t (sv_proc_t::READ_REG)(uint64_t i)
 }
 */
 
-sv_reg_t sv_proc_t::get_rs1()
+reg_t sv_proc_t::get_rs1()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs1()]);
+    return (_insn->p->get_state()->XPR[_insn->rs1()]);
 }
 
-sv_reg_t sv_proc_t::get_rs2()
+reg_t sv_proc_t::get_rs2()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs2()]);
+    return (_insn->p->get_state()->XPR[_insn->rs2()]);
 }
 
-sv_reg_t sv_proc_t::get_rvc_rs1s()
+reg_t sv_proc_t::get_rvc_rs1s()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs1s()]);
+    return (_insn->p->get_state()->XPR[_insn->rvc_rs1s()]);
 }
 
-sv_reg_t sv_proc_t::get_rvc_rs2s()
+reg_t sv_proc_t::get_rvc_rs2s()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs2s()]);
+    return (_insn->p->get_state()->XPR[_insn->rvc_rs2s()]);
 }
 
-sv_reg_t sv_proc_t::get_rvc_rs1()
+reg_t sv_proc_t::get_rvc_rs1()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs1()]);
+    return (_insn->p->get_state()->XPR[_insn->rvc_rs1()]);
 }
 
-sv_reg_t sv_proc_t::get_rvc_rs2()
+reg_t sv_proc_t::get_rvc_rs2()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rvc_rs2()]);
+    return (_insn->p->get_state()->XPR[_insn->rvc_rs2()]);
 }
 
-sv_reg_t sv_proc_t::get_rs3()
+reg_t sv_proc_t::get_rs3()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[_insn->rs3()]);
+    return (_insn->p->get_state()->XPR[_insn->rs3()]);
 }
 
-sv_reg_t sv_proc_t::get_rvc_sp()
+reg_t sv_proc_t::get_rvc_sp()
 {
-    return sv_uint64_t(_insn->p->get_state()->XPR[X_SP]);
+    return (_insn->p->get_state()->XPR[X_SP]);
 }
 
-sv_reg_t sv_proc_t::uint64_max()
+reg_t sv_proc_t::uint64_max()
 {
-    return sv_uint64_t((UINT64_C(18446744073709551615)));
+    return ((UINT64_C(18446744073709551615)));
 }
 
-sv_reg_t (sv_proc_t::sext_xlen)(sv_reg_t v)
+/*
+reg_t (sv_proc_t::sext_xlen)(uint64_t x)
 {
-    uint64_t x = v.as_uint64();
     x = (((sreg_t)(x) << (64-xlen)) >> (64-xlen));
     return sv_uint64_t(x);
 }
+*/
+reg_t (sv_proc_t::sext_xlen)(reg_t x)
+{
+    //uint64_t x = v.as_uint64();
+    x = (((sreg_t)(x) << (64-xlen)) >> (64-xlen));
+    return x;
+    //return sv_uint64_t(x);
+}
 
-sv_reg_t (sv_proc_t::zext_xlen)(sv_reg_t v)
+reg_t (sv_proc_t::zext_xlen)(reg_t x)
 {
-    uint64_t x = v.as_uint64();
+    //uint64_t x = v.as_uint64();
     x = (((reg_t)(x) << (64-xlen)) >> (64-xlen));
-    return sv_uint64_t(x);
+    return x;
+    //return sv_uint64_t(x);
 }
 
-sv_reg_t (sv_proc_t::sext32)(uint_fast32_t v)
+/*
+reg_t (sv_proc_t::sext32)(uint_fast32_t v)
 {
     return sext32((uint64_t)v); // XXX TODO do properly
 }
-
-sv_reg_t (sv_proc_t::sext32)(sv_reg_t v)
+*/
+reg_t (sv_proc_t::sext32)(reg_t x)
 {
-    uint64_t x = v.as_uint64();
+    //uint64_t x = v.as_uint64();
     x = ((sreg_t)(int32_t)(x));
-    return sv_uint64_t(x);
+    return x;
+    //return sv_uint64_t(x);
 }
 
-sv_reg_t (sv_proc_t::zext32)(sv_reg_t v)
+reg_t (sv_proc_t::zext32)(reg_t x)
 {
-    uint64_t x = v.as_uint64();
+    //uint64_t x = v.as_uint64();
     x = ((reg_t)(uint32_t)(x));
-    return sv_uint64_t(x);
+    return x;
+    //return sv_uint64_t(x);
 }
 
 freg_t sv_proc_t::get_frs1()
@@ -134,6 +154,7 @@ freg_t sv_proc_t::get_frs2()
     return READ_FREG(_insn->rs2());
 }
 
+/*
 sv_reg_t sv_reg_t::make_sv_int64_t (int64_t v) const
 {
     return sv_sreg_t(v);
@@ -145,8 +166,54 @@ sv_reg_t sv_reg_t::make_sv_uint64_t (uint64_t v) const
 }
 
 
-sv_reg_t::operator sv_sreg_t () const
+sv_reg_t::operator sv_sreg_t ()
 {
     return sv_sreg_t ( as_uint64() );
 }
 
+sv_reg_t::operator int32_t ()
+{
+    uint64_t x = get_data();
+    sreg_t _x = (sreg_t) x;
+    sv_sreg_t y = sv_sreg_t ( _x );
+    return y;
+}
+
+
+sv_reg_t::operator uint16_t ()
+{
+    uint64_t x = get_data();
+    uint16_t _x = (uint16_t) x;
+    sv_uint16_t y = sv_uint16_t ( _x );
+    return y;
+}
+
+
+sv_reg_t::operator uint8_t () // XXX TODO, make_sv_char_t
+{
+    uint64_t x = get_data();
+    uint8_t _x = (uint8_t) x;
+    sv_uint64_t y = sv_uint64_t ( _x );
+    return y;
+}
+
+sv_reg_t::operator char () // XXX TODO, make_sv_char_t
+{
+    uint64_t x = get_data();
+    char _x = (char) x;
+    sv_sreg_t y = sv_sreg_t ( _x );
+    return y;
+}
+
+sv_reg_t::operator uint32_t () // TODO, make_sv_uint32_t
+        { return make_sv_uint64_t( (sreg_t) (as_uint64()) ); }
+sv_reg_t::operator sreg_t ()
+        { return make_sv_int64_t( (sreg_t) (as_uint64()) ); }
+
+sv_reg_t::operator reg_t ()
+{
+    uint64_t x = get_data();
+    sv_uint64_t y = sv_uint64_t ( x );
+    return y;
+}
+*/

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index 158e42f17a9f2b3c0d9e0a9e9d5ca03da0b269c9..29f680dc74788bcec7a1383dcca6fddf44a8b519 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -4,7 +4,7 @@
 #include <stdio.h>
 #include "decode.h"
 #include "sv_decode.h"
-#include "sv_reg.h"
+//#include "sv_reg.h"
 
 #undef RS1
 #undef RS2
@@ -43,10 +43,11 @@ class sv_proc_t
 {
 public:
     sv_proc_t(processor_t *_p) : p(_p), _insn(NULL), xlen(0) {}
-    void (WRITE_RD)(bool value); // f32_eq calls this: XXX TODO investigate
-    void (WRITE_RD)(sv_reg_t value);
-    void (WRITE_RD)(int_fast64_t value); // XXX TODO investigate
-    void (WRITE_RD)(uint_fast64_t value); // XXX TODO investigate
+    //void (WRITE_RD)(bool value); // f32_eq calls this: XXX TODO investigate
+    //void (WRITE_RD)(sv_reg_t &value);
+    //void (WRITE_RD)(int_fast64_t value); // XXX TODO investigate
+    //void (WRITE_RD)(uint_fast64_t value); // XXX TODO investigate
+    void (WRITE_RD)(uint64_t value); // XXX TODO investigate
     void (WRITE_FRD)(freg_t value);
     void (WRITE_FRD)(float64_t value);
     void (WRITE_FRD)(float32_t value);
@@ -70,27 +71,28 @@ public:
         this->insn._insn = i;
     }
 
-    sv_reg_t get_rs1();
-    sv_reg_t get_rs2();
-    sv_reg_t get_rs3();
+    reg_t get_rs1();
+    reg_t get_rs2();
+    reg_t get_rs3();
 
-    sv_reg_t get_rvc_sp();
-    sv_reg_t get_rvc_rs1();
-    sv_reg_t get_rvc_rs2();
-    sv_reg_t get_rvc_rs1s();
-    sv_reg_t get_rvc_rs2s();
+    reg_t get_rvc_sp();
+    reg_t get_rvc_rs1();
+    reg_t get_rvc_rs2();
+    reg_t get_rvc_rs1s();
+    reg_t get_rvc_rs2s();
 
-    sv_reg_t uint64_max();
+    reg_t uint64_max();
 
     freg_t get_frs1();
     freg_t get_frs2();
 
-    //sv_reg_t (sext_xlen)(reg_t &v); // WARNING... 
-    sv_reg_t (zext_xlen)(sv_reg_t v);
-    sv_reg_t (sext_xlen)(sv_reg_t v);
-    sv_reg_t (sext32)(uint_fast32_t v); // XXX TODO
-    sv_reg_t (sext32)(sv_reg_t v);
-    sv_reg_t (zext32)(sv_reg_t v);
+    reg_t (sext_xlen)(reg_t v); // WARNING...
+    reg_t (zext_xlen)(reg_t v);
+    //reg_t (sext_xlen)(sv_reg_t &v);
+    //reg_t (sext32)(uint_fast32_t v); // XXX TODO
+    reg_t (sext32)(reg_t v);
+    //reg_t (sext32)(sv_reg_t &v);
+    reg_t (zext32)(reg_t v);
 
 #include "sv_insn_decl.h"
 };

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 7bf35be89a843cc89ff0acfcb4f46009d66b11fe..6a69f28535bc3115a77e92d9c685e6b73e0a5fdf 100644 (file)
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -6,11 +6,13 @@
 
 #define DECL_1OP( op ) \
   bool operator op () const { \
-    return op (this->as_uint64()); } 
+    return op (this->as_uint64()); }
 
 #define DECL_BOP( op ) \
   bool operator op (const sv_reg_t& rhs) const { \
-    return this->as_uint64() op rhs.as_uint64(); } 
+    return this->as_uint64() op rhs.as_uint64(); } \
+  bool operator op (reg_t rhs) const { \
+    return this->as_uint64() op rhs; }
 
 #define DECL_BOPE( op ) \
   bool operator op (int rhs) const { \
@@ -26,7 +28,9 @@
   sv_reg_t operator op (const sreg_t& rhs) const { \
     return make_##type( (this->as_uint64() op rhs) ); } \
   sv_reg_t operator op (int rhs) const { \
-    return make_##type( (this->as_uint64() op rhs) ); } 
+    return make_##type( (this->as_uint64() op rhs) ); } \
+  sv_reg_t operator op (uint32_t rhs) const { \
+    return make_##type( (this->as_uint64() op rhs) ); }
 
 #define op_bneg ~
 #define op_xor ^
@@ -53,7 +57,7 @@ class sv_reg_t {
 public:
   virtual ~sv_reg_t() {}
   // using a type which accommodates all values
-  virtual uint64_t as_uint64() const { return 0; };
+  virtual uint64_t as_uint64() const = 0;
 
 public:
   DECL_BOP( op_ge )
@@ -76,20 +80,17 @@ public:
   DECL_OP( sv_uint64_t, op_sl )
   DECL_OP( sv_uint64_t, op_sr )
 
-  operator char () const  // XXX TODO, make_sv_char_t
-        { return make_sv_int64_t( (sreg_t) (as_uint64()) ); }
-  operator int32_t () // XXX TODO, make_sv_char_t
-        { return make_sv_int64_t( (sreg_t) (as_uint64()) ); }
-  operator uint32_t () const  // TODO, make_sv_uint32_t
-        { return make_sv_uint64_t( (sreg_t) (as_uint64()) ); }
-  operator sv_sreg_t () const;
-  operator sreg_t () const 
-        { return make_sv_int64_t( (sreg_t) (as_uint64()) ); }
-  operator reg_t () const 
-        { return make_sv_uint64_t( (reg_t) (as_uint64()) ); }
-  //operator uint_fast64_t () const 
+  operator uint8_t ();
+  operator char ();
+  operator uint32_t ();
+  operator int32_t ();
+  operator uint16_t ();
+  operator sv_sreg_t () ;
+  operator sreg_t () ;
+  operator reg_t () ;
+  //operator uint_fast64_t () const
   //      { return make_sv_uint64_t( (reg_t) (as_uint64()) ); }
-  //operator int_fast64_t () const 
+  //operator int_fast64_t () const
         //{ return make_sv_int64_t( (sreg_t) (as_uint64()) ); }
   // ...
 public:
@@ -120,6 +121,8 @@ private:
 
 class sv_uint16_t : public sv_reg_t {
 // ...
+public:
+    sv_uint16_t(uint16_t v) : data(v) {}
 private:
     virtual uint64_t as_uint64() const { return this->data; }
 private: