Additional notes:
-1) With regard to "Improve by two orders of magnitude the performance/watt for targeted Edge Applications", subject to Moore's Law and other limitations, such as geometry of devices we are moving in this direction, and whether we can achieve it will be subject to the available manufacturing processes we can afford during the scope of this Grant. We have already achieved one magnitude of improvement in simulation (TRL 3) of FFT, DCT and other DSP calculations. As already indicated above, the output of our design can be run on many different geometries of significantly-different performances.
-
-
-2) You will note that a significant number of our technology collaborators and the technology and services that we rely on are already funded by EU Grants. Through RED Semiconductor Ltd, we are going to be the conduit to commercial realisation of value for this investment, with subsequent commercial benefits of employment and tax revenues across the EU. We know not to lose sight of the fact all EU funding is fundamentally focused on future commercial success.
+1. With regard to "Improve by two orders of magnitude the performance/watt for targeted Edge Applications", subject to Moore's Law and other limitations, such as geometry of devices we are moving in this direction, and whether we can achieve it will be subject to the available manufacturing processes we can afford during the scope of this Grant. We have already achieved one magnitude of improvement in simulation (TRL 3) of FFT, DCT and other DSP calculations. As already indicated above, the output of our design can be run on many different geometries of significantly-different performances.
+2. You will note that a significant number of our technology collaborators and the technology and services that we rely on are already funded by EU Grants. Through RED Semiconductor Ltd, we are going to be the conduit to commercial realisation of value for this investment, with subsequent commercial benefits of employment and tax revenues across the EU. We know not to lose sight of the fact all EU funding is fundamentally focused on future commercial success.
* Fed4Fire.eu Grant Agreement No: 732638
* https://openpowerfoundation.org/libre-soc-180nm-power-isa-asic-submitted-to-imec-for-fabrication/
-Both Marie-Minerve Louerat (CNRS) and Jean-Paul Chaput's (Sorbonne Université LIP6 Lab) Academic Publications will continue https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 as will their continued Conference participation (example: FOSDEM 2021 coriolis2 https://av.tib.eu/media/52401?hl=coriolis2)
+Marie-Minerve Louerat (CNRS) and Jean-Paul Chaput's and Professor Galayko's (Sorbonne Université LIP6 Lab) Academic Publications will continue https://www.lip6.fr/actualite/personnes-fiche.php?ident=P109 https://www.lip6.fr/actualite/personnes-fiche.php?ident=P98 https://www.lip6.fr/actualite/personnes-fiche.php?ident=P230 as will their continued Conference participation (example: FOSDEM 2021 coriolis2 https://av.tib.eu/media/52401?hl=coriolis2)
Luke Leighton also releases videos of his Libre-SOC talks on youtube https://www.youtube.com/user/lkcl and a full list of all conferences (past and present) are maintained on the Libre-SOC website https://libre-soc.org/conferences/
Again these deliverables are no different from NLnet's existing deliverables to the EU under Grant Agreements 825310 and 825322
-1.1. A functioning Call-for-Proposals on the NLnet website.
-1.2. Inclusion of the new CfP within the existing NLnet infrastructure
-1.3. Progress Reports and Independent Audit Reports to the EU
+* 1.1. A functioning Call-for-Proposals on the NLnet website.
+* 1.2. Inclusion of the new CfP within the existing NLnet infrastructure
+* 1.3. Progress Reports and Independent Audit Reports to the EU
## 2. SVP64 Standards, RFC submission to OPF ISA WG
Note: some of these deliverables may not yet be determined due to the OpenPOWER Foundation having not yet finalised and published its procedures, having not yet completed their Legal Review. In addition, although we can advise and consult with them, it will be the OPF ISA WG who decides what final subdivisions of SVP64 are appropriate (not the Participants). This directly impacts and determines what the actual Deliverables will be: They will however fit the following template:
-2.1. Publish report on appropriate subdivisions of SVP64 subdivisions into multiple distinct OPF RFCs
-2.2. Publish presentations and explanatory materials to aid in the understanding of SVP64 and its value
-2.3. Attend Conferences to promote SVP64 and its benefits
-2.4. Complete the documentation and all tasks required for each SVP64 RFC and submit them to the OPF
-2.5. For each RFC, publish a report on the decision and all other permitted information that does not fall within the Commercial Confidentiality Requirements set by the OpenPOWER Foundation (these conditions are outside of our control).
+* 2.1. Publish report on appropriate subdivisions of SVP64 subdivisions into multiple distinct OPF RFCs
+* 2.2. Publish presentations and explanatory materials to aid in the understanding of SVP64 and its value
+* 2.3. Attend Conferences to promote SVP64 and its benefits
+* 2.4. Complete the documentation and all tasks required for each SVP64 RFC and submit them to the OPF
+* 2.5. For each RFC, publish a report on the decision and all other permitted information that does not fall within the Commercial Confidentiality Requirements set by the OpenPOWER Foundation (these conditions are outside of our control).
## 3. Power ISA Simulator and Compliance Test Suite
Deliverables:
-3.1. Delivery of an updated version of cavatools with new Draft SVP64 features
-3.2. Delivery of a version of cavatools with hardware-accurate models including Out-of-Order Execution
-3.3. Delivery of additional co-simulation and co-execution options to the Libre-SOC "Test API" including at least IBM POWER 9 (and POWER 10 if access can be obtained), and Microwatt.
-3.4. Delivery of an implementation of a Compliance Test Suite that meets the OpenPOWER Foundation's criteria
-3.5. Delivery of the documentation and an implementation of a Compliance Test Suite for Draft SVP64 Extensions for submission to the relevant OpenPOWER Foundation Workgroup.
-3.6. Public reports on all of the above at Conferences and on the Libre-SOC website.
+* 3.1. Delivery of an updated version of cavatools with new Draft SVP64 features
+* 3.2. Delivery of a version of cavatools with hardware-accurate models including Out-of-Order Execution
+* 3.3. Delivery of additional co-simulation and co-execution options to the Libre-SOC "Test API" including at least IBM POWER 9 (and POWER 10 if access can be obtained), and Microwatt.
+* 3.4. Delivery of an implementation of a Compliance Test Suite that meets the OpenPOWER Foundation's criteria
+* 3.5. Delivery of the documentation and an implementation of a Compliance Test Suite for Draft SVP64 Extensions for submission to the relevant OpenPOWER Foundation Workgroup.
+* 3.6. Public reports on all of the above at Conferences and on the Libre-SOC website.
## 4. Compilers and Software Libraries
Deliverables:
-4.1. Feasibility report on the viability and scope of achievable work within the available respective budgets for each deliverable
-4.2. Prototype compilers for each of gcc, llvm, Kazan and MESA3D meeting the scope of achievable work defined in the Feasibility study, delivered in source code form under appropriate Libre-Licenses and including unit test bench source code demonstrating successfully meeting the objectives
-4.3. Prototype ports of libc6, u-boot, Linux Kernel and other software demonstrated to meet the scope of achievable work, delivered in source code form under appropriate Libre-Licenses with unit tests.
-4.4. Public reports on the above and presentations at suitable Conferences
+* 4.1. Feasibility report on the viability and scope of achievable work within the available respective budgets for each deliverable
+* 4.2. Prototype compilers for each of gcc, llvm, Kazan and MESA3D meeting the scope of achievable work defined in the Feasibility study, delivered in source code form under appropriate Libre-Licenses and including unit test bench source code demonstrating successfully meeting the objectives
+* 4.3. Prototype ports of libc6, u-boot, Linux Kernel and other software demonstrated to meet the scope of achievable work, delivered in source code form under appropriate Libre-Licenses with unit tests.
+* 4.4. Public reports on the above and presentations at suitable Conferences
## 5. Enhancement of Libre-SOC HDL
Deliverables:
-5.1. Advanced HDL SIMD Library with appropriate documentation, unit tests and Formal Correctness Proofs, suitable for general-purpose wide adoption outside of Libre-SOC's use-case, under appropriate Libre Licenses
-5.2. Advanced HDL IEEE754 Library with appropriate documentation, unit tests and Formal Correctness Proofs, , suitable for general-purpose wide adoption outside of Libre-SOC's use-case, under appropriate Libre Licenses
-5.3. Advanced Libre-SOC SMP-capable Core, capable of multi-issue Out-of-Order Execution and implementing the Power ISA and Draft SVP64 Custom Extensions, with full unit tests and appropriate Formal Correctness Proofs.
-5.4. "Peripheral" HDL including PHYs+Controllers including Pinmux / Fabric Inter-connect Autogenerator
-5.5. Verification, Validation and Simulation of HDL
-5.6. Appropriate publications and reports on all of the above at Conferences and on the Libre-SOC website.
+* 5.1. Advanced HDL SIMD Library with appropriate documentation, unit tests and Formal Correctness Proofs, suitable for general-purpose wide adoption outside of Libre-SOC's use-case, under appropriate Libre Licenses
+* 5.2. Advanced HDL IEEE754 Library with appropriate documentation, unit tests and Formal Correctness Proofs, , suitable for general-purpose wide adoption outside of Libre-SOC's use-case, under appropriate Libre Licenses
+* 5.3. Advanced Libre-SOC SMP-capable Core, capable of multi-issue Out-of-Order Execution and implementing the Power ISA and Draft SVP64 Custom Extensions, with full unit tests and appropriate Formal Correctness Proofs.
+* 5.4. "Peripheral" HDL including PHYs+Controllers including Pinmux / Fabric Inter-connect Autogenerator
+* 5.5. Verification, Validation and Simulation of HDL
+* 5.6. Appropriate publications and reports on all of the above at Conferences and on the Libre-SOC website.
## 6. EMF Signature Hardware security
Deliverables:
-6.1. Feasibility and test methodology Report
-6.2. Mixed Analog / Digital Cells for the Signature System
-6.3. SPICE Simulation report on the expected behaviour of the "Signature" system
-6.4. coriolis2 module for automated deployment of Signature System within any ASIC
-6.5. small ASIC in large geometry and test report on the results
-6.6. large Libre-SOC ASIC in small geometry with Signature System and test report on its behaviour
-6.7. Academic Paper on the whole system.
+* 6.1. Feasibility and test methodology Report
+* 6.2. Mixed Analog / Digital Cells for the Signature System
+* 6.3. SPICE Simulation report on the expected behaviour of the "Signature" system
+* 6.4. coriolis2 module for automated deployment of Signature System within any ASIC
+* 6.5. small ASIC in large geometry and test report on the results
+* 6.6. large Libre-SOC ASIC in small geometry with Signature System and test report on its behaviour
+* 6.7. Academic Paper on the whole system.
## 7. Cell Libraries
Deliverables:
-7.1. Design of all Cells needed
-7.2. SPICE Model Simulations of all Cells
-7.3. Creation of Test ASIC Layouts and submission for MPW Shuttles in various geometries
-7.4. Generate and publish reports (Academic and others) and disseminate results
+* 7.1. Design of all Cells needed
+* 7.2. SPICE Model Simulations of all Cells
+* 7.3. Creation of Test ASIC Layouts and submission for MPW Shuttles in various geometries
+* 7.4. Generate and publish reports (Academic and others) and disseminate results
## 8. Improve Coriolis2 for smaller geometries
The key deliverables are measured by the successful passing of DRC (Design Rule Checks) against Commercial VLSI tools (Mentor, Synopsis), and is so critically inter-dependent on all components working 100% together that there can only be one deliverable, here, per ASIC Layout. Completion of sub- and sub-sub-tasks shall however be recorded in an easily-auditable Standard Libre/Open Task Tracking Database (gitlab, bugzilla) and appropriate structured progress reports created. As is the case with all Libre/Open Projects, "continuous" delivery is inherent through the ongoing publication of all source code in real-time. Full delivery is expected around 30 months.
-8.1. Coriolis2 VLSI improvements
-8.2. multiple small test ASIC layouts, to be added to LIP6 alliance-check-toolkit, potentially to be taped out and act as a preliminary test of prototype Cell Libraries
-8.3. large 2-core ASIC layout to be specifically taped-out in an MPW Shuttle Run
-8.4. Very large 8-core ASIC layout, not necessarily to be taped-out (MPW) due to size and cost, designed to push the limits.
-8.5. Academic and other reports
+* 8.1. Coriolis2 VLSI improvements
+* 8.2. multiple small test ASIC layouts, to be added to LIP6 alliance-check-toolkit, potentially to be taped out and act as a preliminary test of prototype Cell Libraries
+* 8.3. large 2-core ASIC layout to be specifically taped-out in an MPW Shuttle Run
+* 8.4. Very large 8-core ASIC layout, not necessarily to be taped-out (MPW) due to size and cost, designed to push the limits.
+* 8.5. Academic and other reports
## 9. VLSI Layout, Tape-outs and ASIC testing
Note that due to the strong inter-dependence, these are the same Deliverables as Work Package 8.
-9.1. Multiple small test ASIC layouts, to be added to LIP6 alliance-check-toolkit, potentially to be taped out and act as a preliminary test of prototype Cell Libraries
-9.2. Large 2-core ASIC layout to be specifically taped-out in an MPW Shuttle Run
-9.3. Very large 8-core ASIC layout, not to be taped-out due to size and cost, designed to push the limits.
-9.4. Academic and other reports
+* 9.1. Multiple small test ASIC layouts, to be added to LIP6 alliance-check-toolkit, potentially to be taped out and act as a preliminary test of prototype Cell Libraries
+* 9.2. Large 2-core ASIC layout to be specifically taped-out in an MPW Shuttle Run
+* 9.3. Very large 8-core ASIC layout, not to be taped-out due to size and cost, designed to push the limits.
+* 9.4. Academic and other reports
## 10. Management
Deliverables:
-10.1. Management, Administration and Training team
-10.2. Reporting
+* 10.1. Management, Administration and Training team
+* 10.2. Reporting
## 11. Helix GPS Correlator
Deliverables:
-11.1 Scoping Report
-11.2 NRE: Adapt 2-core to working demonstrator GPS Application
-11.3 Helix Management of NRE
-11.4 Helix Internal Engineering for GPS Antenna connectivity and testing.
-11.5 Reports
+* 11.1 Scoping Report
+* 11.2 NRE: Adapt 2-core to working demonstrator GPS Application
+* 11.3 Helix Management of NRE
+* 11.4 Helix Internal Engineering for GPS Antenna connectivity and testing.
+* 11.5 Reports
## Table 3.1c List of Deliverables
The majority of the consortium have been working together for over three years on the precursor technical development of the Libre-SOC core project, the evolution of which is the lynch-pin and "proving-ground" of this grant application. The public record of their achievements and team involvement can be found in their public Open Source record https://libre-soc.org/.
+
The Libre-SOC team are internationally experienced software professionals who have strong familiarity with state of the art software to silicon technologies. They have been supported by two of the co-applicants labs CNRS and LIP6 (The applicants being Sorbonne Université and Affiliated Entity, CNRS), and many other European based technology development groups, which each provide key elements of the project from specialist programs such as coriolis2, alliance, HITAS, YAGLE and more, and the manufacturing expertise of Imec. Their versatility and experience with Libre/Open Source Software also means that they can adapt to unforeseen circumstances and can navigate the ever-changing and constantly-evolving FOSS landscape with confidence.
+
The above is critically important in light of the requirement to demonstrate access to critical infrastructure, resources and the ability to fulfil: with the sole exception of NDA'd Foundry PDKs (Physical Design Kits), the entirety of this project is Libre/Open Source, both in the tools it utilises, components that it uses, and the results that are generated. With there being no restriction on the availability of Libre/Open Source software needed to complete the project, the Participants correspondingly have no impediment. We also have a proven strategy to deal with the NDA's: a "parallel track" where at least one Participant (Sorbonne Université, LIP6 Lab) has signed TSMC Foundry NDAs, and consequently there is no impediment there, either.
+
Sorbonne Université (SU) is a multidisciplinary, research-intensive and world class academic institution. It was created on January 1st 2018 as the merger of two first-class research intensive universities, UPMC (University Pierre and Marie Curie) and Paris-Sorbonne. Sorbonne Université is now organized with three faculties: humanities, medicine and science each with the wide-ranging autonomy necessary to conduct its ambitious programs in both research and education. SU counts 53,500 students, 3,400 professor-researchers and 3,600 administrative and technical staff members. SU is intensively engaged in European research projects (163 FP7 projects and 195 H2020 projects).
Its computer science laboratory, LIP6, is internationally recognized as a leading research institute.
+
LIP6 is a Joint Research Unit of both SU (Sorbonne Université) and CNRS. Both entities invest resources within LIP6 so CNRS is then an Affiliated Entity linked to SU. According to SU-CNRS agreement regarding LIP6, SU, as a full partner, manages the grant for its Affiliated Entity, CNRS.
+
RED Semiconductor Ltd has been established as a commercialisation vehicle, sharing the Libre principles of the core Libre-SOC team and bringing Semiconductor industry commercial management and technology experience. This includes the founders of two successful semiconductor companies and a public company chairman. There is also a cross directorship of Luke Leighton (of Libre-SOC) giving the company an extensive technology market and leadership experience.
+
NLnet is a Netherlands based public benefit organisation that brings to the table over 35 years of European internet history and well over two decades of unique real-world experience in funding and supporting bottom up internet infrastructure projects around the world - engaging some of the best independent researchers and developers. NLnet has funded essential work on important infrastructure parts of the internet, from the technologies with which the answers from the DNS root of the internet can now be trusted, all the way up to key standards for email security, transport layer security, email authenticity, and a lot more - on virtually every layer of the internet, from securing core routing protocols to browser security plugins, from firmware security to open source LTE networks.
+
Most recently NLnet is hosting the NGI0 Discovery, NGI0 PET and NGI Assure open calls as part of the Next Generation Internet research and development initiative, of which NLnet supports 300+ open source software, open hardware and open standards projects to build a more resilient, sustainable and trustworthy internet.
+
NLnet, a Stichting / Foundation, has been Libre-SOC’s funding source from the beginning and fundamentally understands our technology and direction of travel. As well as providing augmentation under existing EU Grants funding for technology opportunities that we will benefit from but are yet to be identified, they are a fundamental sounding board that will be invaluable to the project moving forward.
+
Regarding the extreme high-end computing resources necessary to complete the exceptionally-demanding task of VLSI development and Layout, we find that high-end modern laptops and desktop computers (with 64 to 256 GB of RAM) are perfectly adequate. However in the event that our immediately-accessible computing resources are not adequate, both Sorbonne Université (LIP6 and CNRS) and Libre-SOC qualify for access to Fed4Fire (https://www.fed4fire.eu/- grant agreement No 732638) which gives us direct access to large clusters (100+) high-end servers. Additionally, we are specifying some of these high-end computers in our budget, and the software to run on them is entirely Libre-Licensed and within our combined experience to deploy.
+
We have established that Embecosm Gmbh and Vrull.eu are some of the world's leading experts in Compiler Technology. We will put out to tender a Contract with an initial evaluation phase, followed by a TRL 4/5 Research phase for the prerequisite compilers (gcc, llvm, Kazan, MESA3D) necessary to support the core design work.
+
The OpenPOWER Foundation is a part of the Linux Foundation, and is directly responsible for the long-term protection and evolution of the Power ISA. Members include IBM, Google, NVidia, Raptor Engineering, University of Oregon and many more.
https://openpowerfoundation.org/membership/current-members/.
+
The Chair of the newly-formed ISA Working Group is Paul Mackerras, and the Technical Chair is Toshaan Bharvani. Both of these people have been kindly attending bi-weekly meetings with the Libre-SOC Team for over 18 months, and we have kept them apprised of ongoing developments, particularly with the Draft SVP64 ISA Extension. They are both going out of their way to regularly advise us on how to go about a successful RFC Process for SVP64, and we deeply appreciate their support.
+
HELIX Technology's involvement, as a potential customer and potential user of the Libre-SOC technology, will give focus to the deliverable of the project. They have world-leading expertise in Antenna Technology, and in the mathematics behind the Signal Processing required for GNSS/GPS. We have deliberately selected them to ensure the ambition of our overall project.
+
We therefore have a cohesive cooperative team of experience from concept to customer product and a supporting cast of specialist technical support that are an established practiced team.
+
As a last point: the creation of the teams for this project is critical for RED Semiconductors Limited and Libre-SOC. We have the benefit of having the core of an International Technology Headhunter Research Team amongst the directors of RED Semiconductor Limited, giving us the capability to ensure the project is fully manned in the required timescales without the need to externally resource recruitment services, and this is included in RED’s management manpower.
+
projects / libreriscv.git / commitdiff