"ww" can always be "wa".
* config/rs6000/constraints.md (define_register_constraint "ww"):
Delete.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
(rs6000_init_hard_regno_mode_ok): Adjust.
* config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
RS6000_CONSTRAINT_ww.
* config/rs6000/rs6000.md: Adjust.
* config/rs6000/vsx.md: Adjust.
* doc/md.texi (Machine Constraints): Adjust.
From-SVN: r271932
+2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/constraints.md (define_register_constraint "ww"):
+ Delete.
+ * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust.
+ (rs6000_init_hard_regno_mode_ok): Adjust.
+ * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Delete
+ RS6000_CONSTRAINT_ww.
+ * config/rs6000/rs6000.md: Adjust.
+ * config/rs6000/vsx.md: Adjust.
+ * doc/md.texi (Machine Constraints): Adjust.
+
2019-06-04 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (SFDF, SFDF2): Adjust comments.
(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]"
"General purpose register if 64-bit instructions are enabled or NO_REGS.")
-(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]"
- "FP or VSX register to perform float operations under -mvsx or NO_REGS.")
-
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"Floating point register if the STFIWX instruction is enabled or NO_REGS.")
"wp reg_class = %s\n"
"wq reg_class = %s\n"
"wr reg_class = %s\n"
- "ww reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
"\n",
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wp]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wq]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
- reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_ww]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
wc - Reserved to represent individual CR bits (used in LLVM).
wn - always NO_REGS.
wr - GPR if 64-bit mode is permitted.
- ww - Register class to do SF conversions in with VSX operations.
wx - Float register if we can do 32-bit int stores. */
if (TARGET_HARD_FLOAT)
rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
}
- if (TARGET_P8_VECTOR) /* SFmode */
- rs6000_constraints[RS6000_CONSTRAINT_ww] = VSX_REGS;
- else if (TARGET_VSX)
- rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS;
-
if (TARGET_STFIWX)
rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */
RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
- RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_MAX
; ISA 2.06 (power7). This includes instructions that normally target DF mode,
; but are used on SFmode, since internally SFmode values are kept in the DFmode
; format.
-(define_mode_attr Fv [(SF "ww") (DF "wa") (DI "wa")])
+(define_mode_attr Fv [(SF "wa") (DF "wa") (DI "wa")])
; Which isa is needed for those float instructions?
(define_mode_attr Fisa [(SF "p8v") (DF "*") (DI "*")])
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
- Z, m, ww, !r, f, ww,
+ Z, m, wa, !r, f, wa,
!r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
- wa, r, j, j, f, ww,
+ wa, r, j, j, f, wa,
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
(define_insn_and_split "reload_gpr_from_vsxsf"
[(set (match_operand:SF 0 "register_operand" "=r")
- (unspec:SF [(match_operand:SF 1 "register_operand" "ww")]
+ (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
UNSPEC_P8V_RELOAD_FROM_VSX))
(clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
(V2DF "wa")
(DI "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(TF "wp")
(KF "wq")
(V1TI "v")
(define_mode_attr VSr3 [(V2DF "wa")
(V4SF "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(DI "wa")
(KF "wq")
(TF "wp")])
(V2DF "wa")
(DI "wa")
(DF "wa")
- (SF "ww")
+ (SF "wa")
(V1TI "wa")
(TI "wa")
(TF "wp")
;; Same as vsx_xscvspdp, but use SF as the type
(define_insn "vsx_xscvspdp_scalar2"
- [(set (match_operand:SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(unspec:SF [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
;; format of scalars is actually DF.
(define_insn "vsx_xscvdpsp_scalar"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")]
+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVSPDP))]
"VECTOR_UNIT_VSX_P (V4SFmode)"
"xscvdpsp %x0,%x1"
;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs
(define_insn "vsx_xscvdpspn"
- [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
(unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
(define_insn "vsx_xscvdpspn_scalar"
[(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
- (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww")]
+ (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "wa")]
UNSPEC_VSX_CVDPSPN))]
"TARGET_XSCVDPSPN"
"xscvdpspn %x0,%x1"
(define_insn "vsx_concat_v2sf"
[(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
(unspec:V2DF
- [(match_operand:SF 1 "vsx_register_operand" "ww")
- (match_operand:SF 2 "vsx_register_operand" "ww")]
+ [(match_operand:SF 1 "vsx_register_operand" "wa")
+ (match_operand:SF 2 "vsx_register_operand" "wa")]
UNSPEC_VSX_CONCAT))]
"VECTOR_MEM_VSX_P (V2DFmode)"
{
;; Extract a SF element from V4SF
(define_insn_and_split "vsx_extract_v4sf"
- [(set (match_operand:SF 0 "vsx_register_operand" "=ww")
+ [(set (match_operand:SF 0 "vsx_register_operand" "=wa")
(vec_select:SF
(match_operand:V4SF 1 "vsx_register_operand" "wa")
(parallel [(match_operand:QI 2 "u5bit_cint_operand" "n")])))
;; Variable V4SF extract
(define_insn_and_split "vsx_extract_v4sf_var"
- [(set (match_operand:SF 0 "gpc_reg_operand" "=ww,ww,?r")
+ [(set (match_operand:SF 0 "gpc_reg_operand" "=wa,wa,?r")
(unspec:SF [(match_operand:V4SF 1 "input_operand" "v,m,m")
(match_operand:DI 2 "gpc_reg_operand" "r,r,r")]
UNSPEC_VSX_EXTRACT))
;; not double. First convert the value to double, and then to the desired
;; type.
(define_insn_and_split "*vsx_extract_si_<uns>float_<mode>"
- [(set (match_operand:VSX_EXTRACT_FL 0 "gpc_reg_operand" "=ww")
+ [(set (match_operand:VSX_EXTRACT_FL 0 "gpc_reg_operand" "=wa")
(any_float:VSX_EXTRACT_FL
(vec_select:SI
(match_operand:V4SI 1 "gpc_reg_operand" "v")
[(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
(unspec:V4SF
[(match_operand:V4SF 1 "gpc_reg_operand" "0")
- (match_operand:SF 2 "gpc_reg_operand" "ww")
+ (match_operand:SF 2 "gpc_reg_operand" "wa")
(match_operand:QI 3 "const_0_to_3_operand" "n")]
UNSPEC_VSX_SET))
(clobber (match_scratch:SI 4 "=&wa"))]
Any VSX register if the @option{-mvsx} option was used or NO_REGS.
When using any of the register constraints (@code{wa},
-@code{wp}, @code{wq}, or @code{ww})
+@code{wp}, or @code{wq},
that take VSX registers, you must use @code{%x<n>} in the template so
that the correct register is used. Otherwise the register number
output in the assembly file will be incorrect if an Altivec register
@item wr
General purpose register if 64-bit instructions are enabled or NO_REGS.
-@item ww
-FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS.
-
@item wx
Floating point register if the STFIWX instruction is enabled or NO_REGS.
projects / gcc.git / commitdiff