sdram: move dfii to phy

diff --git a/misoclib/mem/sdram/dfii/__init__.py b/misoclib/mem/sdram/dfii/__init__.py
deleted file mode 100644 (file)
index c3fa216..0000000
--- a/misoclib/mem/sdram/dfii/__init__.py
+++ /dev/null
@@ -1,58 +0,0 @@
-from migen.fhdl.std import *
-from migen.bank.description import *
-
-from misoclib.mem.sdram.bus import dfi
-
-class PhaseInjector(Module, AutoCSR):
-       def __init__(self, phase):
-               self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
-               self._command_issue = CSR()
-               self._address = CSRStorage(flen(phase.address))
-               self._baddress = CSRStorage(flen(phase.bank))
-               self._wrdata = CSRStorage(flen(phase.wrdata))
-               self._rddata = CSRStatus(flen(phase.rddata))
-
-               ###
-
-               self.comb += [
-                       If(self._command_issue.re,
-                               phase.cs_n.eq(~self._command.storage[0]),
-                               phase.we_n.eq(~self._command.storage[1]),
-                               phase.cas_n.eq(~self._command.storage[2]),
-                               phase.ras_n.eq(~self._command.storage[3])
-                       ).Else(
-                               phase.cs_n.eq(1),
-                               phase.we_n.eq(1),
-                               phase.cas_n.eq(1),
-                               phase.ras_n.eq(1)
-                       ),
-                       phase.address.eq(self._address.storage),
-                       phase.bank.eq(self._baddress.storage),
-                       phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
-                       phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
-                       phase.wrdata.eq(self._wrdata.storage),
-                       phase.wrdata_mask.eq(0)
-               ]
-               self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
-
-class DFIInjector(Module, AutoCSR):
-       def __init__(self, a, ba, d, nphases=1):
-               inti = dfi.Interface(a, ba, d, nphases)
-               self.slave = dfi.Interface(a, ba, d, nphases)
-               self.master = dfi.Interface(a, ba, d, nphases)
-
-               self._control = CSRStorage(4) # sel, cke, odt, reset_n
-
-               for n, phase in enumerate(inti.phases):
-                       setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
-
-               ###
-
-               self.comb += If(self._control.storage[0],
-                               self.slave.connect(self.master)
-                       ).Else(
-                               inti.connect(self.master)
-                       )
-               self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]
-               self.comb += [phase.odt.eq(self._control.storage[2]) for phase in inti.phases if hasattr(phase, "odt")]
-               self.comb += [phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases if hasattr(phase, "reset_n")]

diff --git a/misoclib/mem/sdram/phy/dfii.py b/misoclib/mem/sdram/phy/dfii.py
new file mode 100644 (file)
index 0000000..c3fa216
--- /dev/null
+++ b/misoclib/mem/sdram/phy/dfii.py
@@ -0,0 +1,58 @@
+from migen.fhdl.std import *
+from migen.bank.description import *
+
+from misoclib.mem.sdram.bus import dfi
+
+class PhaseInjector(Module, AutoCSR):
+       def __init__(self, phase):
+               self._command = CSRStorage(6) # cs, we, cas, ras, wren, rden
+               self._command_issue = CSR()
+               self._address = CSRStorage(flen(phase.address))
+               self._baddress = CSRStorage(flen(phase.bank))
+               self._wrdata = CSRStorage(flen(phase.wrdata))
+               self._rddata = CSRStatus(flen(phase.rddata))
+
+               ###
+
+               self.comb += [
+                       If(self._command_issue.re,
+                               phase.cs_n.eq(~self._command.storage[0]),
+                               phase.we_n.eq(~self._command.storage[1]),
+                               phase.cas_n.eq(~self._command.storage[2]),
+                               phase.ras_n.eq(~self._command.storage[3])
+                       ).Else(
+                               phase.cs_n.eq(1),
+                               phase.we_n.eq(1),
+                               phase.cas_n.eq(1),
+                               phase.ras_n.eq(1)
+                       ),
+                       phase.address.eq(self._address.storage),
+                       phase.bank.eq(self._baddress.storage),
+                       phase.wrdata_en.eq(self._command_issue.re & self._command.storage[4]),
+                       phase.rddata_en.eq(self._command_issue.re & self._command.storage[5]),
+                       phase.wrdata.eq(self._wrdata.storage),
+                       phase.wrdata_mask.eq(0)
+               ]
+               self.sync += If(phase.rddata_valid, self._rddata.status.eq(phase.rddata))
+
+class DFIInjector(Module, AutoCSR):
+       def __init__(self, a, ba, d, nphases=1):
+               inti = dfi.Interface(a, ba, d, nphases)
+               self.slave = dfi.Interface(a, ba, d, nphases)
+               self.master = dfi.Interface(a, ba, d, nphases)
+
+               self._control = CSRStorage(4) # sel, cke, odt, reset_n
+
+               for n, phase in enumerate(inti.phases):
+                       setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
+
+               ###
+
+               self.comb += If(self._control.storage[0],
+                               self.slave.connect(self.master)
+                       ).Else(
+                               inti.connect(self.master)
+                       )
+               self.comb += [phase.cke.eq(self._control.storage[1]) for phase in inti.phases]
+               self.comb += [phase.odt.eq(self._control.storage[2]) for phase in inti.phases if hasattr(phase, "odt")]
+               self.comb += [phase.reset_n.eq(self._control.storage[3]) for phase in inti.phases if hasattr(phase, "reset_n")]

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 3e93fdb421d97352bb82854364eda45dd7a7a124..25d5eec718f49fecac036d8def591663dc525d35 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -2,8 +2,8 @@ from migen.fhdl.std import *
 from migen.bus import wishbone, csr
 
 from misoclib.mem.sdram.bus import dfi, lasmibus
+from misoclib.mem.sdram.phy import dfii
 from misoclib.mem.sdram import minicon, lasmicon
-from misoclib.mem.sdram import dfii
 from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
 from misoclib.soc import SoC, mem_decoder