Added English language description for lwzupsx instruction

diff --git a/openpower/isa/pifixedloadshift.mdwn b/openpower/isa/pifixedloadshift.mdwn
index 265ce4ec8b6274e0d1404bd50cdde960163b93c2..1f9d3148652ee7053a880dd761dc6a5808704aac 100644 (file)
--- a/openpower/isa/pifixedloadshift.mdwn
+++ b/openpower/isa/pifixedloadshift.mdwn
@@ -99,17 +99,18 @@ Special Registers Altered:
 
 X-Form
 
-* lwzupsx RT,RA,RB
+* lwzupsx RT,RA,RB,SH
 
 Pseudo-code:
 
-    EA <- (RA)
+    EA <- (RA)<<(SH+1)
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- (RA) + (RB)
 
 Description:
 
-    Let the effective address (EA) be the register RA.
+    Let the effective address (EA) be the contents of
+    register RA shifted by (SH+1).
 
     The halfword in storage addressed by EA is loaded into RT[48:63].
     RT[0:47] are filled with a copy of bit 0 of the loaded halfword.