Remove iterator based Module::remove as per @cliffordwolf

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index f732b56b0ea74edbb7be62dc706c39374f3eaa79..3990ec283e229eff9e525d7e0d5d4e1acd103f1a 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1565,21 +1565,14 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
 
 void RTLIL::Module::remove(RTLIL::Cell *cell)
 {
-       auto it = cells_.find(cell->name);
-       log_assert(it != cells_.end());
-       remove(it);
-}
-
-dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
-{
-       RTLIL::Cell *cell = it->second;
        while (!cell->connections_.empty())
                cell->unsetPort(cell->connections_.begin()->first);
 
+       auto it = cells_.find(cell->name);
+       log_assert(it != cells_.end());
        log_assert(refcount_cells_ == 0);
-       it = cells_.erase(it);
+       cells_.erase(it);
        delete cell;
-       return it;
 }
 
 void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 4a0f8b4f86910b202f3bb564a6b39bafcf9d54f5..f4fcf5dcfb6e2c4fe8928f98c5b93fceb293818a 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1040,7 +1040,6 @@ public:
        // Removing wires is expensive. If you have to remove wires, remove them all at once.
        void remove(const pool<RTLIL::Wire*> &wires);
        void remove(RTLIL::Cell *cell);
-       dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it);
 
        void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
        void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2f670dba236caaabd2eabb7ef9fa1fd08b242099..7b13239f2af3ca055ef54764529d580660f08181 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -510,16 +510,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                }
 
                vector<RTLIL::Cell*> boxes;
-               for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
-                       RTLIL::Cell* cell = it->second;
+               for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
+                       RTLIL::Cell *cell = it->second;
                        if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
-                               it = module->remove(it);
+                               module->remove(cell);
                                continue;
                        }
                        RTLIL::Module* box_module = design->module(cell->type);
                        if (box_module && box_module->attributes.count("\\abc_box_id"))
-                               boxes.emplace_back(it->second);
-                       ++it;
+                               boxes.emplace_back(cell);
                }
 
                std::map<std::string, int> cell_stats;
@@ -620,8 +619,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                        }
                }
 
-                for (auto cell : boxes)
-                        module->remove(cell);
+               for (auto cell : boxes)
+                       module->remove(cell);
 
                // Copy connections (and rename) from mapped_mod to module
                for (auto conn : mapped_mod->connections()) {