[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
egid=100
env=
euid=100
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
system=system
uid=100
euid=100
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
width=64
responder_set=false
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 97621780 # Number of BTB hits
-global.BPredUnit.BTBLookups 104888901 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 203 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 4270829 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 101462576 # Number of conditional branches predicted
-global.BPredUnit.lookups 108029652 # Number of BP lookups
-global.BPredUnit.usedRAS 1765818 # Number of times the RAS was used to get a target.
-host_inst_rate 64442 # Simulator instruction rate (inst/s)
-host_mem_usage 296420 # Number of bytes of host memory used
-host_seconds 8776.17 # Real time elapsed on the host
-host_tick_rate 192322 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 20975706 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 18042230 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 207074480 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 57063120 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 71631614 # Number of BTB hits
+global.BPredUnit.BTBLookups 80215513 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 194 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 4366377 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 76991765 # Number of conditional branches predicted
+global.BPredUnit.lookups 83232960 # Number of BP lookups
+global.BPredUnit.usedRAS 1776050 # Number of times the RAS was used to get a target.
+host_inst_rate 91613 # Simulator instruction rate (inst/s)
+host_mem_usage 151676 # Number of bytes of host memory used
+host_seconds 6173.25 # Real time elapsed on the host
+host_tick_rate 271486 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 26015543 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 23632204 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 134244919 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 44983310 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
-sim_seconds 0.001688 # Number of seconds simulated
-sim_ticks 1687849017 # Number of ticks simulated
+sim_seconds 0.001676 # Number of seconds simulated
+sim_ticks 1675949017 # Number of ticks simulated
system.cpu.commit.COM:branches 62547159 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 17132854 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 16353031 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 701581491
+system.cpu.commit.COM:committed_per_cycle.samples 801372491
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 480309675 6846.10%
- 1 104094392 1483.71%
- 2 40244499 573.63%
- 3 11990473 170.91%
- 4 15113210 215.42%
- 5 17360338 247.45%
- 6 10367558 147.77%
- 7 4968492 70.82%
- 8 17132854 244.20%
+ 0 580782547 7247.35%
+ 1 101892793 1271.48%
+ 2 41339172 515.85%
+ 3 11939444 148.99%
+ 4 15719123 196.15%
+ 5 17754998 221.56%
+ 6 10147917 126.63%
+ 7 5443466 67.93%
+ 8 16353031 204.06%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4270194 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 4365734 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 331156834 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 90079827 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 2.984425 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.984425 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 114919015 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 3573.284961 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3259.194046 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 114199728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2570217420 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006259 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 719287 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 495902 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 728055062 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001944 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 223385 # number of ReadReq MSHR misses
+system.cpu.cpi 2.963384 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.963384 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 120253770 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 3927.286441 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3434.366579 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 119156440 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4309529230 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.009125 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1097330 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 872988 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 770472667 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001866 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 224342 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 3753.412851 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3080.837357 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 38221364 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4616536410 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.031177 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1229957 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 972712 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 792530006 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006521 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 257245 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 329.539233 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 2285.588257 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 317.127712 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 3492 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 327032 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 1150751 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 747460499 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 9089.303046 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9344.661839 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 37503702 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17702499310 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.049368 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1947619 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1690762 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2400241806 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006511 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 256857 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 327.941025 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3498.764706 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 325.562069 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 3493 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 17 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 1145498 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 59479 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 154370336 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 3686.944185 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 152421092 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7186753830 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.012627 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1949244 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1468614 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 1520585068 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003113 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 480630 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 159705091 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 7229.030286 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 156660142 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 22012028540 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.019066 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3044949 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2563750 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3170714473 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003013 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 481199 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 154370336 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 3686.944185 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3163.733159 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 159705091 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 7229.030286 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 6589.195890 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 152421092 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7186753830 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.012627 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1949244 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 1468614 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 1520585068 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003113 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 480630 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 156660142 # number of overall hits
+system.cpu.dcache.overall_miss_latency 22012028540 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.019066 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3044949 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2563750 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3170714473 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003013 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 481199 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 476534 # number of replacements
-system.cpu.dcache.sampled_refs 480630 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 477103 # number of replacements
+system.cpu.dcache.sampled_refs 481199 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4061.534340 # Cycle average of tags in use
-system.cpu.dcache.total_refs 152421092 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 22778000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 337990 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 113629190 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 667 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4610173 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 1474333999 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 347767079 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 231043933 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 53597030 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1980 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 9141290 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 108029652 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 167528188 # Number of cache lines fetched
-system.cpu.fetch.Cycles 410392582 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 7840605 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 1486495774 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 39151172 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.143052 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 167528188 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 99387598 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.968403 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4063.174314 # Cycle average of tags in use
+system.cpu.dcache.total_refs 156660142 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 20910000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 338217 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 515310439 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 681 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4340917 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 740208637 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 161139948 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 116871564 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 14453620 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 2001 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 8050541 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 83232960 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 72135284 # Number of cache lines fetched
+system.cpu.fetch.Cycles 198811102 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1485258 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 751818937 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 5990379 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.102023 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 72135284 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 73407664 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.921543 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 755178522
+system.cpu.fetch.rateDist.samples 815826112
system.cpu.fetch.rateDist.min_value 0
- 0 512314112 6784.01%
- 1 11453310 151.66%
- 2 16801464 222.48%
- 3 16318450 216.09%
- 4 18767749 248.52%
- 5 15201778 201.30%
- 6 32935567 436.13%
- 7 7297838 96.64%
- 8 124088254 1643.16%
+ 0 689150299 8447.27%
+ 1 10579353 129.68%
+ 2 12110332 148.44%
+ 3 11560507 141.70%
+ 4 9007686 110.41%
+ 5 3425511 41.99%
+ 6 3768928 46.20%
+ 7 3222436 39.50%
+ 8 73001060 894.81%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 167528184 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5600.855285 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4703.251892 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 167526954 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6889052 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000007 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1230 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 305 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4350508 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 925 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 72135284 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5699.600162 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4917.297556 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 72134046 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 7056105 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1238 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4627177 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000013 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 941 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5880.941176 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 181110.220541 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 3783 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 76656.797024 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 17 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 99976 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 3783 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 167528184 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5600.855285 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
-system.cpu.icache.demand_hits 167526954 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6889052 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000007 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1230 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 305 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4350508 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 925 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 72135284 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5699.600162 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
+system.cpu.icache.demand_hits 72134046 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 7056105 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000017 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1238 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 297 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4627177 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000013 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 941 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 167528184 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5600.855285 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4703.251892 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 72135284 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5699.600162 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4917.297556 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 167526954 # number of overall hits
-system.cpu.icache.overall_miss_latency 6889052 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000007 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1230 # number of overall misses
-system.cpu.icache.overall_mshr_hits 305 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4350508 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 925 # number of overall MSHR misses
+system.cpu.icache.overall_hits 72134046 # number of overall hits
+system.cpu.icache.overall_miss_latency 7056105 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000017 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1238 # number of overall misses
+system.cpu.icache.overall_mshr_hits 297 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4627177 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000013 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 941 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 47 # number of replacements
-system.cpu.icache.sampled_refs 925 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 44 # number of replacements
+system.cpu.icache.sampled_refs 941 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 739.927243 # Cycle average of tags in use
-system.cpu.icache.total_refs 167526954 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 749.515669 # Cycle average of tags in use
+system.cpu.icache.total_refs 72134046 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 932670496 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 92484798 # Number of branches executed
-system.cpu.iew.EXEC:nop 154927960 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.987080 # Inst execution rate
-system.cpu.iew.EXEC:refs 253735466 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 51400640 # Number of stores executed
+system.cpu.idleCycles 860122906 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 67691806 # Number of branches executed
+system.cpu.iew.EXEC:nop 43795429 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.748142 # Inst execution rate
+system.cpu.iew.EXEC:refs 168635664 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 41396142 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 486804101 # num instructions consuming a value
-system.cpu.iew.WB:count 671280122 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.809385 # average fanout of values written-back
+system.cpu.iew.WB:consumers 508232399 # num instructions consuming a value
+system.cpu.iew.WB:count 603225060 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.792920 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 394011709 # num instructions producing a value
-system.cpu.iew.WB:rate 0.888903 # insts written-back per cycle
-system.cpu.iew.WB:sent 673021204 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 4738518 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 26824121 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 207074480 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 402987686 # num instructions producing a value
+system.cpu.iew.WB:rate 0.739404 # insts written-back per cycle
+system.cpu.iew.WB:sent 604785539 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4695315 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 442855270 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 134244919 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 169524029 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 57063120 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 933012139 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 202334826 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7294318 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 745421559 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 36474 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 5961708 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 44983310 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 691933738 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 127239522 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 6754480 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 610353566 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 42801 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1439 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 53597030 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 214253 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 5548 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 70837719 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 7377596 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 20150 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 120734 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 14453620 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 431168 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 1871526 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 4575118 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 24838 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 1892 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 5548 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 92024970 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 17250597 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 1892 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 530187 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 4208331 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.335073 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.335073 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 752715877 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 1001889 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 5578 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 19195409 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 5170787 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 1001889 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 542024 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 4153291 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.337452 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.337452 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 617108046 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
- IntAlu 496182294 65.92% # Type of FU issued
- IntMult 8208 0.00% # Type of FU issued
+ IntAlu 445691749 72.22% # Type of FU issued
+ IntMult 6563 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
FloatAdd 33 0.00% # Type of FU issued
FloatCmp 6 0.00% # Type of FU issued
FloatMult 5 0.00% # Type of FU issued
FloatDiv 0 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 204178453 27.13% # Type of FU issued
- MemWrite 52346873 6.95% # Type of FU issued
+ MemRead 129192933 20.94% # Type of FU issued
+ MemWrite 42216752 6.84% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 3466320 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.004605 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 3402065 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005513 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 2723724 78.58% # attempts to use FU when none available
+ IntAlu 2626203 77.19% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 683243 19.71% # attempts to use FU when none available
- MemWrite 59353 1.71% # attempts to use FU when none available
+ MemRead 644339 18.94% # attempts to use FU when none available
+ MemWrite 131523 3.87% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 755178522
+system.cpu.iq.ISSUE:issued_per_cycle.samples 815826112
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 450030250 5959.26%
- 1 91846319 1216.22%
- 2 83470092 1105.30%
- 3 53962116 714.56%
- 4 57175468 757.11%
- 5 10089384 133.60%
- 6 7448894 98.64%
- 7 1047122 13.87%
- 8 108877 1.44%
+ 0 553114491 6779.81%
+ 1 85371128 1046.44%
+ 2 77782451 953.42%
+ 3 52154516 639.28%
+ 4 28098332 344.42%
+ 5 10103046 123.84%
+ 6 7930576 97.21%
+ 7 956122 11.72%
+ 8 315450 3.87%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.996739 # Inst issue rate
-system.cpu.iq.iqInstsAdded 778084154 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 752715877 # Number of instructions issued
+system.cpu.iq.ISSUE:rate 0.756421 # Inst issue rate
+system.cpu.iq.iqInstsAdded 648138284 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 617108046 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 210836257 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 250496 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 80438129 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1088392 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 119170992 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 481555 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 6806.870170 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2221.284395 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 455236 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 179150016 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.054654 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 26319 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 58461984 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054654 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 26319 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 337990 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 337990 # number of Writeback hits
+system.cpu.iq.iqSquashedOperandsExamined 57507029 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 482140 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 8078.944187 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2363.998861 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 455802 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 212783232 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.054627 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 26338 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 62263002 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.054627 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 26338 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 338217 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 338217 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 30.138911 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 30.147278 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 481555 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 6806.870170 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 455236 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 179150016 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.054654 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 26319 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 482140 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 8078.944187 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 455802 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 212783232 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.054627 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 26338 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 58461984 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.054654 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 26319 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 62263002 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.054627 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 26338 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 819545 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 6806.870170 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2221.284395 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 820357 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 8078.944187 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2363.998861 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 793226 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 179150016 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.032114 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 26319 # number of overall misses
+system.cpu.l2cache.overall_hits 794019 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 212783232 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.032106 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 26338 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 58461984 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.032114 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 26319 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 62263002 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.032106 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 26338 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 934 # number of replacements
-system.cpu.l2cache.sampled_refs 26319 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 935 # number of replacements
+system.cpu.l2cache.sampled_refs 26338 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 24352.046438 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 793226 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 24391.955858 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 794019 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 907 # number of writebacks
-system.cpu.numCycles 755178522 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 71954881 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 908 # number of writebacks
+system.cpu.numCycles 815826112 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 467231804 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 32102756 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 363513131 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 18414484 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 164520 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 1301215151 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1374424300 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 698904999 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 224329578 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 53597030 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 41747264 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 235050110 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 36638 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents 38638370 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 170863189 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 8553533 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 36121 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 961623776 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 729244091 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 554812455 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 115192044 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 14453620 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 48042805 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 90957566 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 42650 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 105666858 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 77555696 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 28 # count of temporary serializing insts renamed
-system.cpu.timesIdled 349047 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 308219 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
euid=100
zero=false
port=system.membus.port[0]
-[trace]
-bufsize=0
-cycle=0
-dump_on_exit=false
-file=cout
-flags=
-ignore=
-start=0
-
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
system=system
uid=100
euid=100
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
width=64
responder_set=false
-[trace]
-flags=
-start=0
-cycle=0
-bufsize=0
-file=cout
-dump_on_exit=false
-ignore=
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[random]
-seed=1
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 38046005 # Number of BTB hits
-global.BPredUnit.BTBLookups 46765160 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1072 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 5897447 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 36345249 # Number of conditional branches predicted
-global.BPredUnit.lookups 64275681 # Number of BP lookups
-global.BPredUnit.usedRAS 12928446 # Number of times the RAS was used to get a target.
-host_inst_rate 88491 # Simulator instruction rate (inst/s)
-host_mem_usage 183984 # Number of bytes of host memory used
-host_seconds 4244.22 # Real time elapsed on the host
-host_tick_rate 69460 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 64217134 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 49870920 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 126084683 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 92646936 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 36573856 # Number of BTB hits
+global.BPredUnit.BTBLookups 48300104 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1110 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 6040473 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 37489973 # Number of conditional branches predicted
+global.BPredUnit.lookups 66376995 # Number of BP lookups
+global.BPredUnit.usedRAS 13616030 # Number of times the RAS was used to get a target.
+host_inst_rate 78938 # Simulator instruction rate (inst/s)
+host_mem_usage 153528 # Number of bytes of host memory used
+host_seconds 4757.83 # Real time elapsed on the host
+host_tick_rate 66128 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 89962751 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 64024234 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 131935591 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 95765344 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574675 # Number of instructions simulated
-sim_seconds 0.000295 # Number of seconds simulated
-sim_ticks 294803028 # Number of ticks simulated
+sim_seconds 0.000315 # Number of seconds simulated
+sim_ticks 314625027 # Number of ticks simulated
system.cpu.commit.COM:branches 44587523 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 16167573 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 13381546 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 260352657
+system.cpu.commit.COM:committed_per_cycle.samples 276331431
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 139362663 5352.84%
- 1 37755491 1450.17%
- 2 23927219 919.03%
- 3 17243764 662.32%
- 4 9550787 366.84%
- 5 7718539 296.46%
- 6 5199548 199.71%
- 7 3427073 131.63%
- 8 16167573 620.99%
+ 0 148231465 5364.26%
+ 1 40756250 1474.90%
+ 2 28135615 1018.18%
+ 3 18140880 656.49%
+ 4 10622787 384.42%
+ 5 8112500 293.58%
+ 6 5544405 200.64%
+ 7 3405983 123.26%
+ 8 13381546 484.26%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183388 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5893264 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 6036288 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664447 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 98024957 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 118579541 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574675 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574675 # Number of Instructions Simulated
-system.cpu.cpi 0.784939 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.784939 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 94465294 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5573.350269 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5155.812183 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 94463621 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 9324215 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1673 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 688 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 5078475 # number of ReadReq MSHR miss cycles
+system.cpu.cpi 0.837716 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.837716 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 96374626 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5603.456853 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5219.612576 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 96372656 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 11038810 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000020 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1970 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 984 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5146538 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 986 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 5442.694460 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5169.706416 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73508218 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 68082665 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000170 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 12509 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 9314 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 16517212 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 6647.641993 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6867.316020 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73501543 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 127528364 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000261 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 19184 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 15988 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 21947942 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2708.631579 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3690.984252 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40184.650478 # Average number of references to valid blocks.
+system.cpu.dcache.WriteReq_mshr_misses 3196 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2800 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 40620.324964 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 19 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 2032 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 51464 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 7500080 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 53200 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 167986021 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 5458.107460 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 167971839 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 77406880 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 14182 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 10002 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 21595687 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 169895353 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6550.400586 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 169874199 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 138567174 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000125 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 21154 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 16972 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 27094480 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4180 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 4182 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 167986021 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 5458.107460 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 5166.432297 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 169895353 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6550.400586 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 6478.833094 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 167971839 # number of overall hits
-system.cpu.dcache.overall_miss_latency 77406880 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 14182 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 10002 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 21595687 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 169874199 # number of overall hits
+system.cpu.dcache.overall_miss_latency 138567174 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000125 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 21154 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 16972 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 27094480 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4180 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 4182 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 784 # number of replacements
-system.cpu.dcache.sampled_refs 4180 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 786 # number of replacements
+system.cpu.dcache.sampled_refs 4182 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3190.140908 # Cycle average of tags in use
-system.cpu.dcache.total_refs 167971839 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3211.654167 # Cycle average of tags in use
+system.cpu.dcache.total_refs 169874199 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 637 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 19324711 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 4274 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 11555430 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 538406721 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 137426232 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 102617017 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 16124012 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 12594 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 984698 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 64275681 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 66044385 # Number of cache lines fetched
-system.cpu.fetch.Cycles 172472243 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1233740 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 552850318 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 6527825 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.232481 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 66044385 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 50974451 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.999627 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 639 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 32658535 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 4257 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 11810746 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 562730439 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 143183566 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 99541453 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 18560140 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 12611 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 947878 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 66376995 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 68531131 # Number of cache lines fetched
+system.cpu.fetch.Cycles 171584130 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1722712 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 577337575 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 6483468 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.225089 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 68531131 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 50189886 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.957796 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 276476670
+system.cpu.fetch.rateDist.samples 294891572
system.cpu.fetch.rateDist.min_value 0
- 0 170048750 6150.56%
- 1 11707777 423.46%
- 2 11563595 418.25%
- 3 7250668 262.25%
- 4 16393688 592.95%
- 5 9178756 331.99%
- 6 6871715 248.55%
- 7 4129243 149.35%
- 8 39332478 1422.63%
+ 0 191838575 6505.39%
+ 1 8000057 271.29%
+ 2 8353997 283.29%
+ 3 6793291 230.37%
+ 4 15387795 521.81%
+ 5 8442060 286.28%
+ 6 8794810 298.24%
+ 7 2528585 85.75%
+ 8 44752402 1517.59%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 66044384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 4697.455355 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 3736.572860 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 66039333 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 23726847 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 5051 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 1160 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 14539005 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000059 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3891 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 5023.260870 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 16972.329221 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 68531131 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 4689.224645 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 3850.973049 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 68526132 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 23441434 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000073 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 4999 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1103 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 15003391 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000057 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3896 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 17588.842916 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 69 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 346605 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 66044384 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 4697.455355 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
-system.cpu.icache.demand_hits 66039333 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 23726847 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
-system.cpu.icache.demand_misses 5051 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 1160 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 14539005 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000059 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3891 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 68531131 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 4689.224645 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency
+system.cpu.icache.demand_hits 68526132 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 23441434 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000073 # miss rate for demand accesses
+system.cpu.icache.demand_misses 4999 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1103 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 15003391 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000057 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3896 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 66044384 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 4697.455355 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 3736.572860 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 66039333 # number of overall hits
-system.cpu.icache.overall_miss_latency 23726847 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
-system.cpu.icache.overall_misses 5051 # number of overall misses
-system.cpu.icache.overall_mshr_hits 1160 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 14539005 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000059 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3891 # number of overall MSHR misses
+system.cpu.icache.overall_accesses 68531131 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 4689.224645 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 3850.973049 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 68526132 # number of overall hits
+system.cpu.icache.overall_miss_latency 23441434 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000073 # miss rate for overall accesses
+system.cpu.icache.overall_misses 4999 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1103 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 15003391 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000057 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3896 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 1971 # number of replacements
-system.cpu.icache.sampled_refs 3891 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1976 # number of replacements
+system.cpu.icache.sampled_refs 3896 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1776.887115 # Cycle average of tags in use
-system.cpu.icache.total_refs 66039333 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1786.777118 # Cycle average of tags in use
+system.cpu.icache.total_refs 68526132 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 18326359 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 51280930 # Number of branches executed
-system.cpu.iew.EXEC:nop 27455299 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.521589 # Inst execution rate
-system.cpu.iew.EXEC:refs 191354897 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 79285920 # Number of stores executed
+system.cpu.idleCycles 19733456 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 52475714 # Number of branches executed
+system.cpu.iew.EXEC:nop 28200659 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.439607 # Inst execution rate
+system.cpu.iew.EXEC:refs 190729803 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 78992420 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 293982680 # num instructions consuming a value
-system.cpu.iew.WB:count 415403944 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.694108 # average fanout of values written-back
+system.cpu.iew.WB:consumers 302582293 # num instructions consuming a value
+system.cpu.iew.WB:count 419651187 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.683002 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 204055700 # num instructions producing a value
-system.cpu.iew.WB:rate 1.502492 # insts written-back per cycle
-system.cpu.iew.WB:sent 416259284 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6316593 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2856011 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 126084683 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 240 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 7411275 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 92646936 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 496689311 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 112068977 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 8996952 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 420683841 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 114816 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 206664160 # num instructions producing a value
+system.cpu.iew.WB:rate 1.423069 # insts written-back per cycle
+system.cpu.iew.WB:sent 420984328 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6525670 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4581779 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 131935591 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 243 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 8433935 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 95765344 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 517242480 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 111737383 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 7591261 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 424527920 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 366722 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 1986 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 16124012 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 416926 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 183286 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 727659 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 9888553 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 47660 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 32377 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 18560140 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 737234 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 8882 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 8984961 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 39727 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 81366 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 183286 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 25432695 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 19115536 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 81366 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 996952 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 5319641 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.273985 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.273985 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 429680793 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 675434 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 175954 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 31283603 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 22233944 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 675434 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1009222 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 5516448 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.193722 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.193722 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 432119181 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 33581 0.01% # Type of FU issued
- IntAlu 167723328 39.03% # Type of FU issued
- IntMult 2137299 0.50% # Type of FU issued
+ IntAlu 171100299 39.60% # Type of FU issued
+ IntMult 2148839 0.50% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 34928239 8.13% # Type of FU issued
- FloatCmp 8071357 1.88% # Type of FU issued
- FloatCvt 3141242 0.73% # Type of FU issued
- FloatMult 16626981 3.87% # Type of FU issued
- FloatDiv 1577676 0.37% # Type of FU issued
+ FloatAdd 35472672 8.21% # Type of FU issued
+ FloatCmp 7906658 1.83% # Type of FU issued
+ FloatCvt 2966336 0.69% # Type of FU issued
+ FloatMult 16725823 3.87% # Type of FU issued
+ FloatDiv 1566508 0.36% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 114426564 26.63% # Type of FU issued
- MemWrite 81014526 18.85% # Type of FU issued
+ MemRead 113251606 26.21% # Type of FU issued
+ MemWrite 80946859 18.73% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 9055324 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.021075 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 9237965 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.021378 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 66610 0.74% # attempts to use FU when none available
+ IntAlu 31984 0.35% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
- FloatAdd 110487 1.22% # attempts to use FU when none available
- FloatCmp 35273 0.39% # attempts to use FU when none available
- FloatCvt 2828 0.03% # attempts to use FU when none available
- FloatMult 2149754 23.74% # attempts to use FU when none available
- FloatDiv 664669 7.34% # attempts to use FU when none available
+ FloatAdd 74124 0.80% # attempts to use FU when none available
+ FloatCmp 35886 0.39% # attempts to use FU when none available
+ FloatCvt 5384 0.06% # attempts to use FU when none available
+ FloatMult 1393766 15.09% # attempts to use FU when none available
+ FloatDiv 1142138 12.36% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 4545406 50.20% # attempts to use FU when none available
- MemWrite 1480297 16.35% # attempts to use FU when none available
+ MemRead 5413419 58.60% # attempts to use FU when none available
+ MemWrite 1141264 12.35% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 276476670
+system.cpu.iq.ISSUE:issued_per_cycle.samples 294891572
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 105552217 3817.76%
- 1 55104063 1993.08%
- 2 43517427 1574.00%
- 3 31483356 1138.73%
- 4 21726208 785.82%
- 5 11633875 420.79%
- 6 4624667 167.27%
- 7 2409257 87.14%
- 8 425600 15.39%
+ 0 116554693 3952.46%
+ 1 58404803 1980.55%
+ 2 49059967 1663.66%
+ 3 31805455 1078.55%
+ 4 23494336 796.71%
+ 5 9548381 323.79%
+ 6 4038173 136.94%
+ 7 1656320 56.17%
+ 8 329444 11.17%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.554130 # Inst issue rate
-system.cpu.iq.iqInstsAdded 469233772 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 429680793 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 240 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 93305351 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1513608 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 71392848 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 8070 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 4399.297838 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2193.473956 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 717 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 32348037 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.911152 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 7353 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16128614 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.911152 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 7353 # number of ReadReq MSHR misses
-system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 637 # number of WriteReqNoAck|Writeback accesses(hits+misses)
-system.cpu.l2cache.WriteReqNoAck|Writeback_hits 637 # number of WriteReqNoAck|Writeback hits
+system.cpu.iq.ISSUE:rate 1.465349 # Inst issue rate
+system.cpu.iq.iqInstsAdded 489041578 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 432119181 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 243 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 113088119 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1629891 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 97430194 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 8078 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4922.926872 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2406.841240 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 721 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 36217973 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.910745 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 7357 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 17707131 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.910745 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 7357 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.184143 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.184858 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 8070 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 4399.297838 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 32348037 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.911152 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7353 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 8078 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4922.926872 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 721 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 36217973 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.910745 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7357 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 16128614 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.911152 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7353 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 17707131 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.910745 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7357 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 8707 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 4399.297838 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2193.473956 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 8717 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4922.926872 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2406.841240 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 1354 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 32348037 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.844493 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7353 # number of overall misses
+system.cpu.l2cache.overall_hits 1360 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 36217973 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.843983 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7357 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 16128614 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.844493 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7353 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 17707131 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.843983 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7357 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 7353 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 7357 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 6415.706550 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1354 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 6462.850486 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1360 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 276476670 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 8743693 # Number of cycles rename is blocking
+system.cpu.numCycles 294891572 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14686909 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532206 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 653030 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 142074266 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 8196045 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 109 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 687565953 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 524563034 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 338654872 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 98656303 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 16124012 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 9950983 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 79122666 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 927413 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 40317 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 23109451 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 249 # count of temporary serializing insts renamed
-system.cpu.timesIdled 6216 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 2446116 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 148616326 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 11769281 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 721460314 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 549210935 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 355537016 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 94743971 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 18560140 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15563294 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 96004810 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 2720932 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 38133 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 34543353 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 264 # count of temporary serializing insts renamed
+system.cpu.timesIdled 6492 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
+warn: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
euid=100
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
system=system
uid=100
euid=100
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
width=64
responder_set=false
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 13202034 # Number of BTB hits
-global.BPredUnit.BTBLookups 22107115 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 30370 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 454360 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 16498204 # Number of conditional branches predicted
-global.BPredUnit.lookups 27047110 # Number of BP lookups
-global.BPredUnit.usedRAS 4878193 # Number of times the RAS was used to get a target.
-host_inst_rate 69520 # Simulator instruction rate (inst/s)
-host_mem_usage 239908 # Number of bytes of host memory used
-host_seconds 1144.87 # Real time elapsed on the host
-host_tick_rate 987535 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 14725847 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 11490673 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 28863760 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 16312214 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 7945230 # Number of BTB hits
+global.BPredUnit.BTBLookups 13714223 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 29001 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 454297 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 10141226 # Number of conditional branches predicted
+global.BPredUnit.lookups 15617287 # Number of BP lookups
+global.BPredUnit.usedRAS 1851141 # Number of times the RAS was used to get a target.
+host_inst_rate 91600 # Simulator instruction rate (inst/s)
+host_mem_usage 155864 # Number of bytes of host memory used
+host_seconds 868.91 # Real time elapsed on the host
+host_tick_rate 1051887 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 16262618 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 12842437 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 22199501 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 16236124 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.001131 # Number of seconds simulated
-sim_ticks 1130602014 # Number of ticks simulated
+sim_seconds 0.000914 # Number of seconds simulated
+sim_ticks 913992014 # Number of ticks simulated
system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3893678 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3798224 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 89505192
+system.cpu.commit.COM:committed_per_cycle.samples 61093189
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 62882698 7025.59%
- 1 8753972 978.04%
- 2 5175203 578.20%
- 3 3243621 362.39%
- 4 2169519 242.39%
- 5 1432847 160.09%
- 6 1161882 129.81%
- 7 791772 88.46%
- 8 3893678 435.02%
+ 0 33945527 5556.35%
+ 1 9263496 1516.29%
+ 2 5234944 856.88%
+ 3 3369457 551.53%
+ 4 2068681 338.61%
+ 5 1423240 232.96%
+ 6 1205139 197.26%
+ 7 784481 128.41%
+ 8 3798224 621.71%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 359967 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 359791 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 21665941 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8215609 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 14.205014 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 14.205014 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 19540231 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 4453.766964 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3237.815878 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 19382637 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 701886951 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.008065 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 157594 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 95950 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 199591922 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003155 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61644 # number of ReadReq MSHR misses
+system.cpu.cpi 11.483501 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 11.483501 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 19669616 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 4470.389268 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 3240.793422 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 19511676 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 706053281 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.008030 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 157940 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 96341 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 199629634 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003132 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61599 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4830.124895 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3999.409028 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13942631 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3239786953 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.045899 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 670746 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 527274 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 573803212 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 9707.501078 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 9477.511675 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13569879 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 10129757960 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.071407 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1043498 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 900030 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1359719645 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009818 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 143472 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 3332.672727 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3759.399862 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 162.470348 # Average number of references to valid blocks.
+system.cpu.dcache.WriteReq_mshr_misses 143468 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 3321.963636 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3975 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 161.320715 # Average number of references to valid blocks.
system.cpu.dcache.blocked_no_mshrs 110 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 125901 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 366594 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 473312202 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 1 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 365416 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 3975 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 34153608 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33325268 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 3941673904 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.024253 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 828340 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 623224 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 773395134 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006006 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 205116 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 34282993 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 9019.034891 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33081555 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10835811241 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.035045 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1201438 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 996371 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 1559349279 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005982 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 205067 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 34153608 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4758.521747 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3770.525625 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 34282993 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 9019.034891 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 7604.096607 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33325268 # number of overall hits
-system.cpu.dcache.overall_miss_latency 3941673904 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.024253 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 828340 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 623224 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 773395134 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006006 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 205116 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 33081555 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10835811241 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.035045 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1201438 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 996371 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 1559349279 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005982 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 205067 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 201020 # number of replacements
-system.cpu.dcache.sampled_refs 205116 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 200971 # number of replacements
+system.cpu.dcache.sampled_refs 205067 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4057.039034 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33325268 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 27784000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147771 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 11948269 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 95198 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3558048 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 131593428 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 51674084 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 25481309 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4702945 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 281359 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 401531 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 27047110 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 22733117 # Number of cache lines fetched
-system.cpu.fetch.Cycles 51481541 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 159026 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 148267180 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 3966980 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.287100 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 22733117 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 18080227 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.573826 # Number of inst fetches per cycle
+system.cpu.dcache.tagsinuse 4063.517542 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33081555 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 17025000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 147753 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 13116101 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 95141 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3521692 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 99189601 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 29616630 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 18020228 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1276894 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 291919 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 340231 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 15617287 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13002150 # Number of cache lines fetched
+system.cpu.fetch.Cycles 31529148 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 124397 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 100725428 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 547316 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.250397 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 13002150 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 9796371 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.614964 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 94208138
+system.cpu.fetch.rateDist.samples 62370084
system.cpu.fetch.rateDist.min_value 0
- 0 65459635 6948.41%
- 1 1687117 179.08%
- 2 1748812 185.63%
- 3 1938924 205.81%
- 4 6981531 741.08%
- 5 6100701 647.58%
- 6 758078 80.47%
- 7 1979150 210.08%
- 8 7554190 801.86%
+ 0 43843090 7029.51%
+ 1 1383259 221.78%
+ 2 1262238 202.38%
+ 3 1426265 228.68%
+ 4 3918105 628.20%
+ 5 1724208 276.45%
+ 6 613107 98.30%
+ 7 1031700 165.42%
+ 8 7168112 1149.29%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 22733116 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3345.551905 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2359.548288 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 22631700 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 339292492 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.004461 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 101416 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 13878 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 206550138 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.003851 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 87538 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses 13002150 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3387.778909 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2412.580892 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12899943 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 346254719 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.007861 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 102207 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 14535 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 211515792 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.006743 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 87672 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3731.567010 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 258.538675 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 5804 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 147.140366 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 97 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 361962 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 5804 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 22733116 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
-system.cpu.icache.demand_hits 22631700 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 339292492 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.004461 # miss rate for demand accesses
-system.cpu.icache.demand_misses 101416 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 13878 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 206550138 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.003851 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 87538 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 13002150 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3387.778909 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency
+system.cpu.icache.demand_hits 12899943 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 346254719 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.007861 # miss rate for demand accesses
+system.cpu.icache.demand_misses 102207 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 14535 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 211515792 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.006743 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 87672 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 22733116 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3345.551905 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2359.548288 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 13002150 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3387.778909 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2412.580892 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 22631700 # number of overall hits
-system.cpu.icache.overall_miss_latency 339292492 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.004461 # miss rate for overall accesses
-system.cpu.icache.overall_misses 101416 # number of overall misses
-system.cpu.icache.overall_mshr_hits 13878 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 206550138 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.003851 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 87538 # number of overall MSHR misses
+system.cpu.icache.overall_hits 12899943 # number of overall hits
+system.cpu.icache.overall_miss_latency 346254719 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.007861 # miss rate for overall accesses
+system.cpu.icache.overall_misses 102207 # number of overall misses
+system.cpu.icache.overall_mshr_hits 14535 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 211515792 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.006743 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 87672 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 85490 # number of replacements
-system.cpu.icache.sampled_refs 87537 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 85624 # number of replacements
+system.cpu.icache.sampled_refs 87671 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1835.330854 # Cycle average of tags in use
-system.cpu.icache.total_refs 22631700 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1862.743229 # Cycle average of tags in use
+system.cpu.icache.total_refs 12899943 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1036393877 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 14379719 # Number of branches executed
-system.cpu.iew.EXEC:nop 9265977 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.989418 # Inst execution rate
-system.cpu.iew.EXEC:refs 43156162 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 15338261 # Number of stores executed
+system.cpu.idleCycles 851621931 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 14377755 # Number of branches executed
+system.cpu.iew.EXEC:nop 9220461 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.335296 # Inst execution rate
+system.cpu.iew.EXEC:refs 36382036 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 15204952 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 46157981 # num instructions consuming a value
-system.cpu.iew.WB:count 86105601 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.741496 # average fanout of values written-back
+system.cpu.iew.WB:consumers 46748099 # num instructions consuming a value
+system.cpu.iew.WB:count 82847738 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.736514 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 34225955 # num instructions producing a value
-system.cpu.iew.WB:rate 0.913993 # insts written-back per cycle
-system.cpu.iew.WB:sent 86171133 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 389534 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3213991 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 28863760 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 4784 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1402526 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 16312214 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 110003367 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 27817901 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 453087 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 93211232 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 28742 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 34430613 # num instructions producing a value
+system.cpu.iew.WB:rate 1.328325 # insts written-back per cycle
+system.cpu.iew.WB:sent 82914162 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 396555 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4917376 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 22199501 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 4762 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 311974 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 16236124 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 96553237 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 21177084 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 433562 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 83282498 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 37202 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 12962 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4702945 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 194395 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 1528 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 6922047 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 1365052 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 5008 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 11594 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1276894 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 204710 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 98563 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 1300046 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 1230 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3825 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1528 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 8484361 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 1467595 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3825 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 102872 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 286662 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.070398 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.070398 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 93664319 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 27684 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 1255 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1820102 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 1391505 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 27684 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 103251 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 293304 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.087081 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.087081 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 83716060 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
- IntAlu 49995908 53.38% # Type of FU issued
- IntMult 43196 0.05% # Type of FU issued
+ IntAlu 46816661 55.92% # Type of FU issued
+ IntMult 44502 0.05% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 123595 0.13% # Type of FU issued
+ FloatAdd 125345 0.15% # Type of FU issued
FloatCmp 86 0.00% # Type of FU issued
- FloatCvt 122386 0.13% # Type of FU issued
+ FloatCvt 122997 0.15% # Type of FU issued
FloatMult 51 0.00% # Type of FU issued
- FloatDiv 37853 0.04% # Type of FU issued
+ FloatDiv 37854 0.05% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 27919833 29.81% # Type of FU issued
- MemWrite 15421411 16.46% # Type of FU issued
+ MemRead 21285503 25.43% # Type of FU issued
+ MemWrite 15283061 18.26% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1229792 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013130 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1123822 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.013424 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 83895 6.82% # attempts to use FU when none available
+ IntAlu 98385 8.75% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 589327 47.92% # attempts to use FU when none available
- MemWrite 556570 45.26% # attempts to use FU when none available
+ MemRead 476117 42.37% # attempts to use FU when none available
+ MemWrite 549320 48.88% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 94208138
+system.cpu.iq.ISSUE:issued_per_cycle.samples 62370084
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 54322746 5766.25%
- 1 13333515 1415.33%
- 2 10626230 1127.95%
- 3 8813553 935.54%
- 4 4440243 471.32%
- 5 1597603 169.58%
- 6 685526 72.77%
- 7 334234 35.48%
- 8 54488 5.78%
+ 0 25315225 4058.87%
+ 1 13800975 2212.76%
+ 2 10743054 1722.47%
+ 3 5596398 897.29%
+ 4 4388925 703.69%
+ 5 1495414 239.76%
+ 6 664039 106.47%
+ 7 305653 49.01%
+ 8 60401 9.68%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.994227 # Inst issue rate
-system.cpu.iq.iqInstsAdded 100732606 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 93664319 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 4784 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 20911338 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 73995 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 201 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 16334966 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 292646 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3929.598028 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2043.469607 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 122985 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 666699531 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.579748 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 169661 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 346697097 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579748 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 169661 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147771 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147307 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.003140 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 464 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.003140 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 464 # number of Writeback MSHR misses
+system.cpu.iq.ISSUE:rate 1.342247 # Inst issue rate
+system.cpu.iq.iqInstsAdded 87328014 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 83716060 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 4762 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 7507881 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 113500 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 179 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 6033024 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 292729 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 7766.621627 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2997.837795 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 123055 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1317793758 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.579628 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 169674 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 508655130 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.579628 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 169674 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 147753 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 147285 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.003167 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 468 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.003167 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 468 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.593139 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.593300 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 292646 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3929.598028 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 122985 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 666699531 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.579748 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 169661 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 292729 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 7766.621627 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 123055 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 1317793758 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.579628 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 169674 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 346697097 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.579748 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 169661 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 508655130 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.579628 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 169674 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 440417 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3918.880417 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2043.469607 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 440482 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 7745.258419 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2997.837795 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 270292 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 666699531 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.386282 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 170125 # number of overall misses
+system.cpu.l2cache.overall_hits 270340 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 1317793758 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.386263 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 170142 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 346697097 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.385228 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 169661 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 508655130 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.385201 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 169674 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 136892 # number of replacements
-system.cpu.l2cache.sampled_refs 169660 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 136905 # number of replacements
+system.cpu.l2cache.sampled_refs 169673 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 30349.297230 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 270292 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 625483000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 115938 # number of writebacks
-system.cpu.numCycles 94208138 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 7563765 # Number of cycles rename is blocking
+system.cpu.l2cache.tagsinuse 30821.723437 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 270340 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 468003000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 115935 # number of writebacks
+system.cpu.numCycles 62370084 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 8787185 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 87866 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 52361095 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 3315491 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 3509 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 154857350 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 130101763 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 82913656 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 25182526 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4702945 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 3542613 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 30366775 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 855194 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 4773 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 6398047 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 4771 # count of temporary serializing insts renamed
-system.cpu.timesIdled 275758 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 113083 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 30263464 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3026568 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 587 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 118807787 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 98380136 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 59048113 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 17777635 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1276894 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 3354217 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 6501232 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 910689 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 4741 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 5955323 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 4739 # count of temporary serializing insts renamed
+system.cpu.timesIdled 280733 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[exetrace]
-intel_format=false
-legion_lockstep=false
-pc_symbol=true
-print_cpseq=false
-print_cycle=true
-print_data=true
-print_effaddr=true
-print_fetchseq=false
-print_iregs=false
-print_opclass=true
-print_thread=true
-speculative=true
-trace_system=client
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
+dummy=0
[system]
type=System
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
euid=100
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
system=system
uid=100
euid=100
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
width=64
responder_set=false
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[exetrace]
-speculative=true
-print_cycle=true
-print_opclass=true
-print_thread=true
-print_effaddr=true
-print_data=true
-print_iregs=false
-print_fetchseq=false
-print_cpseq=false
-print_reg_delta=false
-pc_symbol=true
-intel_format=false
-legion_lockstep=false
-trace_system=client
-
-[statsreset]
-reset_cycle=0
-
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 1060300638 # Number of BTB hits
-global.BPredUnit.BTBLookups 1075264664 # Number of BTB lookups
+global.BPredUnit.BTBHits 929108954 # Number of BTB hits
+global.BPredUnit.BTBLookups 938262248 # Number of BTB lookups
global.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 20658855 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 1028649695 # Number of conditional branches predicted
-global.BPredUnit.lookups 1098978166 # Number of BP lookups
-global.BPredUnit.usedRAS 20738311 # Number of times the RAS was used to get a target.
-host_inst_rate 28281 # Simulator instruction rate (inst/s)
-host_mem_usage 1256892 # Number of bytes of host memory used
-host_seconds 61385.49 # Real time elapsed on the host
-host_tick_rate 405833 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 114920109 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 60881817 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 938731548 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 389309694 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.condIncorrect 21205625 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 887467305 # Number of conditional branches predicted
+global.BPredUnit.lookups 962390884 # Number of BP lookups
+global.BPredUnit.usedRAS 21400461 # Number of times the RAS was used to get a target.
+host_inst_rate 41899 # Simulator instruction rate (inst/s)
+host_mem_usage 150980 # Number of bytes of host memory used
+host_seconds 41434.26 # Real time elapsed on the host
+host_tick_rate 599461 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 138710917 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 68670490 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 815007661 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 388931456 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
-sim_seconds 0.024912 # Number of seconds simulated
-sim_ticks 24912272090 # Number of ticks simulated
+sim_seconds 0.024838 # Number of seconds simulated
+sim_ticks 24838210102 # Number of ticks simulated
system.cpu.commit.COM:branches 214632552 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 72343657 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 66487461 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 5678957793
+system.cpu.commit.COM:committed_per_cycle.samples 7112101736
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 5103057521 8985.90%
- 1 193842571 341.33%
- 2 126727829 223.15%
- 3 63255233 111.39%
- 4 47590442 83.80%
- 5 34302037 60.40%
- 6 22774532 40.10%
- 7 15063971 26.53%
- 8 72343657 127.39%
+ 0 6522703166 9171.27%
+ 1 208562151 293.25%
+ 2 123042509 173.00%
+ 3 62023833 87.21%
+ 4 51435586 72.32%
+ 5 40600313 57.09%
+ 6 22309158 31.37%
+ 7 14937559 21.00%
+ 8 66487461 93.48%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 20658355 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 21205131 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 3012390712 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 2701603860 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 14.350025 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 14.350025 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 466176479 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5764.172372 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5678.042412 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 454097633 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 69624550394 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.025910 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 12078846 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 4784670 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 41416640690 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.015647 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7294176 # number of ReadReq MSHR misses
+system.cpu.cpi 14.307364 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 14.307364 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 489384352 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5253.286413 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 5452.839977 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 474368420 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 78882991559 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.030683 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 15015932 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 7713263 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 39820285465 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.014922 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7302669 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 11148.179412 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14223.476157 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 157574910 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 35156809407 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.019621 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3153592 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1270515 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 26783900812 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011716 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1883077 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 972.020892 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 2881.979981 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 66.650940 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 659829 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 896062 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 641367573 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2582432746 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 8690.039906 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14121.575874 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 155407108 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 46243126214 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.033108 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 5321394 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 3438755 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 26585829481 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.011713 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1882639 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 985.727671 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets 3841.099983 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 68.563354 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 637482 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 65141 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 628383647 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 250213094 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 626904981 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 6878.830546 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 611672543 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 104781359801 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.024298 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 15232438 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6055185 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 68200541502 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.014639 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9177253 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 650112854 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6152.535381 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 629775528 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 125126117773 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.031283 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 20337326 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 11152018 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 66406114946 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.014129 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9185308 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 626904981 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 6878.830546 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 7431.476663 # average overall mshr miss latency
+system.cpu.dcache.overall_accesses 650112854 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6152.535381 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 7229.601331 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 611672543 # number of overall hits
-system.cpu.dcache.overall_miss_latency 104781359801 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.024298 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 15232438 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6055185 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 68200541502 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.014639 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9177253 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 629775528 # number of overall hits
+system.cpu.dcache.overall_miss_latency 125126117773 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.031283 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 20337326 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 11152018 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 66406114946 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.014129 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9185308 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 9173157 # number of replacements
-system.cpu.dcache.sampled_refs 9177253 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9181212 # number of replacements
+system.cpu.dcache.sampled_refs 9185308 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4093.061614 # Cycle average of tags in use
-system.cpu.dcache.total_refs 611672543 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 39716000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244715 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3168036062 # Number of cycles decode is blocked
+system.cpu.dcache.tagsinuse 4093.052798 # Cycle average of tags in use
+system.cpu.dcache.total_refs 629775528 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 39780000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2244995 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 5295615421 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 511 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 48557069 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 6641345328 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 1298412925 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 1202046298 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 501929792 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1629 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 10462509 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 1098978166 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 541280485 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1955627258 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 11328270 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 7938391391 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 242391708 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.177803 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 541280485 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1081038949 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.284345 # Number of inst fetches per cycle
+system.cpu.decode.DECODE:BranchResolved 51642597 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 5750899999 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 834310560 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 972356636 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 417727902 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1635 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 9819120 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 962390884 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 341574441 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1454523625 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 5354005 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 6616091478 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 145044249 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.127810 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 341574441 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 950509415 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.878651 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 6180887586
+system.cpu.fetch.rateDist.samples 7529829639
system.cpu.fetch.rateDist.min_value 0
- 0 4766540797 7711.74%
- 1 80764415 130.67%
- 2 63598055 102.89%
- 3 58203597 94.17%
- 4 424384465 686.61%
- 5 69131012 111.85%
- 6 94422767 152.77%
- 7 44649271 72.24%
- 8 579193207 937.07%
+ 0 6416880458 8521.95%
+ 1 35027129 46.52%
+ 2 21417088 28.44%
+ 3 34363919 45.64%
+ 4 372287950 494.42%
+ 5 53476407 71.02%
+ 6 32781145 43.54%
+ 7 26846633 35.65%
+ 8 536748910 712.83%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 541280484 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 5378.819380 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 4616.750831 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 541279194 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 6938677 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000002 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1290 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 387 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 4168926 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 341574441 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 5436.849282 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 4708.305648 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 341573187 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 6817809 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 1254 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 351 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 4251600 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 903 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 4207.523810 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 599423.249169 # Average number of references to valid blocks.
+system.cpu.icache.avg_blocked_cycles_no_targets 4779 # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 378264.880399 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 21 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 1 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 88358 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 4779 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 541280484 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 5378.819380 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
-system.cpu.icache.demand_hits 541279194 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 6938677 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000002 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1290 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 387 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 4168926 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 341574441 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 5436.849282 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency
+system.cpu.icache.demand_hits 341573187 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 6817809 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
+system.cpu.icache.demand_misses 1254 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 351 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 4251600 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 903 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 541280484 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 5378.819380 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 4616.750831 # average overall mshr miss latency
+system.cpu.icache.overall_accesses 341574441 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 5436.849282 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 4708.305648 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 541279194 # number of overall hits
-system.cpu.icache.overall_miss_latency 6938677 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000002 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1290 # number of overall misses
-system.cpu.icache.overall_mshr_hits 387 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 4168926 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 341573187 # number of overall hits
+system.cpu.icache.overall_miss_latency 6817809 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
+system.cpu.icache.overall_misses 1254 # number of overall misses
+system.cpu.icache.overall_mshr_hits 351 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 4251600 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 903 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 716.132429 # Cycle average of tags in use
-system.cpu.icache.total_refs 541279194 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 719.119159 # Cycle average of tags in use
+system.cpu.icache.total_refs 341573187 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 18731384505 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 250098653 # Number of branches executed
-system.cpu.iew.EXEC:nop 147895912 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.440971 # Inst execution rate
-system.cpu.iew.EXEC:refs 918923683 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 177016651 # Number of stores executed
+system.cpu.idleCycles 17308380464 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 264199071 # Number of branches executed
+system.cpu.iew.EXEC:nop 130726584 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.347587 # Inst execution rate
+system.cpu.iew.EXEC:refs 833351854 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 181613826 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1839076786 # num instructions consuming a value
-system.cpu.iew.WB:count 2471794731 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.797100 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1860973502 # num instructions consuming a value
+system.cpu.iew.WB:count 2467010272 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.791148 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1465928228 # num instructions producing a value
-system.cpu.iew.WB:rate 0.399909 # insts written-back per cycle
-system.cpu.iew.WB:sent 2475054397 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 21956654 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2471410228 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 938731548 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 111073783 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 389309694 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 4831881465 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 741907032 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 286170200 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2725595031 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1536928 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1472305742 # num instructions producing a value
+system.cpu.iew.WB:rate 0.327632 # insts written-back per cycle
+system.cpu.iew.WB:sent 2471732034 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 22834368 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 4630364405 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 815007661 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 46 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 31860417 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 388931456 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4520549939 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 651738028 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 279876672 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2617267318 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2938028 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 161620 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 501929792 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 6153373 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 8 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 233590575 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 41593346 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 516978 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 161905 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 417727902 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 6385903 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 122063096 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 39544757 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 151090 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 47985 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 8 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 493065187 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 228404712 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 47985 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 726441 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 21230213 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.069686 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.069686 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 3011765231 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 4644371 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 12 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 369341300 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 228026474 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 4644371 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 832035 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 22002333 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.069894 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.069894 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 2897143990 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 0 0.00% # Type of FU issued
- IntAlu 1970711875 65.43% # Type of FU issued
- IntMult 679 0.00% # Type of FU issued
+ IntAlu 1942173026 67.04% # Type of FU issued
+ IntMult 100 0.00% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 206 0.00% # Type of FU issued
+ FloatAdd 210 0.00% # Type of FU issued
FloatCmp 15 0.00% # Type of FU issued
- FloatCvt 146 0.00% # Type of FU issued
- FloatMult 12 0.00% # Type of FU issued
+ FloatCvt 140 0.00% # Type of FU issued
+ FloatMult 13 0.00% # Type of FU issued
FloatDiv 24 0.00% # Type of FU issued
FloatSqrt 0 0.00% # Type of FU issued
- MemRead 862446019 28.64% # Type of FU issued
- MemWrite 178606255 5.93% # Type of FU issued
+ MemRead 770673405 26.60% # Type of FU issued
+ MemWrite 184297057 6.36% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 11307551 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.003754 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 12298143 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.004245 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
(null) 0 0.00% # attempts to use FU when none available
- IntAlu 509990 4.51% # attempts to use FU when none available
+ IntAlu 765509 6.22% # attempts to use FU when none available
IntMult 0 0.00% # attempts to use FU when none available
IntDiv 0 0.00% # attempts to use FU when none available
FloatAdd 0 0.00% # attempts to use FU when none available
FloatMult 0 0.00% # attempts to use FU when none available
FloatDiv 0 0.00% # attempts to use FU when none available
FloatSqrt 0 0.00% # attempts to use FU when none available
- MemRead 9173598 81.13% # attempts to use FU when none available
- MemWrite 1623963 14.36% # attempts to use FU when none available
+ MemRead 9714303 78.99% # attempts to use FU when none available
+ MemWrite 1818331 14.79% # attempts to use FU when none available
IprAccess 0 0.00% # attempts to use FU when none available
InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 6180887586
+system.cpu.iq.ISSUE:issued_per_cycle.samples 7529829639
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 4878979324 7893.65%
- 1 360055339 582.53%
- 2 481197713 778.53%
- 3 280796976 454.30%
- 4 94854448 153.46%
- 5 50760526 82.12%
- 6 26723872 43.24%
- 7 6795220 10.99%
- 8 724168 1.17%
+ 0 6294390011 8359.27%
+ 1 325228389 431.92%
+ 2 480486573 638.11%
+ 3 243738023 323.70%
+ 4 97825007 129.92%
+ 5 51561666 68.48%
+ 6 27659179 36.73%
+ 7 6861374 9.11%
+ 8 2079417 2.76%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 0.487271 # Inst issue rate
-system.cpu.iq.iqInstsAdded 4683985508 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3011765231 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 2916477755 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 6096386 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 3050829124 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 9178154 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 7336.712513 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2076.036854 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7008989 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 15914539999 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.236340 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2169165 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4503266483 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2169165 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244715 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2215400 # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate 0.013060 # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses 29315 # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate 0.013060 # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses 29315 # number of Writeback MSHR misses
+system.cpu.iq.ISSUE:rate 0.384756 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4389823309 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2897143990 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 2623608231 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 10330579 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 2673985156 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 9186210 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 7225.224344 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2102.004971 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7015727 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 15682226609 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.236276 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2170483 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 4562366056 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.236276 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2170483 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2244995 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2215762 # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate 0.013021 # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses 29233 # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate 0.013021 # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses 29233 # number of Writeback MSHR misses
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.252507 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.253196 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9178154 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 7336.712513 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7008989 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 15914539999 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.236340 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2169165 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9186210 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 7225.224344 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7015727 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 15682226609 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.236276 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2170483 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 4503266483 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.236340 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2169165 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 4562366056 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.236276 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2170483 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 11422869 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 7238.883228 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2076.036854 # average overall mshr miss latency
+system.cpu.l2cache.overall_accesses 11431205 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 7129.205138 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2102.004971 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 9224389 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15914539999 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.192463 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2198480 # number of overall misses
+system.cpu.l2cache.overall_hits 9231489 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 15682226609 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.192431 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2199716 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 4503266483 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.189897 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2169165 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 4562366056 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.189874 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2170483 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements 2136397 # number of replacements
-system.cpu.l2cache.sampled_refs 2169165 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2137715 # number of replacements
+system.cpu.l2cache.sampled_refs 2170483 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 32623.472165 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 9224389 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 520424000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1039341 # number of writebacks
-system.cpu.numCycles 6180887586 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2894504060 # Number of cycles rename is blocking
+system.cpu.l2cache.tagsinuse 32622.966749 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 9231489 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 513093000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1039675 # number of writebacks
+system.cpu.numCycles 7529829639 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 5035061268 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 6511750 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 1451413065 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 266047107 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 3125053 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 8501370508 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 6112671585 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 4584914520 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1056218413 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 501929792 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 276756270 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 3208711557 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 65986 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 1117979447 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed
-system.cpu.timesIdled 7293390 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 12523289 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 970889170 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 234469237 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 2022618 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 7453165021 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 5328451425 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 4004220538 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 843247999 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 417727902 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 262813407 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 2628017575 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 89893 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 51 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 1009480859 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 49 # count of temporary serializing insts renamed
+system.cpu.timesIdled 6494671 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
-0: system.remote_gdb.listener: listening for remote gdb on port 7006
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
+warn: Increasing stack size by one page.
[root]
type=Root
children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
+dummy=0
[system]
type=System
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
+cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
split_size=0
store_compressed=false
subblock_size=0
-tgts_per_mshr=5
+tgts_per_mshr=20
trace_addr=0
two_queue=false
write_buffers=8
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
output=cout
[root]
type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
+dummy=0
[system.physmem]
type=PhysicalMemory
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
input=cin
output=cout
env=
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/linux/o3-timing
+cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
system=system
uid=100
euid=100
clock=1
phase=0
numThreads=1
+cpu_id=0
activity=0
workload=system.cpu.workload
checker=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
block_size=64
latency=1
mshrs=10
-tgts_per_mshr=5
+tgts_per_mshr=20
write_buffers=8
prioritizeRequests=false
protocol=null
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 11848811 # Number of BTB hits
-global.BPredUnit.BTBLookups 15227898 # Number of BTB lookups
-global.BPredUnit.RASInCorrect 1227 # Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 2015952 # Number of conditional branches incorrect
-global.BPredUnit.condPredicted 12943595 # Number of conditional branches predicted
-global.BPredUnit.lookups 17560137 # Number of BP lookups
-global.BPredUnit.usedRAS 1685355 # Number of times the RAS was used to get a target.
-host_inst_rate 110871 # Simulator instruction rate (inst/s)
-host_mem_usage 184176 # Number of bytes of host memory used
-host_seconds 759.26 # Real time elapsed on the host
-host_tick_rate 138735 # Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 9867030 # Number of conflicting loads.
-memdepunit.memDep.conflictingStores 3328836 # Number of conflicting stores.
-memdepunit.memDep.insertedLoads 29553768 # Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 9396457 # Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 13130842 # Number of BTB hits
+global.BPredUnit.BTBLookups 17054746 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 1205 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1949700 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 14620230 # Number of conditional branches predicted
+global.BPredUnit.lookups 19607486 # Number of BP lookups
+global.BPredUnit.usedRAS 1766776 # Number of times the RAS was used to get a target.
+host_inst_rate 70212 # Simulator instruction rate (inst/s)
+host_mem_usage 153248 # Number of bytes of host memory used
+host_seconds 1198.94 # Real time elapsed on the host
+host_tick_rate 95357 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 19046664 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 5327434 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 34568849 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 10915344 # Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.000105 # Number of seconds simulated
-sim_ticks 105335101 # Number of ticks simulated
+sim_seconds 0.000114 # Number of seconds simulated
+sim_ticks 114327081 # Number of ticks simulated
system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3300349 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2895131 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle.samples 65617496
+system.cpu.commit.COM:committed_per_cycle.samples 73926385
system.cpu.commit.COM:committed_per_cycle.min_value 0
- 0 32041205 4883.03%
- 1 13628356 2076.94%
- 2 7878182 1200.62%
- 3 3859920 588.25%
- 4 2040157 310.92%
- 5 1456623 221.99%
- 6 796888 121.44%
- 7 615816 93.85%
- 8 3300349 502.97%
+ 0 37511035 5074.11%
+ 1 16507127 2232.91%
+ 2 8529257 1153.75%
+ 3 3749717 507.22%
+ 4 1879220 254.20%
+ 5 1361115 184.12%
+ 6 851721 115.21%
+ 7 642062 86.85%
+ 8 2895131 391.62%
system.cpu.commit.COM:committed_per_cycle.max_value 8
system.cpu.commit.COM:committed_per_cycle.end_dist
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2003468 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1937238 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 39205061 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 58539227 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 1.251312 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.251312 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 23022109 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 5495.207331 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4910.485944 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23021236 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4797316 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 873 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 375 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2445422 # number of ReadReq MSHR miss cycles
+system.cpu.cpi 1.358131 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.358131 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 23376895 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 5393.890593 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4863.252964 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23375917 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5275225 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.000042 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 978 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 472 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2460806 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 498 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 506 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 4880.722363 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 4578.932720 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6495178 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 28918280 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000911 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5925 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 4186 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 7962764 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 6579.789722 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 6507.873418 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6492638 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 55697920 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001302 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 8465 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6727 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 11310684 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1739 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs 2807.125000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets 3125.260571 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13194.641931 # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs 8 # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets 875 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs 22457 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets 2734603 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 1738 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs 2809.444444 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 13310.407754 # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs 9 # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs 25285 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29523212 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 4959.634598 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29516414 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 33715596 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 6798 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 4561 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10408186 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2237 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 29877998 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 6456.967595 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29868555 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 60973145 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000316 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9443 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 7199 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13771490 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2244 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses 29523212 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 4959.634598 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 4652.742959 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29516414 # number of overall hits
-system.cpu.dcache.overall_miss_latency 33715596 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 6798 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 4561 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10408186 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2237 # number of overall MSHR misses
+system.cpu.dcache.overall_accesses 29877998 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 6456.967595 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 6137.027629 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits 29868555 # number of overall hits
+system.cpu.dcache.overall_miss_latency 60973145 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000316 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9443 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 7199 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13771490 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2244 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements 158 # number of replacements
-system.cpu.dcache.sampled_refs 2237 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 160 # number of replacements
+system.cpu.dcache.sampled_refs 2244 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1400.647488 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29516414 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1415.957077 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29868555 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 105 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 2047370 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12661 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 2829477 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 146297095 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 36266329 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 27223403 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 6075840 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45354 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 80395 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 17560137 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 17576948 # Number of cache lines fetched
-system.cpu.fetch.Cycles 45711428 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 479088 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 150837354 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2061309 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.244934 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 17576948 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13534166 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.103924 # Number of inst fetches per cycle
+system.cpu.dcache.writebacks 106 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 5155486 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12562 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3109369 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 165294506 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 40322652 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 28299602 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8350763 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 41264 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 148646 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 19607486 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 19380281 # Number of cache lines fetched
+system.cpu.fetch.Cycles 48705122 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 491925 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 170506876 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2058666 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.238310 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 19380281 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 14897618 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.072348 # Number of inst fetches per cycle
system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist.samples 71693337
+system.cpu.fetch.rateDist.samples 82277149
system.cpu.fetch.rateDist.min_value 0
- 0 43559639 6075.83%
- 1 2788432 388.94%
- 2 2133609 297.60%
- 3 3200202 446.37%
- 4 4098889 571.73%
- 5 1363717 190.22%
- 6 1885995 263.06%
- 7 1651845 230.40%
- 8 11011009 1535.85%
+ 0 52952312 6435.85%
+ 1 3129610 380.37%
+ 2 1369966 166.51%
+ 3 2017219 245.17%
+ 4 3854384 468.46%
+ 5 1357405 164.98%
+ 6 1550178 188.41%
+ 7 1288552 156.61%
+ 8 14757523 1793.64%
system.cpu.fetch.rateDist.max_value 8
system.cpu.fetch.rateDist.end_dist
-system.cpu.icache.ReadReq_accesses 17576948 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 3407.568545 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 2506.978423 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 17563424 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 46083957 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000769 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 13524 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 3467 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25212682 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000572 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10057 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets 3513.269231 # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1746.387988 # Average number of references to valid blocks.
+system.cpu.icache.ReadReq_accesses 19380281 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 3416.377011 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 2534.518183 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 19366483 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 47139170 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000712 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 13798 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 3761 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25438959 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000518 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10037 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.icache.avg_refs 1929.509116 # Average number of references to valid blocks.
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets 26 # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets 91345 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 17576948 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 3407.568545 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
-system.cpu.icache.demand_hits 17563424 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 46083957 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000769 # miss rate for demand accesses
-system.cpu.icache.demand_misses 13524 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 3467 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25212682 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000572 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10057 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 19380281 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 3416.377011 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency
+system.cpu.icache.demand_hits 19366483 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 47139170 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000712 # miss rate for demand accesses
+system.cpu.icache.demand_misses 13798 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 3761 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25438959 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000518 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10037 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses 17576948 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 3407.568545 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 2506.978423 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 17563424 # number of overall hits
-system.cpu.icache.overall_miss_latency 46083957 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000769 # miss rate for overall accesses
-system.cpu.icache.overall_misses 13524 # number of overall misses
-system.cpu.icache.overall_mshr_hits 3467 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25212682 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000572 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10057 # number of overall MSHR misses
+system.cpu.icache.overall_accesses 19380281 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 3416.377011 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 2534.518183 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits 19366483 # number of overall hits
+system.cpu.icache.overall_miss_latency 47139170 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000712 # miss rate for overall accesses
+system.cpu.icache.overall_misses 13798 # number of overall misses
+system.cpu.icache.overall_mshr_hits 3761 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25438959 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000518 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10037 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements 8145 # number of replacements
-system.cpu.icache.sampled_refs 10057 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8123 # number of replacements
+system.cpu.icache.sampled_refs 10037 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1487.085502 # Cycle average of tags in use
-system.cpu.icache.total_refs 17563424 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1498.249784 # Cycle average of tags in use
+system.cpu.icache.total_refs 19366483 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 33641765 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12581618 # Number of branches executed
-system.cpu.iew.EXEC:nop 11617565 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.388001 # Inst execution rate
-system.cpu.iew.EXEC:refs 31473535 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7134398 # Number of stores executed
+system.cpu.idleCycles 32049933 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12923262 # Number of branches executed
+system.cpu.iew.EXEC:nop 13162253 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.241494 # Inst execution rate
+system.cpu.iew.EXEC:refs 31990682 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7220394 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 88408054 # num instructions consuming a value
-system.cpu.iew.WB:count 97920299 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.731090 # average fanout of values written-back
+system.cpu.iew.WB:consumers 91915926 # num instructions consuming a value
+system.cpu.iew.WB:count 100065162 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.718590 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 64634219 # num instructions producing a value
-system.cpu.iew.WB:rate 1.365821 # insts written-back per cycle
-system.cpu.iew.WB:sent 98494929 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2154192 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 104376 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 29553768 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 2191495 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 9396457 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 131107086 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24339137 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2193063 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 99510422 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 16363 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 66049838 # num instructions producing a value
+system.cpu.iew.WB:rate 1.216196 # insts written-back per cycle
+system.cpu.iew.WB:sent 100916733 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2084205 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 596692 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 34568849 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 437 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 864110 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 10915344 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 150440832 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24770288 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2226727 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 102146587 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 177017 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 879 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 6075840 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 34734 # Number of cycles IEW is unblocking
-system.cpu.iew.lsq.thread.0.blockedLoads 9915 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 36009 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 941599 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 3004 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.iewLSQFullEvents 827 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8350763 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 211777 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 3149 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 865223 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 1107 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 23070 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9915 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 9519355 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2893762 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 23070 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 196104 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1958088 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.799161 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.799161 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0 101703485 # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 167324 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9618 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 14534436 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4412649 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 167324 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 194984 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1889221 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.736306 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.736306 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 104373314 # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.start_dist
(null) 7 0.00% # Type of FU issued
- IntAlu 62578225 61.53% # Type of FU issued
- IntMult 472394 0.46% # Type of FU issued
+ IntAlu 64752207 62.04% # Type of FU issued
+ IntMult 471285 0.45% # Type of FU issued
IntDiv 0 0.00% # Type of FU issued
- FloatAdd 2776755 2.73% # Type of FU issued
- FloatCmp 115486 0.11% # Type of FU issued
- FloatCvt 2376016 2.34% # Type of FU issued
- FloatMult 302348 0.30% # Type of FU issued
- FloatDiv 754954 0.74% # Type of FU issued
- FloatSqrt 321 0.00% # Type of FU issued
- MemRead 25019338 24.60% # Type of FU issued
- MemWrite 7307641 7.19% # Type of FU issued
+ FloatAdd 2789912 2.67% # Type of FU issued
+ FloatCmp 115515 0.11% # Type of FU issued
+ FloatCvt 2364267 2.27% # Type of FU issued
+ FloatMult 305289 0.29% # Type of FU issued
+ FloatDiv 755087 0.72% # Type of FU issued
+ FloatSqrt 324 0.00% # Type of FU issued
+ MemRead 25418322 24.35% # Type of FU issued
+ MemWrite 7401099 7.09% # Type of FU issued
IprAccess 0 0.00% # Type of FU issued
InstPrefetch 0 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0.end_dist
-system.cpu.iq.ISSUE:fu_busy_cnt 1392706 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.013694 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_cnt 1952486 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018707 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full.start_dist
-(null) 0 0.00% # attempts to use FU when none available
-IntAlu 193189 13.87% # attempts to use FU when none available
-IntMult 0 0.00% # attempts to use FU when none available
-IntDiv 0 0.00% # attempts to use FU when none available
-FloatAdd 1883 0.14% # attempts to use FU when none available
-FloatCmp 96 0.01% # attempts to use FU when none available
-FloatCvt 2836 0.20% # attempts to use FU when none available
-FloatMult 2464 0.18% # attempts to use FU when none available
-FloatDiv 659899 47.38% # attempts to use FU when none available
-FloatSqrt 0 0.00% # attempts to use FU when none available
-MemRead 465101 33.40% # attempts to use FU when none available
-MemWrite 67238 4.83% # attempts to use FU when none available
-IprAccess 0 0.00% # attempts to use FU when none available
-InstPrefetch 0 0.00% # attempts to use FU when none available
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 163325 8.36% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 1017 0.05% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 12505 0.64% # attempts to use FU when none available
+ FloatMult 2432 0.12% # attempts to use FU when none available
+ FloatDiv 905685 46.39% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 774173 39.65% # attempts to use FU when none available
+ MemWrite 93349 4.78% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full.end_dist
system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle.samples 71693337
+system.cpu.iq.ISSUE:issued_per_cycle.samples 82277149
system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
- 0 27977053 3902.32%
- 1 15408153 2149.18%
- 2 12854527 1792.99%
- 3 7056557 984.27%
- 4 4494209 626.87%
- 5 2427532 338.60%
- 6 1097338 153.06%
- 7 305661 42.63%
- 8 72307 10.09%
+ 0 35738506 4343.67%
+ 1 18264427 2219.87%
+ 2 12740961 1548.54%
+ 3 6961052 846.05%
+ 4 4806764 584.22%
+ 5 2441659 296.76%
+ 6 994924 120.92%
+ 7 291934 35.48%
+ 8 36922 4.49%
system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
system.cpu.iq.ISSUE:issued_per_cycle.end_dist
-system.cpu.iq.ISSUE:rate 1.418590 # Inst issue rate
-system.cpu.iq.iqInstsAdded 119489085 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 101703485 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 34413373 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 132312 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 28441004 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.l2cache.ReadReq_accesses 12293 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 3855.809345 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2071.040418 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7221 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19556665 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.412593 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 5072 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10504317 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.412593 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 5072 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 105 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 105 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.444401 # Average number of references to valid blocks.
+system.cpu.iq.ISSUE:rate 1.268558 # Inst issue rate
+system.cpu.iq.iqInstsAdded 137278142 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 104373314 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 437 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 52505275 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 293840 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 49588547 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.l2cache.ReadReq_accesses 12278 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 4378.207161 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2293.937242 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7195 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 22254427 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.413993 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 5083 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11660083 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.413993 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 5083 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs 1.436356 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12293 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 3855.809345 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7221 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 19556665 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.412593 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5072 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12278 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 4378.207161 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7195 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 22254427 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.413993 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5083 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 10504317 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.412593 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5072 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 11660083 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.413993 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5083 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses 12398 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 3855.809345 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 2071.040418 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7326 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 19556665 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.409098 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5072 # number of overall misses
+system.cpu.l2cache.overall_accesses 12384 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 4378.207161 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 2293.937242 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits 7301 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 22254427 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.410449 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5083 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 10504317 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.409098 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5072 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 11660083 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.410449 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5083 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 5072 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 5083 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3261.872945 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7326 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3292.223620 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7301 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 71693337 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 812700 # Number of cycles rename is blocking
+system.cpu.numCycles 82277149 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2387077 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 369396 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 37208342 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 772307 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 122 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 182866276 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 141908898 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 104156212 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 26334995 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 6075840 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1200845 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 35728851 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 60615 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 555 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2896644 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 544 # count of temporary serializing insts renamed
-system.cpu.timesIdled 10380 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 1473927 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 41553511 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1059964 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 61 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 206590907 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 160246119 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 117849091 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 27232157 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8350763 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2654523 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 49421730 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 99118 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 461 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 5497153 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 451 # count of temporary serializing insts renamed
+system.cpu.timesIdled 10204 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
- 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46
+ 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
- 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48
+ 40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
warn: Entering event queue @ 0. Starting simulation...
+warn: Increasing stack size by one page.
projects / gem5.git / commitdiff