radv: move calculating the vertex sgpr to the pipeline.

There is no need to calculate this at draw time.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 851b2cae6bbbfc7bd689ec2c27d90d93c8c8ff8d..0e2ae31f7d0e38f4e1cc893efeb688ba01848ac6 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2618,22 +2618,14 @@ void radv_CmdDraw(
 
        MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
 
-       struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
-                                                            AC_UD_VS_BASE_VERTEX_START_INSTANCE);
-       if (loc->sgpr_idx != -1) {
-               uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
-                                                               radv_pipeline_has_tess(cmd_buffer->state.pipeline));
-               int vs_num = 2;
-               if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
-                       vs_num = 3;
-
-               assert (loc->num_sgprs == vs_num);
-               radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
-               radeon_emit(cmd_buffer->cs, firstVertex);
-               radeon_emit(cmd_buffer->cs, firstInstance);
-               if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
-                       radeon_emit(cmd_buffer->cs, 0);
-       }
+       assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
+       radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
+                             cmd_buffer->state.pipeline->graphics.vtx_emit_num);
+       radeon_emit(cmd_buffer->cs, firstVertex);
+       radeon_emit(cmd_buffer->cs, firstInstance);
+       if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
+               radeon_emit(cmd_buffer->cs, 0);
+
        radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
        radeon_emit(cmd_buffer->cs, instanceCount);
 
@@ -2678,22 +2670,14 @@ void radv_CmdDrawIndexed(
                radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
        }
 
-       struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
-                                                            AC_UD_VS_BASE_VERTEX_START_INSTANCE);
-       if (loc->sgpr_idx != -1) {
-               uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
-                                                               radv_pipeline_has_tess(cmd_buffer->state.pipeline));
-               int vs_num = 2;
-               if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
-                       vs_num = 3;
-
-               assert (loc->num_sgprs == vs_num);
-               radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vs_num);
-               radeon_emit(cmd_buffer->cs, vertexOffset);
-               radeon_emit(cmd_buffer->cs, firstInstance);
-               if (cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
-                       radeon_emit(cmd_buffer->cs, 0);
-       }
+       assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
+       radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
+                             cmd_buffer->state.pipeline->graphics.vtx_emit_num);
+       radeon_emit(cmd_buffer->cs, vertexOffset);
+       radeon_emit(cmd_buffer->cs, firstInstance);
+       if (cmd_buffer->state.pipeline->graphics.vtx_emit_num == 3)
+               radeon_emit(cmd_buffer->cs, 0);
+
        radeon_emit(cmd_buffer->cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
        radeon_emit(cmd_buffer->cs, instanceCount);
 
@@ -2738,13 +2722,10 @@ radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
                return;
 
        cmd_buffer->device->ws->cs_add_buffer(cs, buffer->bo, 8);
-
-       struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.pipeline, MESA_SHADER_VERTEX,
-                                                            AC_UD_VS_BASE_VERTEX_START_INSTANCE);
-       uint32_t base_reg = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(cmd_buffer->state.pipeline),
-                                                       radv_pipeline_has_tess(cmd_buffer->state.pipeline));
        bool draw_id_enable = cmd_buffer->state.pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id;
-       assert(loc->sgpr_idx != -1);
+       uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;
+       assert(base_reg);
+
        radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
        radeon_emit(cs, 1);
        radeon_emit(cs, indirect_va);
@@ -2754,9 +2735,9 @@ radv_emit_indirect_draw(struct radv_cmd_buffer *cmd_buffer,
                                       PKT3_DRAW_INDIRECT_MULTI,
                             8, false));
        radeon_emit(cs, 0);
-       radeon_emit(cs, ((base_reg + loc->sgpr_idx * 4) - SI_SH_REG_OFFSET) >> 2);
-       radeon_emit(cs, ((base_reg + (loc->sgpr_idx + 1) * 4) - SI_SH_REG_OFFSET) >> 2);
-       radeon_emit(cs, (((base_reg + (loc->sgpr_idx + 2) * 4) - SI_SH_REG_OFFSET) >> 2) |
+       radeon_emit(cs, (base_reg - SI_SH_REG_OFFSET) >> 2);
+       radeon_emit(cs, ((base_reg + 4) - SI_SH_REG_OFFSET) >> 2);
+       radeon_emit(cs, (((base_reg + 8) - SI_SH_REG_OFFSET) >> 2) |
                        S_2C3_DRAW_INDEX_ENABLE(draw_id_enable) |
                        S_2C3_COUNT_INDIRECT_ENABLE(!!count_va));
        radeon_emit(cs, draw_count); /* count */

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 6671acd66336df14b2d7d4adb142160779acb323..e77f9597bac362955771632bd25bc5e96601ca82 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2206,6 +2206,16 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
                pipeline->binding_stride[desc->binding] = desc->stride;
        }
 
+       struct ac_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
+                                                            AC_UD_VS_BASE_VERTEX_START_INSTANCE);
+       if (loc->sgpr_idx != -1) {
+               pipeline->graphics.vtx_base_sgpr = radv_shader_stage_to_user_data_0(MESA_SHADER_VERTEX, radv_pipeline_has_gs(pipeline), radv_pipeline_has_tess(pipeline));
+               pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
+               if (pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.needs_draw_id)
+                       pipeline->graphics.vtx_emit_num = 3;
+               else
+                       pipeline->graphics.vtx_emit_num = 2;
+       }
        if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
                radv_dump_pipeline_stats(device, pipeline);
        }

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e31ea2b5e94e7712b346a9390dca16a86bd99628..13f298e72e90ea57923904e0ae07bd012e7cec34 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1077,6 +1077,8 @@ struct radv_pipeline {
                        uint32_t ps_input_cntl_num;
                        uint32_t pa_cl_vs_out_cntl;
                        uint32_t vgt_shader_stages_en;
+                       uint32_t vtx_base_sgpr;
+                       uint8_t vtx_emit_num;
                        struct radv_prim_vertex_count prim_vertex_count;
                        bool can_use_guardband;
                } graphics;