implement the Tcc instruction to call syscall.

arch/sparc/isa/bitfields.isa:
    the trap field is 7:0
arch/sparc/isa/decoder.isa:
    add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
    We need the syscall num register

--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a

diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
index b0ac57575e06cd2cc01fdfd6847a676f20a86dcb..237f0fa6427bbac331127dbc73e637cb7d937a7a 100644 (file)
--- a/arch/sparc/isa/bitfields.isa
+++ b/arch/sparc/isa/bitfields.isa
@@ -46,5 +46,5 @@ def bitfield SHCNT64  <5:0>;
 def bitfield SIMM10    <9:0>;
 def bitfield SIMM11    <10:0>;
 def bitfield SIMM13    <12:0>;
-def bitfield SW_TRAP   <6:0>;
+def bitfield SW_TRAP   <7:0>;
 def bitfield X         <12>;

diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index eaf3aab3b4d2b2c71ec79fc70c78ba65a9612f18..716653d840c33b66d0e829c6818cdc01d5aa3d0e 100644 (file)
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -532,12 +532,26 @@ decode OP default Trap::unknown({{IllegalInstruction}}) {
                                         case 1: case 3:
                                                 throw illegal_instruction;
                                         case 0:
+#if FULL_SYSTEM
+                                                throw trap_instruction;
+#else
                                                 if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
-                                                        throw trap_instruction;
+                                                    // At least glibc only uses trap 0,
+                                                    // solaris/sunos may use others
+                                                    assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+                                                    xc->syscall();
+#endif
                                         break;
                                         case 2:
+#if FULL_SYSTEM
+                                                throw trap_instruction;
+#else
                                                 if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
-                                                        throw trap_instruction;
+                                                    // At least glibc only uses trap 0,
+                                                    // solaris/sunos may use others
+                                                    assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+                                                    xc->syscall();
+#endif
                                         break;
                                 }
                         }}); //Tcc

diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 23e3dad74a54e8abc4c7a30a075afed909573f63..ad8ae5c8dc71d1ee730fd963948778f63cce00a2 100644 (file)
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -106,6 +106,7 @@ namespace SparcISA
     const int ArgumentReg3 = 11;
     const int ArgumentReg4 = 12;
     const int ArgumentReg5 = 13;
+    const int SyscallNumReg = 1;
     // Some OS syscall sue a second register (o1) to return a second value
     const int SyscallPseudoReturnReg = ArgumentReg1;