type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch32.ll_20131205.0-gem5
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linux-aarch32-ael.img
read_only=true
[system.clk_domain]
[system.cpu0.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
[system.cpu0.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.cpu0.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu1.isa]
type=ArmISA
+decoderFlavour=Generic
eventq_index=0
fpsid=1090793632
id_aa64afr0_el1=0
[system.cpu1.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+[system.cpu1.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: instruction 'mcr dcisw' unimplemented
-warn: CP14 unimplemented crn[9], opc1[1], crm[0], opc2[2]
+warn: CP14 unimplemented crn[3], opc1[2], crm[8], opc2[2]
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 14 2015 23:52:21
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Oct 10 2015 11:28:39
+gem5 started Oct 10 2015 11:45:23
+gem5 executing on artery, pid 26655
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch32.ll_20131205.0-gem5
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
-Exiting @ tick 2825405893500 because m5_exit instruction encountered
+Exiting @ tick 2627260787000 because m5_exit instruction encountered
sim_ticks 2627260787000 # Number of ticks simulated
final_tick 2627260787000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87166 # Simulator instruction rate (inst/s)
-host_op_rate 105753 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1901847747 # Simulator tick rate (ticks/s)
-host_mem_usage 660800 # Number of bytes of host memory used
-host_seconds 1381.43 # Real time elapsed on the host
+host_inst_rate 73269 # Simulator instruction rate (inst/s)
+host_op_rate 88893 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1598642516 # Simulator tick rate (ticks/s)
+host_mem_usage 609448 # Number of bytes of host memory used
+host_seconds 1643.43 # Real time elapsed on the host
sim_insts 120413300 # Number of instructions simulated
sim_ops 146090184 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.iew.iewIQFullEvents 24988 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 163669 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 18608 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 265561 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 265563 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 373947 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 639508 # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts 639510 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 94079743 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 17020662 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 955277 # Number of squashed instructions skipped in execute
ata1.00: configured for UDMA/33\r
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)\r
-sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sd 0:0:0:0: [sda] Write Protect is off\r
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+sd 0:0:0:0: Attached scsi generic sg0 type 0\r
sda: sda1\r
sd 0:0:0:0: [sda] Attached SCSI disk\r
e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu0.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.cpu0.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu1.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+[system.cpu1.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 14 2015 23:38:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 02:13:35
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47482239150000 because m5_exit instruction encountered
+Exiting @ tick 47573912126000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 47.464182 # Number of seconds simulated
-sim_ticks 47464181819000 # Number of ticks simulated
-final_tick 47464181819000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.573912 # Number of seconds simulated
+sim_ticks 47573912126000 # Number of ticks simulated
+final_tick 47573912126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 165089 # Simulator instruction rate (inst/s)
-host_op_rate 194182 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9130718670 # Simulator tick rate (ticks/s)
-host_mem_usage 773696 # Number of bytes of host memory used
-host_seconds 5198.30 # Real time elapsed on the host
-sim_insts 858179266 # Number of instructions simulated
-sim_ops 1009414094 # Number of ops (including micro ops) simulated
+host_inst_rate 125865 # Simulator instruction rate (inst/s)
+host_op_rate 148024 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6578075559 # Simulator tick rate (ticks/s)
+host_mem_usage 723980 # Number of bytes of host memory used
+host_seconds 7232.19 # Real time elapsed on the host
+sim_insts 910282032 # Number of instructions simulated
+sim_ops 1070541696 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 85568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 76544 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 6880896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 37557256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 10768960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 75264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 68480 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3528576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 13557136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 8552832 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 436032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81587544 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 6880896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3528576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 10409472 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 64065088 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 153088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 136640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 7678784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 42964232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 17895808 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 154176 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 129664 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 3679616 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 16152336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 14975872 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 446400 # Number of bytes read from this memory
+system.physmem.bytes_read::total 104366616 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 7678784 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 3679616 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 11358400 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 83323200 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 64085672 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1337 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1196 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 107514 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 586845 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 168265 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1176 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1070 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 55134 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 211843 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 133638 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6813 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1274831 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1001017 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 83343784 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2392 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2135 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 119981 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 671329 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 279622 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2409 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2026 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 57494 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 252393 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 233998 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6975 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1630754 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1301925 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1003591 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1803 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1613 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 144970 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 791276 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.itb.walker 1443 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.data 285629 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::realview.ide 9187 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1718929 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 144970 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 219312 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bytesReadWrQ 42368 # Total number of bytes read from write queue
-system.physmem.bytesWritten 64084800 # Total number of bytes written to DRAM
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system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 47464179840500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::stdev 249.999790 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 37995 4.99% 100.00% # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 22.692705 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 368.089974 # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::30 88789 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 82985 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 78170 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 2650 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1644 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1156 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 850 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 729 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 549 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 468 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 450 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 298 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 272 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 313 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 286 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 360 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 287 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 263 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 251 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 273 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 174 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 172 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 91 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 114 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 105 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 169 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1008532 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 186.082044 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 114.846498 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 242.592795 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 603416 59.83% 59.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 198742 19.71% 79.54% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 66381 6.58% 86.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 35101 3.48% 89.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 23988 2.38% 91.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 15328 1.52% 93.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 10269 1.02% 94.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 9973 0.99% 95.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 45334 4.50% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1008532 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 74360 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 21.921678 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 319.874978 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-4095 74357 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::81920-86015 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 56148 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 56148 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.833672 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.227387 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.381246 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 52715 93.89% 93.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 1304 2.32% 96.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 213 0.38% 96.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 294 0.52% 97.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 73 0.13% 97.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 309 0.55% 97.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 189 0.34% 98.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 132 0.24% 98.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 76 0.14% 98.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 103 0.18% 98.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 49 0.09% 98.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 61 0.11% 98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 401 0.71% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 39 0.07% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 42 0.07% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 82 0.15% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 14 0.02% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 6 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 25 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 3 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::168-171 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::188-191 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 56148 # Writes before turning the bus around for reads
-system.physmem.totQLat 34002300770 # Total ticks spent queuing
-system.physmem.totMemAccLat 57892969520 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6370845000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 26685.86 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 74360 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 74360 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.512601 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.043743 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 6.433062 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 70224 94.44% 94.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 1905 2.56% 97.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 313 0.42% 97.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 309 0.42% 97.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 95 0.13% 97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 310 0.42% 98.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 189 0.25% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 82 0.11% 98.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 85 0.11% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 110 0.15% 99.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 46 0.06% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 59 0.08% 99.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 410 0.55% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 26 0.03% 99.74% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 24 0.03% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 107 0.14% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 6 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 4 0.01% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 3 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 3 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 28 0.04% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 74360 # Writes before turning the bus around for reads
+system.physmem.totQLat 52515283986 # Total ticks spent queuing
+system.physmem.totMemAccLat 83079846486 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 8150550000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 32215.79 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 45435.86 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.72 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.72 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 50965.79 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.67 # Average write queue length when enqueuing
-system.physmem.readRowHits 1026298 # Number of row buffer hits during reads
-system.physmem.writeRowHits 488335 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.55 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 48.77 # Row buffer hit rate for writes
-system.physmem.avgGap 20832040.70 # Average gap between requests
-system.physmem.pageHitRate 66.56 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2867901120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1564827000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4814050800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3248307360 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1185321114675 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27438751602000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31736697181275 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.645246 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45646225461150 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1584933220000 # Time in different power states
+system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing
+system.physmem.readRowHits 1305984 # Number of row buffer hits during reads
+system.physmem.writeRowHits 617830 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.12 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 47.44 # Row buffer hit rate for writes
+system.physmem.avgGap 16207771.58 # Average gap between requests
+system.physmem.pageHitRate 65.61 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3848576760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2099917875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 6284834400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4250627280 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1215004983300 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27478552093500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31817337547515 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.798037 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45712218150079 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1588597400000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 233019608850 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 273094361171 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2884185360 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1573712250 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 5124397200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3240278640 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3100129378320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1191686941080 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27433167543750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31737806436600 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.668617 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45636858751692 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1584933220000 # Time in different power states
+system.physmem_1.actEnergy 3775925160 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2060276625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 6429961200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4187868480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3107296514400 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1217449094850 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27476408136000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31817607776715 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.803717 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45708592383178 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1588597400000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 242386318308 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 276721037822 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 135703894 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 95425291 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6312333 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 100672877 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 73270894 # Number of BTB hits
+system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
+system.cpu0.branchPred.lookups 141076080 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 100250771 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6354710 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 105662880 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 77608899 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.781166 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 16275299 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1070570 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 73.449540 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 16417680 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1072595 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 277006 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 277006 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8797 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76685 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 277006 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 277006 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 277006 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 85482 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 21392.901430 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 19388.852647 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 17614.753194 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 84631 99.00% 99.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 172 0.20% 99.21% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 584 0.68% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 16 0.02% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 33 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 27 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 302583 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 302583 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11677 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91984 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 302583 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 302583 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 302583 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 103661 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 22488.718033 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 20252.846239 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 20697.815033 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 102356 98.74% 98.74% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 167 0.16% 98.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 962 0.93% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 38 0.04% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 45 0.04% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 22 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 13 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 85482 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 103661 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples -910187592 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 -910187592 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total -910187592 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 76685 89.71% 89.71% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8797 10.29% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 85482 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 277006 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 91984 88.74% 88.74% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11677 11.26% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 103661 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 302583 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 277006 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85482 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 302583 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 103661 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85482 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 362488 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 103661 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 406244 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 88941283 # DTB read hits
-system.cpu0.dtb.read_misses 229899 # DTB read misses
-system.cpu0.dtb.write_hits 77314134 # DTB write hits
-system.cpu0.dtb.write_misses 47107 # DTB write misses
+system.cpu0.dtb.read_hits 91224751 # DTB read hits
+system.cpu0.dtb.read_misses 252123 # DTB read misses
+system.cpu0.dtb.write_hits 79969156 # DTB write hits
+system.cpu0.dtb.write_misses 50460 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 37002 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 982 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 8335 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 39295 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 989 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 11229 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10385 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 89171182 # DTB read accesses
-system.cpu0.dtb.write_accesses 77361241 # DTB write accesses
+system.cpu0.dtb.perms_faults 11007 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 91476874 # DTB read accesses
+system.cpu0.dtb.write_accesses 80019616 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 166255417 # DTB hits
-system.cpu0.dtb.misses 277006 # DTB misses
-system.cpu0.dtb.accesses 166532423 # DTB accesses
+system.cpu0.dtb.hits 171193907 # DTB hits
+system.cpu0.dtb.misses 302583 # DTB misses
+system.cpu0.dtb.accesses 171496490 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 67964 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 67964 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 522 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 55569 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 67964 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 67964 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 67964 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 56091 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 23783.423366 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21371.413212 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 19530.956784 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 52347 93.33% 93.33% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 2944 5.25% 98.57% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 5 0.01% 98.58% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 1 0.00% 98.58% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 475 0.85% 99.43% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 248 0.44% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 15 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 9 0.02% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 29 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-425983 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 56091 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 69790 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 704 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58261 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 58965 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 25666.514034 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 22346.910344 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 25122.368024 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 57570 97.63% 97.63% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 8 0.01% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 1255 2.13% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 40 0.07% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 50 0.08% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 58965 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -911302092 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -911302092 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -911302092 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 55569 99.07% 99.07% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 522 0.93% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 56091 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 58261 98.81% 98.81% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 704 1.19% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 58965 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67964 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67964 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56091 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56091 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 124055 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 243132835 # ITB inst hits
-system.cpu0.itb.inst_misses 67964 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58965 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58965 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 128755 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 253370493 # ITB inst hits
+system.cpu0.itb.inst_misses 69790 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26811 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 28357 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 210881 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 216294 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 243200799 # ITB inst accesses
-system.cpu0.itb.hits 243132835 # DTB hits
-system.cpu0.itb.misses 67964 # DTB misses
-system.cpu0.itb.accesses 243200799 # DTB accesses
-system.cpu0.numCycles 1024570142 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 253440283 # ITB inst accesses
+system.cpu0.itb.hits 253370493 # DTB hits
+system.cpu0.itb.misses 69790 # DTB misses
+system.cpu0.itb.accesses 253440283 # DTB accesses
+system.cpu0.numCycles 1081338531 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 453671847 # Number of instructions committed
-system.cpu0.committedOps 532972040 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 44332709 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 5117 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93904749601 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.258395 # CPI: cycles per instruction
-system.cpu0.ipc 0.442792 # IPC: instructions per cycle
+system.cpu0.committedInsts 467223626 # Number of instructions committed
+system.cpu0.committedOps 548903732 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 48040966 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 5433 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 94067362325 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.314392 # CPI: cycles per instruction
+system.cpu0.ipc 0.432079 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6224 # number of quiesce instructions executed
-system.cpu0.tickCycles 727182617 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 297387525 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 5606815 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 475.898466 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 157812679 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5607327 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.144012 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 5510 # number of quiesce instructions executed
+system.cpu0.tickCycles 755200178 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 326138353 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 5943709 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 508.631098 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 162232873 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5944219 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 27.292546 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7690193000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.898466 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929489 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.929489 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 36 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 335393662 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 335393662 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 81544003 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 81544003 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 71771704 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 71771704 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 253031 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 253031 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 130003 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 130003 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1818235 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1818235 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1799115 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1799115 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 153315707 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 153315707 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 153568738 # number of overall hits
-system.cpu0.dcache.overall_hits::total 153568738 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 3470214 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 3470214 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 2296821 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2296821 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 622517 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 622517 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 787681 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 787681 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 168627 # number of LoadLockedReq misses
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system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2444404000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2533371000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2533371000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4977775000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4977775000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035840 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035840 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018129 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018129 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.704531 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.704531 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.858263 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.858263 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063226 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063226 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.093542 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.093542 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027594 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.027594 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031299 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.031299 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14774.023355 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14774.023355 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22510.680233 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22510.680233 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25559.471412 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25559.471412 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 88661.639458 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 88661.639458 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13726.124613 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13726.124613 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23062.365012 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23062.365012 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 3994886 # number of writebacks
+system.cpu0.dcache.writebacks::total 3994886 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 471328 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 471328 # number of ReadReq MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_hits::total 1040644 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 61 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total 61 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 43748 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 43748 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.StoreCondReq_mshr_hits::total 50 # number of StoreCondReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 1511972 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 3205622 # number of ReadReq MSHR misses
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5031000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2448224000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4983420500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036778 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036778 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.730812 # mshr miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.862509 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.862509 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064132 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064132 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098322 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098322 # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032504 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032504 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16015.338365 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16015.338365 # average ReadReq mshr miss latency
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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23321.922158 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26671.288533 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26671.288533 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 94425.715856 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 94425.715856 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14798.064316 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14798.064316 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22867.944886 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22867.944886 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17140.597325 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17140.597325 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 18177.882470 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18177.882470 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167138.735043 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 167138.735043 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163633.316109 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163633.316109 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 165336.134454 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 165336.134454 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18297.962780 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18297.962780 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19383.871864 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166693.266154 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 166693.266154 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162898.959070 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162898.959070 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 164741.173554 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 9688574 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.890007 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 233226662 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 9689086 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 24.071069 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 9691826 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.890260 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 243455405 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 9692338 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 25.118336 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 41394292000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.890007 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999785 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999785 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 168 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 495520584 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 495520584 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 233226662 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 233226662 # number of ReadReq hits
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-system.cpu0.icache.overall_hits::total 233226662 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 9689087 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 9689087 # number of ReadReq misses
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-system.cpu0.icache.demand_misses::total 9689087 # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::total 9689087 # number of overall misses
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-system.cpu0.icache.ReadReq_miss_latency::total 100299166000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 100299166000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 100299166000 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::total 100299166000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 242915749 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 242915749 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.overall_accesses::cpu0.inst 242915749 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 242915749 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.039887 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.039887 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.039887 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.039887 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.039887 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.039887 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10351.766477 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 10351.766477 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 10351.766477 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10351.766477 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 10351.766477 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 515987824 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 515987824 # Number of data accesses
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+system.cpu0.icache.ReadReq_hits::total 243455405 # number of ReadReq hits
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+system.cpu0.icache.overall_hits::total 243455405 # number of overall hits
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+system.cpu0.icache.ReadReq_misses::total 9692338 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 9692338 # number of demand (read+write) misses
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system.cpu0.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average ReadReq mshr uncacheable latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 141723.240743 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 141723.240743 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu0.l2cache.tags.warmup_cycle 38485430000 # Cycle when the warmup percentage was hit.
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 83.268968 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4373.710312 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3617.876682 # Average occupied blocks per requestor
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-system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27749596500 # number of demand (read+write) miss cycles
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+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 25660880000 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 25660880000 # number of ReadCleanReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39766543496 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39766543496 # number of ReadSharedReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 68436707000 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 68436707000 # number of InvalidateReq MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 527895500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 421006000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 25660880000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 55783526996 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.demand_mshr_miss_latency::total 82393308496 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 527895500 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 421006000 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 25660880000 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 55783526996 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 53668708822 # number of overall MSHR miss cycles
+system.cpu0.l2cache.overall_mshr_miss_latency::total 136062017318 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2327318500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9322247500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2417234500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2417234500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2330678000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9325607000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2418455500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2418455500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 6994929000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4744553000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11739482000 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028221 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4749133500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11744062500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.028589 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.581400 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.581400 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.812294 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.812294 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.552649 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.552649 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.816952 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.816952 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220723 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220723 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.079737 # mshr miss rate for ReadCleanReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.257800 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.257800 # mshr miss rate for ReadSharedReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.729915 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.729915 # mshr miss rate for InvalidateReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.132046 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022391 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045377 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079737 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.249324 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.215996 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.215996 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.084825 # mshr miss rate for ReadCleanReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.266802 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.266802 # mshr miss rate for ReadSharedReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.750042 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.750042 # mshr miss rate for InvalidateReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.139080 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022130 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049197 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.084825 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.254979 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.175963 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 33854.016150 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49505.517456 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35031.209739 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35031.209739 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19034.642232 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19034.642232 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 2006500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2006500 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56469.039844 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56469.039844 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29917.465826 # average ReadCleanReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 33190.748353 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 33190.748353 # average ReadSharedReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 110987.907308 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 110987.907308 # average InvalidateReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34804.523098 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 32235.647650 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 36204.403335 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29917.465826 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37902.087304 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49505.517456 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38473.617152 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.187852 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 44339.119667 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 70126.299396 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35057.911511 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35057.911511 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18692.313416 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18692.313416 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 571562.375000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 571562.375000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60685.103586 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60685.103586 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31211.654222 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 36995.024259 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 36995.024259 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 115692.637341 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 115692.637341 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 37753.359129 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41853.286292 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 47906.918525 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31211.654222 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 41665.193013 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 70126.299396 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46158.314401 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 159132.888889 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139275.218872 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 156131.927400 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 156131.927400 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158689.861783 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 139196.474416 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155397.770353 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155397.770353 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 133723.240743 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 157589.696748 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142441.783149 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 156996.148760 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 142250.542037 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 31422927 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16035788 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 525852 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 525836 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 16 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 867706 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 14437095 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 15482 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 15482 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 5117037 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 13614128 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 885080 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 435794 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 332763 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 479351 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 73 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1199260 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1131949 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9689087 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4838943 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 791881 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 786200 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29170184 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18058991 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 372221 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1095581 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 48696977 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623449216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 561436611 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1353296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3982960 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1190222083 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6103291 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 37789516 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.022593 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.148604 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 32152230 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 16420555 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2260 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 569005 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 568969 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 36 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 939547 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 14756064 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 15563 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 15563 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 5525670 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 13869690 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1023479 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 455350 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 356742 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 509038 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1302016 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1231079 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 9692338 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5147566 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 792720 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 788675 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 29179671 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19139148 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 387023 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1234112 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 49939954 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 623657344 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 598500446 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1429032 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4559656 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1228146478 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6651761 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 39123003 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.023394 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.151159 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 36935768 97.74% 97.74% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 853732 2.26% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 16 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 38207781 97.66% 97.66% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 915186 2.34% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 36 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 37789516 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 19757899995 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 39123003 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 20385491499 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 181829197 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 189810874 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 14614802569 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 14619906616 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7994552968 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8517245437 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 203085447 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 208413461 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 597764892 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 664225858 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 123013748 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 87245709 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5806283 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 91467062 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 66791634 # Number of BTB hits
+system.cpu1.branchPred.lookups 135994038 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 97681271 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5923294 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 101767942 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 74881085 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.022608 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 14491018 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 994593 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 73.580229 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 15572056 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 1048784 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 261280 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 261280 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8108 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 72332 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 261280 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 261280 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 261280 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 80440 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 21205.221283 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 19053.776737 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 17699.176778 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 79639 99.00% 99.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 177 0.22% 99.22% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 525 0.65% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 29 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 26 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 80440 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walks 278179 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 278179 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9856 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80934 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 278179 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 278179 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 278179 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 90790 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 21983.114880 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 19433.562361 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 21494.492882 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 89574 98.66% 98.66% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 162 0.18% 98.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 899 0.99% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 22 0.02% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 47 0.05% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 21 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 36 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 90790 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 1613488760 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 1613488760 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 1613488760 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 72332 89.92% 89.92% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 8108 10.08% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 80440 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 261280 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkPageSizes::4K 80934 89.14% 89.14% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 9856 10.86% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 90790 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 278179 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 261280 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 80440 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 278179 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90790 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 80440 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 341720 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90790 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 368969 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 79147380 # DTB read hits
-system.cpu1.dtb.read_misses 216729 # DTB read misses
-system.cpu1.dtb.write_hits 70165250 # DTB write hits
-system.cpu1.dtb.write_misses 44551 # DTB write misses
+system.cpu1.dtb.read_hits 86408994 # DTB read hits
+system.cpu1.dtb.read_misses 229031 # DTB read misses
+system.cpu1.dtb.write_hits 76265809 # DTB write hits
+system.cpu1.dtb.write_misses 49148 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 35978 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 1622 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 8536 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 36480 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 1565 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 7972 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11275 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 79364109 # DTB read accesses
-system.cpu1.dtb.write_accesses 70209801 # DTB write accesses
+system.cpu1.dtb.perms_faults 11612 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 86638025 # DTB read accesses
+system.cpu1.dtb.write_accesses 76314957 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 149312630 # DTB hits
-system.cpu1.dtb.misses 261280 # DTB misses
-system.cpu1.dtb.accesses 149573910 # DTB accesses
+system.cpu1.dtb.hits 162674803 # DTB hits
+system.cpu1.dtb.misses 278179 # DTB misses
+system.cpu1.dtb.accesses 162952982 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 64423 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 64423 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 649 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 55396 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 64423 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 64423 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 64423 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 56045 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 23900.053528 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 21358.293391 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 20280.389435 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 55251 98.58% 98.58% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 6 0.01% 98.59% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 707 1.26% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 21 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 35 0.06% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 13 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 56045 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 61280 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 61280 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 546 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 52744 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 61280 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 61280 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 61280 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 53290 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 25110.649278 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 21594.032296 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 25562.060343 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 52075 97.72% 97.72% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 7 0.01% 97.73% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1075 2.02% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 37 0.07% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 53 0.10% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.05% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 12 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 53290 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1612594260 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1612594260 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1612594260 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 55396 98.84% 98.84% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 649 1.16% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 56045 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 52744 98.98% 98.98% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 546 1.02% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 53290 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 64423 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 64423 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61280 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61280 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 56045 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 56045 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 120468 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 219650463 # ITB inst hits
-system.cpu1.itb.inst_misses 64423 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 53290 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 53290 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 114570 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 242169117 # ITB inst hits
+system.cpu1.itb.inst_misses 61280 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 38817 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 25468 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 43397 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1058 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 25722 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 193837 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 205735 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 219714886 # ITB inst accesses
-system.cpu1.itb.hits 219650463 # DTB hits
-system.cpu1.itb.misses 64423 # DTB misses
-system.cpu1.itb.accesses 219714886 # DTB accesses
-system.cpu1.numCycles 870330668 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 242230397 # ITB inst accesses
+system.cpu1.itb.hits 242169117 # DTB hits
+system.cpu1.itb.misses 61280 # DTB misses
+system.cpu1.itb.accesses 242230397 # DTB accesses
+system.cpu1.numCycles 953928196 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 404507419 # Number of instructions committed
-system.cpu1.committedOps 476442054 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 42651509 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 4585 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 94059012808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.151581 # CPI: cycles per instruction
-system.cpu1.ipc 0.464774 # IPC: instructions per cycle
+system.cpu1.committedInsts 443058406 # Number of instructions committed
+system.cpu1.committedOps 521637964 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 48259182 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 4720 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 94194636881 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.153053 # CPI: cycles per instruction
+system.cpu1.ipc 0.464457 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 15419 # number of quiesce instructions executed
-system.cpu1.tickCycles 657243105 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 213087563 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 4754677 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 457.418304 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 141978837 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 4755187 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 29.857677 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 13665 # number of quiesce instructions executed
+system.cpu1.tickCycles 720990302 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 232937894 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 5271409 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 430.049497 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 154587010 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5271921 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 29.322710 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8389845325000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.418304 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893395 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.893395 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 300818421 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 300818421 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 72673299 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 72673299 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 65442912 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 65442912 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 235828 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 235828 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 186972 # number of WriteLineReq hits
-system.cpu1.dcache.WriteLineReq_hits::total 186972 # number of WriteLineReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1517500 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1517500 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1485570 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1485570 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 138116211 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 138116211 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 138352039 # number of overall hits
-system.cpu1.dcache.overall_hits::total 138352039 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3009807 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3009807 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 2062772 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 2062772 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 570106 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 570106 # number of SoftPFReq misses
-system.cpu1.dcache.WriteLineReq_misses::cpu1.data 466745 # number of WriteLineReq misses
-system.cpu1.dcache.WriteLineReq_misses::total 466745 # number of WriteLineReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 151961 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 151961 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 182125 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 182125 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 5072579 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 5072579 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5642685 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5642685 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 47626322500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 47626322500 # number of ReadReq miss cycles
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-system.cpu1.dcache.WriteReq_miss_latency::total 41378134500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 19926390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.WriteLineReq_miss_latency::total 19926390000 # number of WriteLineReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2395499000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2395499000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4359715500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4359715500 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5890500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5890500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 89004457000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 89004457000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 89004457000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 89004457000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 75683106 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 75683106 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 67505684 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 67505684 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 805934 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 805934 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653717 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.WriteLineReq_accesses::total 653717 # number of WriteLineReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1669461 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1669461 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1667695 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1667695 # number of StoreCondReq accesses(hits+misses)
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-system.cpu1.dcache.demand_accesses::total 143188790 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 143994724 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 143994724 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039769 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.039769 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030557 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.030557 # miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.707385 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.713986 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_miss_rate::total 0.713986 # miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091024 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091024 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.109208 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.109208 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035426 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.035426 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039187 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.039187 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15823.713115 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15823.713115 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20059.480398 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 20059.480398 # average WriteReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42692.240945 # average WriteLineReq miss latency
-system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42692.240945 # average WriteLineReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15763.906529 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15763.906529 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23938.039808 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23938.039808 # average StoreCondReq miss latency
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.049497 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.occ_percent::total 0.839940 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
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+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 327906694 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 327906694 # Number of data accesses
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+system.cpu1.dcache.SoftPFReq_accesses::total 929811 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 653891 # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.WriteLineReq_accesses::total 653891 # number of WriteLineReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998565 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1998565 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1996677 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1996677 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 155690611 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 155690611 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 156620422 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 156620422 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.040625 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.040625 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.031686 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.726312 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.726312 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.694064 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.WriteLineReq_miss_rate::total 0.694064 # miss rate for WriteLineReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081593 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.081593 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099862 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099862 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.036418 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.036418 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040513 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.040513 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16510.861923 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16510.861923 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.930873 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.930873 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 45428.442057 # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 45428.442057 # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16124.493313 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16124.493313 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23503.174635 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23503.174635 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17546.194352 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17546.194352 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15773.422936 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15773.422936 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18291.324560 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18291.324560 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16344.547726 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16344.547726 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3093987 # number of writebacks
-system.cpu1.dcache.writebacks::total 3093987 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 330751 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 330751 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 852033 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 852033 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 101 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.WriteLineReq_mshr_hits::total 101 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 39295 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 39295 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 47 # number of StoreCondReq MSHR hits
-system.cpu1.dcache.StoreCondReq_mshr_hits::total 47 # number of StoreCondReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 1182784 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 1182784 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 1182784 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2679056 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 2679056 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1210739 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1210739 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 569730 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 569730 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 466644 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::total 466644 # number of WriteLineReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 112666 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 112666 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 182078 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 182078 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.demand_mshr_misses::total 3889795 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_uncacheable::total 23510 # number of ReadReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 22572 # number of WriteReq MSHR uncacheable
-system.cpu1.dcache.WriteReq_mshr_uncacheable::total 22572 # number of WriteReq MSHR uncacheable
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-system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46082 # number of overall MSHR uncacheable misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38219808000 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 19450050500 # number of WriteLineReq MSHR miss cycles
-system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 19450050500 # number of WriteLineReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1560972500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4174804000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5498500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5498500 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 62246092000 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4058237000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7996305000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035398 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035398 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017935 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017935 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.706919 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.706919 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.713832 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.713832 # mshr miss rate for WriteLineReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067486 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067486 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.109179 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.109179 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027165 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.027165 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030970 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030970 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14266.147479 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14266.147479 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19844.313267 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19844.313267 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23636.838502 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23636.838502 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41680.704134 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41680.704134 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13854.867484 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13854.867484 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22928.656949 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22928.656949 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 3447609 # number of writebacks
+system.cpu1.dcache.writebacks::total 3447609 # number of writebacks
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+system.cpu1.dcache.overall_mshr_hits::total 1343662 # number of overall MSHR hits
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 675071 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 453750 # number of WriteLineReq MSHR misses
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+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 46039 # number of overall MSHR uncacheable misses
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3997500 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036024 # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.726030 # mshr miss rate for SoftPFReq accesses
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060938 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.060938 # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099828 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027787 # mshr miss rate for demand accesses
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 136086.956522 # average overall mshr uncacheable latency
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-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29665.921682 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 60396.177826 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 60396.177826 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31362.703847 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 31695.900633 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34920.020841 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30006.524096 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32246.600645 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43272.670972 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34326.521513 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191657 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 45405.487361 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 62763.794851 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 33876.592015 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 33876.592015 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18404.479084 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18404.479084 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 3584500 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 3584500 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 47001.856084 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 47001.856084 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30210.657025 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31801.599439 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31801.599439 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 61599.092773 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 61599.092773 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33100.996437 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 43372.929309 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48350.124748 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30210.657025 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34713.726625 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 62763.794851 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40912.032789 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164615.057422 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164472.671807 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166966.440723 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166966.440723 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164418.990732 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164277.441348 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166840.276236 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 166840.276236 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 128086.956522 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165766.817846 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165691.742106 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 165603.205978 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 165528.386551 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 27994147 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 14282234 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2462 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 511124 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 511112 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 774549 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 13093104 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 22572 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 22572 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 4024053 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 12566811 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 824857 # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests 29416501 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 15028447 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 2391 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 554511 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 554502 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 9 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 803941 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 13684916 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 22517 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 22517 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 4553047 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 13043260 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 982334 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 394282 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 330789 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 437890 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1101707 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1029116 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 8864949 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4459910 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 472941 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 464971 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 26592839 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15453192 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 351687 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1018625 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 43416343 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 567362560 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 485060327 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1274328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3680592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1057377807 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5633237 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 33839951 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.023781 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.152368 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 414162 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 358438 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 473685 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 62 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1229561 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1158646 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 9020695 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4893253 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 460729 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 452056 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 27060072 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17084009 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332493 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1088108 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 45564682 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 577330304 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 542008212 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1195776 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3926416 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1124460708 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 6177589 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 35784390 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.024790 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.155485 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 33035226 97.62% 97.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 804713 2.38% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 34897315 97.52% 97.52% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 887066 2.48% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 9 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 33839951 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 17356578996 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 35784390 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 18416469994 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 182990836 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 187934075 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 13300024061 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 13533732383 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7030302930 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7841048470 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 192411968 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 183047447 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 558633834 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 597345920 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40378 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40378 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136939 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136939 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47682 # Packet count per connected master and slave (bytes)
+system.iobus.trans_dist::ReadReq 40341 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40341 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136603 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136603 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47670 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29756 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122772 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231782 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231782 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122552 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231256 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231256 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354634 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47702 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47690 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17674 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155810 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 130003.826531 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132295.327103 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123753.237907 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 127567.975992 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 151897.894870 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 136421.829164 # average overall mshr miss latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.624401 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.573317 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.598337 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.594433 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.597295 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.760978 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.452138 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.661157 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207900 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.154087 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.216232 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.300824 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.271356 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.340619 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.082342 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.465531 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.488955 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.264900 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.313962 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.073042 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.246563 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.426047 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.300824 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73580.712214 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73562.888904 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73571.998826 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76479.682642 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76568.010076 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76522.396324 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 135274.794522 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 128373.621440 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 133749.410282 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130896.398879 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 131281.027775 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 148108.950330 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130487.876254 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 130124.824356 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 124676.223818 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 134230.283373 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 162878.270449 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 131707.347447 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132210.760118 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125219.539809 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 129626.836307 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 163289.031558 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 142108.606976 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 141131.350427 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 140688.023422 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146626.786626 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126109.958690 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 139130.829350 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149965.776183 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145557.654911 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146431.271259 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 126000.342133 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 138396.453126 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 149839.721100 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 145162.946429 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112723.240743 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 140102.617332 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 139509.057851 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107070.652174 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148262.369792 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 131865.259589 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 148098.366531 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 131670.738530 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 90534 # Transaction distribution
-system.membus.trans_dist::ReadResp 722459 # Transaction distribution
-system.membus.trans_dist::WriteReq 38054 # Transaction distribution
-system.membus.trans_dist::WriteResp 38054 # Transaction distribution
-system.membus.trans_dist::Writeback 1001017 # Transaction distribution
-system.membus.trans_dist::CleanEvict 217536 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 423474 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 287804 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 114083 # Transaction distribution
+system.membus.trans_dist::ReadReq 90608 # Transaction distribution
+system.membus.trans_dist::ReadResp 1019089 # Transaction distribution
+system.membus.trans_dist::WriteReq 38080 # Transaction distribution
+system.membus.trans_dist::WriteResp 38080 # Transaction distribution
+system.membus.trans_dist::Writeback 1301925 # Transaction distribution
+system.membus.trans_dist::CleanEvict 271570 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 429176 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 310200 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 115027 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 614073 # Transaction distribution
-system.membus.trans_dist::ReadExResp 593351 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 631925 # Transaction distribution
-system.membus.trans_dist::InvalidateReq 106984 # Transaction distribution
-system.membus.trans_dist::InvalidateResp 106984 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122772 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadExReq 674063 # Transaction distribution
+system.membus.trans_dist::ReadExResp 652544 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 928481 # Transaction distribution
+system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
+system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122552 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24382 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4492959 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4640165 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 343288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4983453 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155810 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24802 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5589312 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5736718 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342877 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 342877 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6079595 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155682 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48764 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 138392448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 138598346 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7280768 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7280768 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 145879114 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 620798 # Total snoops (count)
-system.membus.snoop_fanout::samples 3413791 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49604 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 180435584 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 180642194 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7274816 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7274816 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 187917010 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 648574 # Total snoops (count)
+system.membus.snoop_fanout::samples 4152999 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3413791 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4152999 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3413791 # Request fanout histogram
-system.membus.reqLayer0.occupancy 110035999 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 4152999 # Request fanout histogram
+system.membus.reqLayer0.occupancy 109607499 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33984 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20235499 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20503498 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7135371847 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9125026082 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 7009823140 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 8873044520 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 230763823 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 230408874 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
+system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 11297780 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 5747695 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2144395 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 127398 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 116260 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 11138 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 90536 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4706613 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38054 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38054 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 3214229 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 1520051 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 472952 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 299595 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 772547 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1095800 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1095800 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4623306 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 106984 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8277775 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6810974 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15088749 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 253701939 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 194091607 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 447793546 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2987756 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 12830892 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.357421 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.481048 # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests 12411375 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 6308416 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2241470 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 182770 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 168316 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 14454 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 90610 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 5207811 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38080 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38080 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 3858986 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 1729776 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 481704 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 322377 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 804081 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 116 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 116 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1151274 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1151274 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 5124442 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9065091 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7602046 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 16667137 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 281816078 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 221579908 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 503395986 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3440017 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 14338060 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.337750 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.475069 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 8255998 64.34% 64.34% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 4563756 35.57% 99.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 11138 0.09% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 9509841 66.33% 66.33% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 4813765 33.57% 99.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 14454 0.10% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 12830892 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8297238000 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 14338060 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9248164097 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2658855 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2627637 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4939762812 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 5363594791 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4158976314 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4586237114 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000024] Console: colour dummy device 80x25\r
-[ 0.000026] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000028] pid_max: default: 32768 minimum: 301\r
-[ 0.000040] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000041] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000175] hw perfevents: no hardware support available\r
-[ 0.060045] CPU1: Booted secondary processor\r
-[ 1.080077] CPU2: failed to come online\r
-[ 2.100147] CPU3: failed to come online\r
-[ 2.100150] Brought up 2 CPUs\r
-[ 2.100151] SMP: Total of 2 processors activated.\r
-[ 2.100223] devtmpfs: initialized\r
-[ 2.100724] atomic64_test: passed\r
-[ 2.100770] regulator-dummy: no parameters\r
-[ 2.101122] NET: Registered protocol family 16\r
-[ 2.101258] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101266] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.102220] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.102224] Serial: AMBA PL011 UART driver\r
-[ 2.102423] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.102463] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.103011] console [ttyAMA0] enabled\r
-[ 2.103164] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.103228] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.103292] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.103348] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.140302] 3V3: 3300 mV \r
-[ 2.140352] vgaarb: loaded\r
-[ 2.140397] SCSI subsystem initialized\r
-[ 2.140431] libata version 3.00 loaded.\r
-[ 2.140480] usbcore: registered new interface driver usbfs\r
-[ 2.140498] usbcore: registered new interface driver hub\r
-[ 2.140524] usbcore: registered new device driver usb\r
-[ 2.140552] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.140560] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.140580] PTP clock support registered\r
-[ 2.140713] Switched to clocksource arch_sys_counter\r
-[ 2.142154] NET: Registered protocol family 2\r
-[ 2.142231] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.142248] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.142265] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.142293] TCP: reno registered\r
-[ 2.142300] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142311] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.142346] NET: Registered protocol family 1\r
-[ 2.142411] RPC: Registered named UNIX socket transport module.\r
-[ 2.142421] RPC: Registered udp transport module.\r
-[ 2.142429] RPC: Registered tcp transport module.\r
-[ 2.142437] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.142449] PCI: CLS 0 bytes, default 64\r
-[ 2.142611] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.142705] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.144323] fuse init (API version 7.23)\r
-[ 2.144408] msgmni has been set to 469\r
-[ 2.144748] io scheduler noop registered\r
-[ 2.144801] io scheduler cfq registered (default)\r
-[ 2.145278] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.145291] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.145302] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.145314] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.145324] pci_bus 0000:00: scanning bus\r
-[ 2.145335] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.145348] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.145362] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145397] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.145408] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.145419] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.145429] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.145440] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.145450] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.145461] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.145494] pci_bus 0000:00: fixups for bus\r
-[ 2.145502] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.145513] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.145533] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.145541] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.145551] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.145559] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.145571] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.145583] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.145596] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.145608] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.145619] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.145631] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.145642] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.145653] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.146115] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.146366] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.146376] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.146403] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.146653] scsi0 : ata_piix\r
-[ 2.146726] scsi1 : ata_piix\r
-[ 2.146757] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.146769] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.146877] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.146889] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.146903] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.146914] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.300739] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.300748] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.300776] ata1.00: configured for UDMA/33\r
-[ 2.300832] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.300940] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.300943] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.300970] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.300979] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.301004] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.301128] sda: sda1\r
-[ 2.301242] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.421010] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.421023] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.421045] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.421055] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.421075] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.421087] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.421158] usbcore: registered new interface driver usb-storage\r
-[ 2.421211] mousedev: PS/2 mouse device common for all mice\r
-[ 2.421360] usbcore: registered new interface driver usbhid\r
-[ 2.421370] usbhid: USB HID core driver\r
-[ 2.421405] TCP: cubic registered\r
-[ 2.421412] NET: Registered protocol family 17\r
-\0[ 2.421752] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.421788] devtmpfs: mounted\r
-[ 2.421844] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000029] Console: colour dummy device 80x25\r
+[ 0.000032] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000034] pid_max: default: 32768 minimum: 301\r
+[ 0.000048] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000049] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000222] hw perfevents: no hardware support available\r
+[ 0.060054] CPU1: Booted secondary processor\r
+[ 1.080084] CPU2: failed to come online\r
+[ 2.100160] CPU3: failed to come online\r
+[ 2.100163] Brought up 2 CPUs\r
+[ 2.100164] SMP: Total of 2 processors activated.\r
+[ 2.100234] devtmpfs: initialized\r
+[ 2.100752] atomic64_test: passed\r
+[ 2.100807] regulator-dummy: no parameters\r
+[ 2.101177] NET: Registered protocol family 16\r
+[ 2.101322] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101331] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.102702] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.102707] Serial: AMBA PL011 UART driver\r
+[ 2.102925] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.102969] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.103518] console [ttyAMA0] enabled\r
+[ 2.103667] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.103726] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.103785] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.103844] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140336] 3V3: 3300 mV \r
+[ 2.140385] vgaarb: loaded\r
+[ 2.140432] SCSI subsystem initialized\r
+[ 2.140469] libata version 3.00 loaded.\r
+[ 2.140531] usbcore: registered new interface driver usbfs\r
+[ 2.140549] usbcore: registered new interface driver hub\r
+[ 2.140572] usbcore: registered new device driver usb\r
+[ 2.140598] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140607] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140626] PTP clock support registered\r
+[ 2.140770] Switched to clocksource arch_sys_counter\r
+[ 2.141801] NET: Registered protocol family 2\r
+[ 2.141884] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.141900] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.141917] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.141953] TCP: reno registered\r
+[ 2.141960] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141972] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.142009] NET: Registered protocol family 1\r
+[ 2.142063] RPC: Registered named UNIX socket transport module.\r
+[ 2.142073] RPC: Registered udp transport module.\r
+[ 2.142081] RPC: Registered tcp transport module.\r
+[ 2.142089] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.142102] PCI: CLS 0 bytes, default 64\r
+[ 2.142263] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.142361] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.144514] fuse init (API version 7.23)\r
+[ 2.144633] msgmni has been set to 469\r
+[ 2.144742] io scheduler noop registered\r
+[ 2.144793] io scheduler cfq registered (default)\r
+[ 2.145358] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.145371] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.145382] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.145394] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.145404] pci_bus 0000:00: scanning bus\r
+[ 2.145415] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.145428] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.145442] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.145479] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.145491] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.145501] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.145512] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.145522] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.145532] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.145543] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.145578] pci_bus 0000:00: fixups for bus\r
+[ 2.145586] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.145598] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.145619] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.145627] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.145637] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.145646] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.145659] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.145672] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.145684] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.145697] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.145708] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.145719] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.145730] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.145741] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.146409] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.146689] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.146700] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.146732] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.147004] scsi0 : ata_piix\r
+[ 2.147088] scsi1 : ata_piix\r
+[ 2.147119] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.147131] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.147235] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.147247] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.147261] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.147273] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290813] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290823] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290852] ata1.00: configured for UDMA/33\r
+[ 2.290919] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.291040] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.291042] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.291098] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.291108] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.291128] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.291290] sda: sda1\r
+[ 2.291413] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.411076] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.411089] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.411111] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.411121] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.411141] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.411152] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.411222] usbcore: registered new interface driver usb-storage\r
+[ 2.411292] mousedev: PS/2 mouse device common for all mice\r
+[ 2.411462] usbcore: registered new interface driver usbhid\r
+[ 2.411472] usbhid: USB HID core driver\r
+[ 2.411505] TCP: cubic registered\r
+[ 2.411513] NET: Registered protocol family 17\r
+\0[ 2.411944] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411993] devtmpfs: mounted\r
+[ 2.412066] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.460208] udevd[609]: starting version 182\r
+[ 2.450550] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.523360] random: dd urandom read with 17 bits of entropy available\r
+[ 2.553587] random: dd urandom read with 18 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.650938] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.681002] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
rpcbind: cannot get uid of '': Success\r\r\r
creating NFS state directory: done\r\r
starting statd: done\r\r
-Starting auto-serial-console: done\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 14 2015 23:30:17
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 02:08:50
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-minor
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51694125219000 because m5_exit instruction encountered
+Exiting @ tick 51667489826000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 51.667585 # Number of seconds simulated
-sim_ticks 51667585479000 # Number of ticks simulated
-final_tick 51667585479000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.667490 # Number of seconds simulated
+sim_ticks 51667489826000 # Number of ticks simulated
+final_tick 51667489826000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 173260 # Simulator instruction rate (inst/s)
-host_op_rate 203581 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9711995066 # Simulator tick rate (ticks/s)
-host_mem_usage 728604 # Number of bytes of host memory used
-host_seconds 5319.98 # Real time elapsed on the host
-sim_insts 921741550 # Number of instructions simulated
-sim_ops 1083047600 # Number of ops (including micro ops) simulated
+host_inst_rate 98445 # Simulator instruction rate (inst/s)
+host_op_rate 115675 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5518412939 # Simulator tick rate (ticks/s)
+host_mem_usage 676348 # Number of bytes of host memory used
+host_seconds 9362.74 # Real time elapsed on the host
+sim_insts 921716010 # Number of instructions simulated
+sim_ops 1083032845 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 358592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 308608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10084224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 94130760 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 400576 # Number of bytes read from this memory
-system.physmem.bytes_read::total 105282760 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 10084224 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 10084224 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 87776448 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 356224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 294592 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 10211648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 93641864 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 394368 # Number of bytes read from this memory
+system.physmem.bytes_read::total 104898696 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 10211648 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 10211648 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 87439552 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 87797028 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 5603 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 4822 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 157566 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1470806 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6259 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1645056 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1371507 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 87460132 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 5566 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 4603 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 159557 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1463167 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6162 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1639055 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1366243 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1374080 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 6940 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 5973 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 195175 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1821853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7753 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2037695 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 195175 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 195175 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1698869 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1368816 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 6895 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 5702 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 197642 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1812394 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 7633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2030265 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 197642 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 197642 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1692351 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1699267 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1698869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 6940 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 5973 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 195175 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1822252 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7753 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3736962 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1645056 # Number of read requests accepted
-system.physmem.writeReqs 1374080 # Number of write requests accepted
-system.physmem.readBursts 1645056 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1374080 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 105226304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 57280 # Total number of bytes read from write queue
-system.physmem.bytesWritten 87795840 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 105282760 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 87797028 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 895 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1692750 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1692351 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 6895 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 5702 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 197642 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1812793 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 7633 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 3723015 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1639055 # Number of read requests accepted
+system.physmem.writeReqs 1368816 # Number of write requests accepted
+system.physmem.readBursts 1639055 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1368816 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 104838592 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 60928 # Total number of bytes read from write queue
+system.physmem.bytesWritten 87458560 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 104898696 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 87460132 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 952 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 144878 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 98762 # Per bank write bursts
-system.physmem.perBankRdBursts::1 104908 # Per bank write bursts
-system.physmem.perBankRdBursts::2 100268 # Per bank write bursts
-system.physmem.perBankRdBursts::3 95741 # Per bank write bursts
-system.physmem.perBankRdBursts::4 100817 # Per bank write bursts
-system.physmem.perBankRdBursts::5 109226 # Per bank write bursts
-system.physmem.perBankRdBursts::6 96584 # Per bank write bursts
-system.physmem.perBankRdBursts::7 96517 # Per bank write bursts
-system.physmem.perBankRdBursts::8 93312 # Per bank write bursts
-system.physmem.perBankRdBursts::9 154793 # Per bank write bursts
-system.physmem.perBankRdBursts::10 99831 # Per bank write bursts
-system.physmem.perBankRdBursts::11 102735 # Per bank write bursts
-system.physmem.perBankRdBursts::12 98206 # Per bank write bursts
-system.physmem.perBankRdBursts::13 101977 # Per bank write bursts
-system.physmem.perBankRdBursts::14 93251 # Per bank write bursts
-system.physmem.perBankRdBursts::15 97233 # Per bank write bursts
-system.physmem.perBankWrBursts::0 83938 # Per bank write bursts
-system.physmem.perBankWrBursts::1 86643 # Per bank write bursts
-system.physmem.perBankWrBursts::2 85449 # Per bank write bursts
-system.physmem.perBankWrBursts::3 83391 # Per bank write bursts
-system.physmem.perBankWrBursts::4 87884 # Per bank write bursts
-system.physmem.perBankWrBursts::5 92979 # Per bank write bursts
-system.physmem.perBankWrBursts::6 83797 # Per bank write bursts
-system.physmem.perBankWrBursts::7 84591 # Per bank write bursts
-system.physmem.perBankWrBursts::8 82134 # Per bank write bursts
-system.physmem.perBankWrBursts::9 88444 # Per bank write bursts
-system.physmem.perBankWrBursts::10 84764 # Per bank write bursts
-system.physmem.perBankWrBursts::11 87315 # Per bank write bursts
-system.physmem.perBankWrBursts::12 85408 # Per bank write bursts
-system.physmem.perBankWrBursts::13 87944 # Per bank write bursts
-system.physmem.perBankWrBursts::14 81647 # Per bank write bursts
-system.physmem.perBankWrBursts::15 85482 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 145140 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 96907 # Per bank write bursts
+system.physmem.perBankRdBursts::1 103074 # Per bank write bursts
+system.physmem.perBankRdBursts::2 99514 # Per bank write bursts
+system.physmem.perBankRdBursts::3 96513 # Per bank write bursts
+system.physmem.perBankRdBursts::4 97689 # Per bank write bursts
+system.physmem.perBankRdBursts::5 108359 # Per bank write bursts
+system.physmem.perBankRdBursts::6 97886 # Per bank write bursts
+system.physmem.perBankRdBursts::7 97902 # Per bank write bursts
+system.physmem.perBankRdBursts::8 96810 # Per bank write bursts
+system.physmem.perBankRdBursts::9 157961 # Per bank write bursts
+system.physmem.perBankRdBursts::10 100161 # Per bank write bursts
+system.physmem.perBankRdBursts::11 104541 # Per bank write bursts
+system.physmem.perBankRdBursts::12 94779 # Per bank write bursts
+system.physmem.perBankRdBursts::13 97199 # Per bank write bursts
+system.physmem.perBankRdBursts::14 94176 # Per bank write bursts
+system.physmem.perBankRdBursts::15 94632 # Per bank write bursts
+system.physmem.perBankWrBursts::0 82268 # Per bank write bursts
+system.physmem.perBankWrBursts::1 85491 # Per bank write bursts
+system.physmem.perBankWrBursts::2 84713 # Per bank write bursts
+system.physmem.perBankWrBursts::3 83877 # Per bank write bursts
+system.physmem.perBankWrBursts::4 85039 # Per bank write bursts
+system.physmem.perBankWrBursts::5 91961 # Per bank write bursts
+system.physmem.perBankWrBursts::6 84027 # Per bank write bursts
+system.physmem.perBankWrBursts::7 85348 # Per bank write bursts
+system.physmem.perBankWrBursts::8 84923 # Per bank write bursts
+system.physmem.perBankWrBursts::9 91534 # Per bank write bursts
+system.physmem.perBankWrBursts::10 85936 # Per bank write bursts
+system.physmem.perBankWrBursts::11 89456 # Per bank write bursts
+system.physmem.perBankWrBursts::12 82822 # Per bank write bursts
+system.physmem.perBankWrBursts::13 84269 # Per bank write bursts
+system.physmem.perBankWrBursts::14 82271 # Per bank write bursts
+system.physmem.perBankWrBursts::15 82605 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
-system.physmem.totGap 51667583532000 # Total gap between requests
+system.physmem.numWrRetry 26 # Number of times write queue was full causing retry
+system.physmem.totGap 51667488071000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1645041 # Read request sizes (log2)
+system.physmem.readPktSize::6 1639040 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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-system.physmem.rdPerTurnAround::mean 20.651179 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::samples 79614 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.230763 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.794029 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 6.276538 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 77327 97.13% 97.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 304 0.38% 97.51% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::28-31 307 0.39% 97.96% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::36-39 338 0.42% 98.46% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::52-55 131 0.16% 99.01% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::72-75 21 0.03% 99.77% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::80-83 7 0.01% 99.93% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::116-119 2 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 79614 # Writes before turning the bus around for reads
-system.physmem.totQLat 26413369588 # Total ticks spent queuing
-system.physmem.totMemAccLat 57241388338 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 8220805000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 16064.95 # Average queueing delay per DRAM burst
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+system.physmem.totQLat 26536419219 # Total ticks spent queuing
+system.physmem.totMemAccLat 57250850469 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 8190515000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 16199.48 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34814.95 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.04 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.70 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.04 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.70 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 34949.48 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.46 # Average write queue length when enqueuing
-system.physmem.readRowHits 1338705 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1030897 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.42 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.15 # Row buffer hit rate for writes
-system.physmem.avgGap 17113367.38 # Average gap between requests
-system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2462533920 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1343644500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 6262011600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4462594560 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1320469447905 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29842244670000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34551920396805 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.734956 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49644314314893 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1725294220000 # Time in different power states
+system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing
+system.physmem.readRowHits 1330988 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1025273 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes
+system.physmem.avgGap 17177428.18 # Average gap between requests
+system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2459736720 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1342118250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 6223136400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4424051520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1319911106400 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29842673702250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34551702734580 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.732053 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49645039210452 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1725290840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 297976817607 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 297159003548 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2424008160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1322623500 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 6562436400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4426734240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3374675494320 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1320896835045 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29841869760750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34552177892415 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.739940 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49643648149046 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1725294220000 # Time in different power states
+system.physmem_1.actEnergy 2442023640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1332453375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 6554020200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4431127680 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1320412056885 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29842234272000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34552074836820 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.739255 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49644231851772 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1725290840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 298642969704 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 297961425728 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 252423071 # Number of BP lookups
-system.cpu.branchPred.condPredicted 176427079 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 11938474 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 185221577 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 131501265 # Number of BTB hits
+system.cpu.branchPred.lookups 252436095 # Number of BP lookups
+system.cpu.branchPred.condPredicted 176405196 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 11951074 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 185535740 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 131467669 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 70.996731 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 30906734 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 2133609 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 70.858407 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 30937069 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 2133020 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 560833 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 560833 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21083 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178899 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 560833 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 560833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 560833 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 199982 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 27029.240132 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 22851.547546 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 20760.636291 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 197624 98.82% 98.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 5 0.00% 98.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2039 1.02% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 109 0.05% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 52 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 79 0.04% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 560363 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 560363 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20601 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178609 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 560363 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 560363 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 560363 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 199210 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 27145.243713 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 23005.972162 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20907.221064 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 196938 98.86% 98.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 98.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 1933 0.97% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 58 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 84 0.04% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 199982 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 199210 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 178900 89.46% 89.46% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 21083 10.54% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 199983 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560833 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 178610 89.66% 89.66% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 20601 10.34% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 199211 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560363 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560833 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199983 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560363 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199211 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199983 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 760816 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199211 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 759574 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 178232351 # DTB read hits
-system.cpu.dtb.read_misses 463077 # DTB read misses
-system.cpu.dtb.write_hits 157845440 # DTB write hits
-system.cpu.dtb.write_misses 97756 # DTB write misses
+system.cpu.dtb.read_hits 178192284 # DTB read hits
+system.cpu.dtb.read_misses 462603 # DTB read misses
+system.cpu.dtb.write_hits 157870024 # DTB write hits
+system.cpu.dtb.write_misses 97760 # DTB write misses
system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 77809 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1378 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 14628 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 78455 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 14585 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 23069 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 178695428 # DTB read accesses
-system.cpu.dtb.write_accesses 157943196 # DTB write accesses
+system.cpu.dtb.perms_faults 23059 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 178654887 # DTB read accesses
+system.cpu.dtb.write_accesses 157967784 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 336077791 # DTB hits
-system.cpu.dtb.misses 560833 # DTB misses
-system.cpu.dtb.accesses 336638624 # DTB accesses
+system.cpu.dtb.hits 336062308 # DTB hits
+system.cpu.dtb.misses 560363 # DTB misses
+system.cpu.dtb.accesses 336622671 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 134950 # Table walker walks requested
-system.cpu.itb.walker.walksLong 134950 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1074 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 117621 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 134950 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 134950 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 134950 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 118695 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 30170.011374 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 25640.228509 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 23413.242871 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 115997 97.73% 97.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 4 0.00% 97.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 2500 2.11% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 50 0.04% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 104 0.09% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 27 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 8 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 118695 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 134893 # Table walker walks requested
+system.cpu.itb.walker.walksLong 134893 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1070 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 117642 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 134893 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 134893 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 134893 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 118712 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 30207.312656 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 25802.029077 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 23121.543530 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 116190 97.88% 97.88% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 6 0.01% 97.88% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 2295 1.93% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 67 0.06% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 109 0.09% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 118712 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 117621 99.10% 99.10% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1074 0.90% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 118695 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 117642 99.10% 99.10% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1070 0.90% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 118712 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134950 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 134950 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134893 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 134893 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118695 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 118695 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 253645 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 438786222 # ITB inst hits
-system.cpu.itb.inst_misses 134950 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118712 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 118712 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 253605 # Table walker requests started/completed, data/inst
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system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 45304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 55568 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 56501 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 357024 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 359579 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
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-system.cpu.itb.hits 438786222 # DTB hits
-system.cpu.itb.misses 134950 # DTB misses
-system.cpu.itb.accesses 438921172 # DTB accesses
-system.cpu.numCycles 2561969113 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 438923253 # ITB inst accesses
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+system.cpu.itb.accesses 438923253 # DTB accesses
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 921741550 # Number of instructions committed
-system.cpu.committedOps 1083047600 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 92851518 # Number of ops (including micro ops) which were discarded before commit
-system.cpu.numFetchSuspends 7622 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 100774422273 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.779487 # CPI: cycles per instruction
-system.cpu.ipc 0.359779 # IPC: instructions per cycle
+system.cpu.committedInsts 921716010 # Number of instructions committed
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+system.cpu.numFetchSuspends 7624 # Number of times Execute suspended instruction fetching
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+system.cpu.cpi 2.778301 # CPI: cycles per instruction
+system.cpu.ipc 0.359932 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 19360 # number of quiesce instructions executed
-system.cpu.tickCycles 1740348403 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 821620710 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 10715341 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.930095 # Cycle average of tags in use
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-system.cpu.dcache.tags.avg_refs 29.885325 # Average number of references to valid blocks.
+system.cpu.kern.inst.quiesce 16484 # number of quiesce instructions executed
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+system.cpu.dcache.tags.tagsinuse 511.930101 # Cycle average of tags in use
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+system.cpu.dcache.tags.avg_refs 29.874749 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.930095 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 1345291071 # Number of data accesses
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-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074036 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 18472.958307 # average ReadReq miss latency
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-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16652.016964 # average LoadLockedReq miss latency
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-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 8224375 # number of writebacks
-system.cpu.dcache.writebacks::total 8224375 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 782628 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable
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system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 96186724500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26816989500 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3465009000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 229759036500 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5830985000 # number of ReadReq MSHR uncacheable cycles
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-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5820481500 # number of WriteReq MSHR uncacheable cycles
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-system.cpu.dcache.overall_mshr_uncacheable_latency::total 11651466500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032789 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032789 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015241 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728128 # mshr miss rate for SoftPFReq accesses
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+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::total 0.028686 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17224.207129 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17224.207129 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46228.053595 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46228.053595 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19249.963570 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19249.963570 # average SoftPFReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 66861.630465 # average WriteLineReq mshr miss latency
-system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 66861.630465 # average WriteLineReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14537.360710 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14537.360710 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81750 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81750 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25709.333291 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 25709.333291 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24740.377475 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24740.377475 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173041.665430 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173041.665430 # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172683.839672 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172683.839672 # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172862.728662 # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172862.728662 # average overall mshr uncacheable latency
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+system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67170.593050 # average WriteLineReq mshr miss latency
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+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14444.583829 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172865.006009 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.tags.replacements 24143027 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.872432 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 414273354 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 24143539 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 17.158767 # Average number of references to valid blocks.
+system.cpu.icache.tags.replacements 24130706 # number of replacements
+system.cpu.icache.tags.tagsinuse 511.872431 # Cycle average of tags in use
+system.cpu.icache.tags.total_refs 414285199 # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs 24131218 # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs 17.168019 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.872432 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 115 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 462560451 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 462560451 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 414273354 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 414273354 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 414273354 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 24143549 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 24143549 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 24143549 # number of overall misses
-system.cpu.icache.overall_misses::total 24143549 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 326781938000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 326781938000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 326781938000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 326781938000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 326781938000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 326781938000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 438416903 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 438416903 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 438416903 # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098496 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.030183 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126825.941587 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.789692 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.789692 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122757.794444 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122757.794444 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122275.211142 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122275.211142 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124960.043991 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124960.043991 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128749.529981 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128749.529981 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160539.795828 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131918.017348 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161165.296980 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161165.296980 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160545.953646 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131920.429970 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161163.783896 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161163.783896 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160852.588164 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140152.854350 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160854.910019 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140154.161655 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 70464557 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 35605124 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4387 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2275 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2275 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 70442734 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 35592438 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2280 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1730195 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 33090138 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1728553 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 33080077 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 9595897 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 26867205 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 47929 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 47931 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 2261624 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 2261624 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 24143549 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 7224490 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1345329 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1238665 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72531044 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32377896 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 689100 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2164239 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 107762279 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548534656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133143634 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2287216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7385984 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2691351490 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 2160503 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 73254310 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.009691 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.097963 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::Writeback 9596069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 26854364 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 48128 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 48129 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 2260770 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 2260770 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 24131228 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 7228389 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1345463 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1238799 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72494093 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32387839 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 691084 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2167479 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 107740495 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1547746112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133685906 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2304392 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7423736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 2691160146 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 2148445 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 73231054 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.009642 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.097721 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 72544433 99.03% 99.03% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 709877 0.97% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 72524927 99.04% 99.04% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 706127 0.96% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 73254310 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 44006051993 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 73231054 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 44001619997 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1484899 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1484887 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 36299896753 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 36281501081 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 14910158065 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 14914900069 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 403245904 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 403060948 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1241004972 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1239526970 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40332 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40332 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40325 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40325 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231022 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231022 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353806 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334520 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334520 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492440 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 565934074 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 565802629 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147782000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115493 # number of replacements
-system.iocache.tags.tagsinuse 10.440039 # Cycle average of tags in use
+system.iocache.tags.replacements 115486 # number of replacements
+system.iocache.tags.tagsinuse 10.440024 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13160095445000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.520833 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.919206 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.220052 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.432450 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.652502 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13160095292000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.919182 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039956 # Number of tag accesses
-system.iocache.tags.data_accesses 1039956 # Number of data accesses
+system.iocache.tags.tag_accesses 1039893 # Number of tag accesses
+system.iocache.tags.data_accesses 1039893 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8847 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8884 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8847 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8887 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8880 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8847 # number of overall misses
-system.iocache.overall_misses::total 8887 # number of overall misses
+system.iocache.overall_misses::realview.ide 8840 # number of overall misses
+system.iocache.overall_misses::total 8880 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1639357105 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1644426105 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1641330150 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1646399150 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 13823164969 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 13823164969 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 13825092479 # number of WriteLineReq miss cycles
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system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
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system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 185300.904826 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 185099.741670 # average ReadReq miss latency
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system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129595.411470 # average WriteLineReq miss latency
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system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 185076.753123 # average overall miss latency
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system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 185300.904826 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 185076.753123 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 32638 # number of cycles access was blocked
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+system.iocache.blocked_cycles::no_mshrs 32333 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3399 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3346 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 9.602236 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.663180 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::realview.ide 8847 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 8884 # number of ReadReq MSHR misses
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system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 8847 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 8887 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 8847 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 8887 # number of overall MSHR misses
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+system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1197007105 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1200226105 # number of ReadReq MSHR miss cycles
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system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8489964969 # number of WriteLineReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 1197007105 # number of demand (read+write) MSHR miss cycles
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system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 1197007105 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 1200427105 # number of overall MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 1202750150 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135300.904826 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 135099.741670 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135670.831448 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 135467.967782 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79595.411470 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79595.411470 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79613.482328 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79613.482328 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 135300.904826 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 135076.753123 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 86006 # Transaction distribution
-system.membus.trans_dist::ReadResp 529580 # Transaction distribution
+system.membus.trans_dist::ReadResp 526484 # Transaction distribution
system.membus.trans_dist::WriteReq 33706 # Transaction distribution
system.membus.trans_dist::WriteResp 33706 # Transaction distribution
-system.membus.trans_dist::Writeback 1371507 # Transaction distribution
-system.membus.trans_dist::CleanEvict 234789 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 38219 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 38221 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1152452 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1152452 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 443574 # Transaction distribution
+system.membus.trans_dist::Writeback 1366243 # Transaction distribution
+system.membus.trans_dist::CleanEvict 236394 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 38482 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 38483 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1149637 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1149637 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 440478 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4853436 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4983088 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341164 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 341164 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5324252 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4838609 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4968261 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340944 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 340944 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 5309205 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185854828 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186025234 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7224960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7224960 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 193250194 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3290 # Total snoops (count)
-system.membus.snoop_fanout::samples 3469738 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185140076 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185310482 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 192529234 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 3380 # Total snoops (count)
+system.membus.snoop_fanout::samples 3460550 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3469738 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3460550 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3469738 # Request fanout histogram
-system.membus.reqLayer0.occupancy 102307500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3460550 # Request fanout histogram
+system.membus.reqLayer0.occupancy 102447500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5483000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5490500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9286465077 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9255992894 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 8797329089 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 8767241103 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 228468079 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 228448107 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000027] Console: colour dummy device 80x25\r
-[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000032] pid_max: default: 32768 minimum: 301\r
-[ 0.000046] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000194] hw perfevents: no hardware support available\r
-[ 1.060094] CPU1: failed to come online\r
-[ 2.080184] CPU2: failed to come online\r
-[ 3.100274] CPU3: failed to come online\r
-[ 3.100278] Brought up 1 CPUs\r
-[ 3.100279] SMP: Total of 1 processors activated.\r
-[ 3.100351] devtmpfs: initialized\r
-[ 3.100988] atomic64_test: passed\r
-[ 3.101045] regulator-dummy: no parameters\r
-[ 3.101555] NET: Registered protocol family 16\r
-[ 3.101725] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101735] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.102530] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.102535] Serial: AMBA PL011 UART driver\r
-[ 3.102787] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.102834] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.103371] console [ttyAMA0] enabled\r
-[ 3.103467] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.103504] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.103541] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.103575] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130690] 3V3: 3300 mV \r
-[ 3.130745] vgaarb: loaded\r
-[ 3.130802] SCSI subsystem initialized\r
-[ 3.130853] libata version 3.00 loaded.\r
-[ 3.130911] usbcore: registered new interface driver usbfs\r
-[ 3.130932] usbcore: registered new interface driver hub\r
-[ 3.130973] usbcore: registered new device driver usb\r
-[ 3.131004] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131013] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131032] PTP clock support registered\r
-[ 3.131182] Switched to clocksource arch_sys_counter\r
-[ 3.132629] NET: Registered protocol family 2\r
-[ 3.132726] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.132747] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.132772] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.132789] TCP: reno registered\r
-[ 3.132796] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132810] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.132857] NET: Registered protocol family 1\r
-[ 3.132907] RPC: Registered named UNIX socket transport module.\r
-[ 3.132917] RPC: Registered udp transport module.\r
-[ 3.132925] RPC: Registered tcp transport module.\r
-[ 3.132933] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132945] PCI: CLS 0 bytes, default 64\r
-[ 3.133143] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.133288] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.135480] fuse init (API version 7.23)\r
-[ 3.135589] msgmni has been set to 469\r
-[ 3.138660] io scheduler noop registered\r
-[ 3.138727] io scheduler cfq registered (default)\r
-[ 3.139287] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.139300] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.139312] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.139324] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.139334] pci_bus 0000:00: scanning bus\r
-[ 3.139345] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.139358] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.139373] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139417] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.139429] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.139440] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.139451] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.139461] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.139472] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.139484] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.139525] pci_bus 0000:00: fixups for bus\r
-[ 3.139534] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.139546] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.139566] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.139575] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.139586] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.139595] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.139607] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.139620] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.139633] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.139646] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.139657] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.139669] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.139680] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.139692] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.140333] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.140661] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.140672] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.140699] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.141055] scsi0 : ata_piix\r
-[ 3.141441] scsi1 : ata_piix\r
-[ 3.141477] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.141489] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.141617] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.141629] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.141645] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.141657] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301211] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301221] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301251] ata1.00: configured for UDMA/33\r
-[ 3.301307] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.301444] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.301474] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.301521] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.301530] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.301554] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.301704] sda: sda1\r
-[ 3.301852] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.421498] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.421511] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.421534] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.421544] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.421567] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.421579] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.421664] usbcore: registered new interface driver usb-storage\r
-[ 3.421730] mousedev: PS/2 mouse device common for all mice\r
-[ 3.421920] usbcore: registered new interface driver usbhid\r
-[ 3.421930] usbhid: USB HID core driver\r
-[ 3.421965] TCP: cubic registered\r
-[ 3.421973] NET: Registered protocol family 17\r
-\0[ 3.422392] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.422431] devtmpfs: mounted\r
-[ 3.422482] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000032] Console: colour dummy device 80x25\r
+[ 0.000035] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000037] pid_max: default: 32768 minimum: 301\r
+[ 0.000053] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000055] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000248] hw perfevents: no hardware support available\r
+[ 1.060096] CPU1: failed to come online\r
+[ 2.080186] CPU2: failed to come online\r
+[ 3.100276] CPU3: failed to come online\r
+[ 3.100279] Brought up 1 CPUs\r
+[ 3.100281] SMP: Total of 1 processors activated.\r
+[ 3.100367] devtmpfs: initialized\r
+[ 3.101025] atomic64_test: passed\r
+[ 3.101090] regulator-dummy: no parameters\r
+[ 3.101671] NET: Registered protocol family 16\r
+[ 3.101853] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101864] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.103085] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.103093] Serial: AMBA PL011 UART driver\r
+[ 3.103374] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.103426] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.103965] console [ttyAMA0] enabled\r
+[ 3.104081] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.104118] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.104154] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.104188] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130720] 3V3: 3300 mV \r
+[ 3.130781] vgaarb: loaded\r
+[ 3.130844] SCSI subsystem initialized\r
+[ 3.130897] libata version 3.00 loaded.\r
+[ 3.130958] usbcore: registered new interface driver usbfs\r
+[ 3.130980] usbcore: registered new interface driver hub\r
+[ 3.131022] usbcore: registered new device driver usb\r
+[ 3.131055] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.131064] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.131084] PTP clock support registered\r
+[ 3.131249] Switched to clocksource arch_sys_counter\r
+[ 3.132739] NET: Registered protocol family 2\r
+[ 3.132848] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.132873] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.132904] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.132922] TCP: reno registered\r
+[ 3.132929] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132945] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.133000] NET: Registered protocol family 1\r
+[ 3.133055] RPC: Registered named UNIX socket transport module.\r
+[ 3.133065] RPC: Registered udp transport module.\r
+[ 3.133073] RPC: Registered tcp transport module.\r
+[ 3.133081] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.133094] PCI: CLS 0 bytes, default 64\r
+[ 3.133303] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.133472] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.135729] fuse init (API version 7.23)\r
+[ 3.135841] msgmni has been set to 469\r
+[ 3.139054] io scheduler noop registered\r
+[ 3.139123] io scheduler cfq registered (default)\r
+[ 3.139783] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.139796] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.139807] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.139820] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.139830] pci_bus 0000:00: scanning bus\r
+[ 3.139842] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.139855] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.139870] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.139918] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.139930] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.139941] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.139952] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.139963] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.139973] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.139985] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.140027] pci_bus 0000:00: fixups for bus\r
+[ 3.140036] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.140049] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.140072] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.140081] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.140092] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.140100] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.140113] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.140127] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.140140] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.140152] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.140164] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.140176] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.140187] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.140199] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.140865] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.141215] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.141227] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.141276] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.141913] scsi0 : ata_piix\r
+[ 3.142046] scsi1 : ata_piix\r
+[ 3.142082] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.142094] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.142229] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.142241] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.142257] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.142269] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.301283] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.301293] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.301323] ata1.00: configured for UDMA/33\r
+[ 3.301390] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.301531] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.301561] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.301609] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.301619] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.301643] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.301806] sda: sda1\r
+[ 3.301962] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.421573] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.421586] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.421610] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.421620] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.421643] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.421655] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.421742] usbcore: registered new interface driver usb-storage\r
+[ 3.421811] mousedev: PS/2 mouse device common for all mice\r
+[ 3.422007] usbcore: registered new interface driver usbhid\r
+[ 3.422016] usbhid: USB HID core driver\r
+[ 3.422056] TCP: cubic registered\r
+[ 3.422064] NET: Registered protocol family 17\r
+\0[ 3.422521] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.422562] devtmpfs: mounted\r
+[ 3.422633] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.464327] udevd[607]: starting version 182\r
+[ 3.464652] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.614662] random: dd urandom read with 21 bits of entropy available\r
+[ 3.594816] random: dd urandom read with 20 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.771415] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.761483] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
exitOnError=false
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu.checker.isa
istage2_mmu=system.cpu.checker.istage2_mmu
itb=system.cpu.checker.itb
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.checker.itb.walker.port system.cpu.checker.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 12461855003000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
-warn: 12461858210000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
+warn: 12469668093000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d780, checker: 0
+warn: 12469671548000: Instruction results do not match! (Values may not actually be integers) Inst: 0xffffffc00d07d7c0, checker: 0
warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
-warn: 13846883856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13889111424500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13890567287500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 13890857543500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14120809755000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14122306502500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14122718805500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14129885647500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14130112878000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14130333669000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14130937323000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14131157192000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14131378652000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14143275616000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14210692350500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14453290384000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14453290599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14461368009500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14469164155500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14469164395000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14469164601500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14477036010500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14477036254000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14477036493500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14477036700000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14482248599500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14482248839000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14488506207500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14488506438000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14498157332500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14498158077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14498158308000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14498158514500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14509187190500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14509187421000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14509187627500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14518942903500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14518943414000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14518943648500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14518943879000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14518944085500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14534430251500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14534430481500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14539499143500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14539499377500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14539499607500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14546501559500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14546502303000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14546502533000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14546502739500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14556606981000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14556607490500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14556607724500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14556607954500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14556608161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14619728573500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14619728789000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14678031922000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14678032489500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14678032742000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14678032990500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
-warn: 14678033206000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14803922617500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804021218000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804021536500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804745192000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804745453000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
-warn: 14804745657500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804816537000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14804816747000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804817018000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
-warn: 14804817588500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804817844000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
-warn: 14804818067500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804818356500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804818865500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804819928000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804820419500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14804820721500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
-warn: 14853183049500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
-warn: 14853362963500: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-warn: 14853363240000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14853363492000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14853363736500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14853363998500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
-warn: 14853364228000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 13859296387500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13859609734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13860504427500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13897233869500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13897642345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13920862903000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13921089576500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13947511863000: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 13980108581500: Instruction results do not match! (Values may not actually be integers) Inst: 0x1, checker: 0
+warn: 14222610860500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14222611461000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14222611711000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14222611957000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14222612172500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14230760994500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14230761201000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14238563882000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14238564861500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14238565068000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14246358412000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14246358927500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14246359161500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14246359391500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14246359598000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14251670590500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14251671564000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14251671770500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14258148326500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14258148556500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14258148763000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14267993950000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14267994180000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14279227060000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14279228043500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14279228273500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14279228480000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14289024214000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14289024957500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14289025187500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14289025394000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14304620359500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14304620589500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14309730901000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14309731131000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14309731337500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14316748039000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14316748269000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14326924073000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14326924303000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14390090123000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14390090371500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14447877040500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14447877289000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14573239339500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573336084000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573336377000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14573336936000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573337191500: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x93
+warn: 14573337414500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573337703500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573338212500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573339279500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573339771000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14573340089500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574085767500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574086028500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x42
+warn: 14574086233000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574157028000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14574157238000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574157509000: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf1
+warn: 14574158079500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574158335000: Instruction results do not match! (Values may not actually be integers) Inst: 0x90, checker: 0x91
+warn: 14574158558500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574158847500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574159356500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574160419500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574160917500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14574161219500: Instruction results do not match! (Values may not actually be integers) Inst: 0xf0, checker: 0xf3
+warn: 14623191245000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
+warn: 14623191536000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14623191788000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14623192032500: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14623192295000: Instruction results do not match! (Values may not actually be integers) Inst: 0x40, checker: 0x41
+warn: 14623192534000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 01:50:46
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 02:24:18
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-checker
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51562169701000 because m5_exit instruction encountered
+Exiting @ tick 51331518104000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 51.291801 # Number of seconds simulated
-sim_ticks 51291801227000 # Number of ticks simulated
-final_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.331518 # Number of seconds simulated
+sim_ticks 51331518104000 # Number of ticks simulated
+final_tick 51331518104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74063 # Simulator instruction rate (inst/s)
-host_op_rate 87030 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4454709483 # Simulator tick rate (ticks/s)
-host_mem_usage 731804 # Number of bytes of host memory used
-host_seconds 11514.06 # Real time elapsed on the host
-sim_insts 852762944 # Number of instructions simulated
-sim_ops 1002063356 # Number of ops (including micro ops) simulated
+host_inst_rate 55750 # Simulator instruction rate (inst/s)
+host_op_rate 65505 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3383587938 # Simulator tick rate (ticks/s)
+host_mem_usage 679676 # Number of bytes of host memory used
+host_seconds 15170.74 # Real time elapsed on the host
+sim_insts 845761974 # Number of instructions simulated
+sim_ops 993759083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81891560 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 205120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 196736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5673888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 72271240 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441728 # Number of bytes read from this memory
+system.physmem.bytes_read::total 78788712 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5673888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5673888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67330112 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 69986404 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 67350692 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 3205 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 104607 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1129251 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6902 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1247039 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1052033 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s)
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+system.physmem.bytesPerActivate::128-255 111955 23.50% 62.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 45179 9.48% 72.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 23084 4.84% 76.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 18337 3.85% 80.73% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 11525 2.42% 83.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 10900 2.29% 85.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 8098 1.70% 87.14% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 61295 12.86% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 476504 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 59915 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 20.799683 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 269.572248 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 59912 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 62413 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 62413 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.520677 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.965036 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.067360 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 59523 95.37% 95.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 900 1.44% 96.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 59 0.09% 96.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 320 0.51% 97.42% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 34 0.05% 97.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 343 0.55% 98.02% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 222 0.36% 98.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 19 0.03% 98.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 51 0.08% 98.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 131 0.21% 98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 29 0.05% 98.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 40 0.06% 98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 504 0.81% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 37 0.06% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 23 0.04% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 123 0.20% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 5 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 4 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 1 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 2 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 24 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 62413 # Writes before turning the bus around for reads
-system.physmem.totQLat 33295532684 # Total ticks spent queuing
-system.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6473725000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 59915 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 59915 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.563832 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.981523 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.290123 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 57069 95.25% 95.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 858 1.43% 96.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 58 0.10% 96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 312 0.52% 97.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 36 0.06% 97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 354 0.59% 97.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 211 0.35% 98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 25 0.04% 98.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 62 0.10% 98.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 123 0.21% 98.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 28 0.05% 98.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 35 0.06% 98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 500 0.83% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 29 0.05% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 31 0.05% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 125 0.21% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 7 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 2 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 2 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 5 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 19 0.03% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 3 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 6 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 59915 # Writes before turning the bus around for reads
+system.physmem.totQLat 31917471814 # Total ticks spent queuing
+system.physmem.totMemAccLat 55284528064 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6231215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25610.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44360.95 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 1061078 # Number of row buffer hits during reads
-system.physmem.writeRowHits 822147 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes
-system.physmem.avgGap 21449247.45 # Average gap between requests
-system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.513169 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states
+system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.76 # Average write queue length when enqueuing
+system.physmem.readRowHits 1024444 # Number of row buffer hits during reads
+system.physmem.writeRowHits 797630 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
+system.physmem.avgGap 22302099.93 # Average gap between requests
+system.physmem.pageHitRate 79.27 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1809644760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 987405375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4795167000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3404170800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1235982378375 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29714714061000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34314417854910 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.486362 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49432942986454 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1714072100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 184500143546 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.516119 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states
+system.physmem_1.actEnergy 1792725480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 978173625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4925481600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3414972960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1238461921980 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29712539014500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34314837317745 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.494534 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49429295042072 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1714072100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 188150328928 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 225483777 # Number of BP lookups
-system.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 104065621 # Number of BTB hits
+system.cpu.branchPred.lookups 223690256 # Number of BP lookups
+system.cpu.branchPred.condPredicted 149470273 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12181359 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 157723580 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 103180902 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 65.418818 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 30739943 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 342702 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.dtb.walker.walks 198855 # Table walker walks requested
-system.cpu.checker.dtb.walker.walksLong 198855 # Table walker walks initiated with long descriptors
-system.cpu.checker.dtb.walker.walkWaitTime::samples 198855 # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::0 198855 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.dtb.walker.walkWaitTime::total 198855 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walks 196399 # Table walker walks requested
+system.cpu.checker.dtb.walker.walksLong 196399 # Table walker walks initiated with long descriptors
+system.cpu.checker.dtb.walker.walkWaitTime::samples 196399 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::0 196399 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.dtb.walker.walkWaitTime::total 196399 # Table walker wait (enqueue to first request) latency
system.cpu.checker.dtb.walker.walksPending::samples -1585443796 # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::0 -1585443796 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.dtb.walker.walksPending::total -1585443796 # Table walker pending requests distribution
-system.cpu.checker.dtb.walker.walkPageSizes::4K 154365 91.27% 91.27% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::2M 14759 8.73% 100.00% # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkPageSizes::total 169124 # Table walker page sizes translated
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 198855 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkPageSizes::4K 153599 91.92% 91.92% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::2M 13493 8.08% 100.00% # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkPageSizes::total 167092 # Table walker page sizes translated
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 196399 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 198855 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 169124 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 196399 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 167092 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 169124 # Table walker requests started/completed, data/inst
-system.cpu.checker.dtb.walker.walkRequestOrigin::total 367979 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 167092 # Table walker requests started/completed, data/inst
+system.cpu.checker.dtb.walker.walkRequestOrigin::total 363491 # Table walker requests started/completed, data/inst
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 160299016 # DTB read hits
-system.cpu.checker.dtb.read_misses 147713 # DTB read misses
-system.cpu.checker.dtb.write_hits 145602296 # DTB write hits
-system.cpu.checker.dtb.write_misses 51142 # DTB write misses
+system.cpu.checker.dtb.read_hits 159160853 # DTB read hits
+system.cpu.checker.dtb.read_misses 146855 # DTB read misses
+system.cpu.checker.dtb.write_hits 144325246 # DTB write hits
+system.cpu.checker.dtb.write_misses 49544 # DTB write misses
system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.checker.dtb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.dtb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID
-system.cpu.checker.dtb.flush_entries 72297 # Number of entries that have been flushed from TLB
+system.cpu.checker.dtb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID
+system.cpu.checker.dtb.flush_entries 71588 # Number of entries that have been flushed from TLB
system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.checker.dtb.prefetch_faults 7392 # Number of TLB faults due to prefetch
+system.cpu.checker.dtb.prefetch_faults 6477 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.checker.dtb.perms_faults 19169 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 160446729 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 145653438 # DTB write accesses
+system.cpu.checker.dtb.perms_faults 18958 # Number of TLB faults due to permissions restrictions
+system.cpu.checker.dtb.read_accesses 159307708 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 144374790 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 305901312 # DTB hits
-system.cpu.checker.dtb.misses 198855 # DTB misses
-system.cpu.checker.dtb.accesses 306100167 # DTB accesses
+system.cpu.checker.dtb.hits 303486099 # DTB hits
+system.cpu.checker.dtb.misses 196399 # DTB misses
+system.cpu.checker.dtb.accesses 303682498 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.walker.walks 120055 # Table walker walks requested
-system.cpu.checker.itb.walker.walksLong 120055 # Table walker walks initiated with long descriptors
-system.cpu.checker.itb.walker.walkWaitTime::samples 120055 # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::0 120055 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.checker.itb.walker.walkWaitTime::total 120055 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walks 119834 # Table walker walks requested
+system.cpu.checker.itb.walker.walksLong 119834 # Table walker walks initiated with long descriptors
+system.cpu.checker.itb.walker.walkWaitTime::samples 119834 # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::0 119834 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.checker.itb.walker.walkWaitTime::total 119834 # Table walker wait (enqueue to first request) latency
system.cpu.checker.itb.walker.walksPending::samples -1586395296 # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::0 -1586395296 100.00% 100.00% # Table walker pending requests distribution
system.cpu.checker.itb.walker.walksPending::total -1586395296 # Table walker pending requests distribution
-system.cpu.checker.itb.walker.walkPageSizes::4K 108145 98.83% 98.83% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::2M 1280 1.17% 100.00% # Table walker page sizes translated
-system.cpu.checker.itb.walker.walkPageSizes::total 109425 # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::4K 107995 98.82% 98.82% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::2M 1286 1.18% 100.00% # Table walker page sizes translated
+system.cpu.checker.itb.walker.walkPageSizes::total 109281 # Table walker page sizes translated
system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120055 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120055 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 119834 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 119834 # Table walker requests started/completed, data/inst
system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109425 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109425 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.walker.walkRequestOrigin::total 229480 # Table walker requests started/completed, data/inst
-system.cpu.checker.itb.inst_hits 853171657 # ITB inst hits
-system.cpu.checker.itb.inst_misses 120055 # ITB inst misses
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109281 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109281 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.walker.walkRequestOrigin::total 229115 # Table walker requests started/completed, data/inst
+system.cpu.checker.itb.inst_hits 846167011 # ITB inst hits
+system.cpu.checker.itb.inst_misses 119834 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.write_hits 0 # DTB write hits
system.cpu.checker.itb.write_misses 0 # DTB write misses
system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.checker.itb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID
-system.cpu.checker.itb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries 51971 # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.checker.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID
+system.cpu.checker.itb.flush_entries 51635 # Number of entries that have been flushed from TLB
system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 853291712 # ITB inst accesses
-system.cpu.checker.itb.hits 853171657 # DTB hits
-system.cpu.checker.itb.misses 120055 # DTB misses
-system.cpu.checker.itb.accesses 853291712 # DTB accesses
-system.cpu.checker.numCycles 1002635249 # number of cpu cycles simulated
+system.cpu.checker.itb.inst_accesses 846286845 # ITB inst accesses
+system.cpu.checker.itb.hits 846167011 # DTB hits
+system.cpu.checker.itb.misses 119834 # DTB misses
+system.cpu.checker.itb.accesses 846286845 # DTB accesses
+system.cpu.checker.numCycles 994327079 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 951545 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks 934978 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 934978 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15042 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154863 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 425141 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 509837 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 2238.847906 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535 506434 99.33% 99.33% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071 1917 0.38% 99.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607 986 0.19% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679 153 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215 25 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287 51 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 509837 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 473320 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 462482 97.71% 97.71% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 7672 1.62% 99.33% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 2249 0.48% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 179 0.04% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 532 0.11% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 62 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 112 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 23 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 473320 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 784047304876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.724244 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.519446 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 781857637876 99.72% 99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 1171824000 0.15% 99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 476098500 0.06% 99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 199009000 0.03% 99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 143211000 0.02% 99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 120940000 0.02% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 26747000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 49238000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 2599500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 784047304876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 154864 91.15% 91.15% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15042 8.85% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 169906 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 934978 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 934978 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169906 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169906 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 1104884 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 170217039 # DTB read hits
-system.cpu.dtb.read_misses 674912 # DTB read misses
-system.cpu.dtb.write_hits 148367148 # DTB write hits
-system.cpu.dtb.write_misses 276633 # DTB write misses
+system.cpu.dtb.read_hits 168982671 # DTB read hits
+system.cpu.dtb.read_misses 669792 # DTB read misses
+system.cpu.dtb.write_hits 147065605 # DTB write hits
+system.cpu.dtb.write_misses 265186 # DTB write misses
system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 71824 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 98 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9312 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 170891951 # DTB read accesses
-system.cpu.dtb.write_accesses 148643781 # DTB write accesses
+system.cpu.dtb.perms_faults 69742 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 169652463 # DTB read accesses
+system.cpu.dtb.write_accesses 147330791 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 318584187 # DTB hits
-system.cpu.dtb.misses 951545 # DTB misses
-system.cpu.dtb.accesses 319535732 # DTB accesses
+system.cpu.dtb.hits 316048276 # DTB hits
+system.cpu.dtb.misses 934978 # DTB misses
+system.cpu.dtb.accesses 316983254 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 161585 # Table walker walks requested
-system.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 161206 # Table walker walks requested
+system.cpu.itb.walker.walksLong 161206 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1436 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 121549 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 17620 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 143586 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 1244.532893 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 9274.227664 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767 142628 99.33% 99.33% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535 542 0.38% 99.71% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303 55 0.04% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071 79 0.06% 99.80% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839 218 0.15% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607 29 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911 14 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 143586 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 140605 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28864.162014 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 137806 98.01% 98.01% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 710 0.50% 98.51% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 1778 1.26% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 108 0.08% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 117 0.08% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 38 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 35 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 140605 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 663785102088 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.942542 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.233053 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 38191035356 5.75% 5.75% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 625543374232 94.24% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 49878500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 812000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 663785102088 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 121549 98.83% 98.83% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1436 1.17% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 122985 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161206 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 161206 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 358536824 # ITB inst hits
-system.cpu.itb.inst_misses 161585 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122985 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 122985 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 284191 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 355626065 # ITB inst hits
+system.cpu.itb.inst_misses 161206 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 79546 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 2046 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid 78304 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 2034 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 52940 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 369021 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 358698409 # ITB inst accesses
-system.cpu.itb.hits 358536824 # DTB hits
-system.cpu.itb.misses 161585 # DTB misses
-system.cpu.itb.accesses 358698409 # DTB accesses
-system.cpu.numCycles 1657263364 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 355787271 # ITB inst accesses
+system.cpu.itb.hits 355626065 # DTB hits
+system.cpu.itb.misses 161206 # DTB misses
+system.cpu.itb.accesses 355787271 # DTB accesses
+system.cpu.numCycles 1638586091 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 642614268 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 998103903 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 223690256 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133920845 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 910005464 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 26014386 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 3801464 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 28966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 9302327 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1031206 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 853 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 355240310 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6091194 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 48629 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 1579791741 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.740255 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.146164 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1024362050 64.84% 64.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 213190505 13.49% 78.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 70458696 4.46% 82.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 271780490 17.20% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 434692108 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 440187114 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1579791741 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.136514 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.609125 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 522893988 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 566130284 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 431833495 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 49726107 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9207867 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33553949 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 3859168 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1081567524 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 28956293 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9207867 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 567372760 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 69190624 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 368823691 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 437050453 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 128146346 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1061861877 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 6771880 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 5087051 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 328687 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 662195 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 77193560 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 20256 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1009820206 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1635273516 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1255804175 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1470464 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 944392449 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 65427754 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 26765768 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23112103 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 102007080 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173010630 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 150618329 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 9860591 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8967243 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1027007600 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27059230 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1042343751 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3268943 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 60307743 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33600701 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 312855 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1579791741 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.659798 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.917984 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 934526324 59.16% 59.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 332943694 21.08% 80.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234048480 14.82% 95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 71809082 4.55% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6444954 0.41% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 19207 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1579791741 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57575402 35.04% 35.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 100057 0.06% 35.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 764 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44168987 26.88% 62.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 62424891 38.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 717769712 68.86% 68.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2531817 0.24% 69.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 122691 0.01% 69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 121277 0.01% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 172853843 16.58% 85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 148944351 14.29% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued
-system.cpu.iq.rate 0.634165 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1042343751 # Type of FU issued
+system.cpu.iq.rate 0.636124 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 164296841 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157623 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3829567748 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1113568735 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1024464263 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 2477278 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 947290 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 909965 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1205083989 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1556592 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 4287735 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13755130 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14415 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 142727 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6290239 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2513645 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1546946 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 9207867 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 6935208 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9652893 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1054288001 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 173010630 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 150618329 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 22687803 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 56498 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 9524585 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 142727 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3650015 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 5096410 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8746425 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1031209628 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 168969861 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10209992 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222579 # number of nop insts executed
-system.cpu.iew.exec_refs 318568485 # number of memory reference insts executed
-system.cpu.iew.exec_branches 197267293 # Number of branches executed
-system.cpu.iew.exec_stores 148362844 # Number of stores executed
-system.cpu.iew.exec_rate 0.627402 # Inst execution rate
-system.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 440084197 # num instructions producing a value
-system.cpu.iew.wb_consumers 711913770 # num instructions consuming a value
+system.cpu.iew.exec_nop 221171 # number of nop insts executed
+system.cpu.iew.exec_refs 316030804 # number of memory reference insts executed
+system.cpu.iew.exec_branches 195653401 # Number of branches executed
+system.cpu.iew.exec_stores 147060943 # Number of stores executed
+system.cpu.iew.exec_rate 0.629329 # Inst execution rate
+system.cpu.iew.wb_sent 1026179606 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1025374228 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 436457494 # num instructions producing a value
+system.cpu.iew.wb_consumers 705894723 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.623840 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.625768 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.618304 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 51232529 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 26746375 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 8382033 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1567845308 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.633837 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.270098 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1057713558 67.46% 67.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 286814809 18.29% 85.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 120141410 7.66% 93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 36433500 2.32% 95.74% # Number of insts commited each cycle
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+system.cpu.commit.committed_per_cycle::7 4169387 0.27% 99.26% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 852762944 # Number of instructions committed
-system.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 306001487 # Number of memory references committed
-system.cpu.commit.loads 160395163 # Number of loads committed
-system.cpu.commit.membars 6971183 # Number of memory barriers committed
-system.cpu.commit.branches 190333133 # Number of branches committed
-system.cpu.commit.fp_insts 897329 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 920660333 # Number of committed integer instructions.
-system.cpu.commit.function_calls 25420821 # Number of function calls committed.
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+system.cpu.commit.branches 188760643 # Number of branches committed
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system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
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-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
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-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction
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-system.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached
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-system.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.943405 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.514561 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads
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+system.cpu.committedOps 993759083 # Number of Ops (including micro ops) Simulated
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+system.cpu.cpi_total 1.937408 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.516154 # IPC: Total IPC of All Threads
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-system.cpu.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.LoadLockedReq_misses::total 450358 # number of LoadLockedReq misses
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system.cpu.dcache.StoreCondReq_miss_latency::total 276500 # number of StoreCondReq miss cycles
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-system.cpu.dcache.SoftPFReq_accesses::total 1562277 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 3771413 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3719267 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3719267 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 297663396 # number of demand (read+write) accesses
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13270991500 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005792 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.785587 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.785587 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784579 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784579 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207560 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207560 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005633 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.040343 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040343 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.409431 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.409431 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.031106 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.031106 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128612.839940 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70763.655401 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70763.655401 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.198000 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.198000 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005556 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038377 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038377 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.404153 # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.404153 # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.029592 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.029592 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128635.929288 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70759.652909 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70759.652909 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129127.304187 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129127.304187 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124571.716553 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124571.716553 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129275.526257 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 50050277 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 25391485 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3463 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2168 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2168 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1617253 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23096406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 8520965 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 17374022 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 43114 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1898399 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp 43119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1956286 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1956286 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15001430 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 6485775 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1330832 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1224168 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45043419 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29192673 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728958 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917333 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 76882383 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960419312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017977630 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2410856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6261232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1987069030 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1835462 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 52366647 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.013365 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.114833 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 51666749 98.66% 98.66% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 699898 1.34% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 52366647 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32990991996 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1490388 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 22530796241 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13336103780 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 427917846 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1135029759 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40289 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40289 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
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system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3830691 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3960313 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 341363 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 341363 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4301676 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3680509 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3810131 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342394 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 342394 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4152525 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3147 # Total snoops (count)
-system.membus.snoop_fanout::samples 2799608 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138873356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 139043342 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7266048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 146309390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2606 # Total snoops (count)
+system.membus.snoop_fanout::samples 2698981 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2698981 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2799608 # Request fanout histogram
-system.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2698981 # Request fanout histogram
+system.membus.reqLayer0.occupancy 104149000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5470500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7144084722 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6645299856 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 228305891 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 16105 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000019] Console: colour dummy device 80x25\r
-[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000022] pid_max: default: 32768 minimum: 301\r
-[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000129] hw perfevents: no hardware support available\r
-[ 1.060065] CPU1: failed to come online\r
-[ 2.080127] CPU2: failed to come online\r
-[ 3.100189] CPU3: failed to come online\r
-[ 3.100192] Brought up 1 CPUs\r
-[ 3.100193] SMP: Total of 1 processors activated.\r
-[ 3.100240] devtmpfs: initialized\r
-[ 3.100669] atomic64_test: passed\r
-[ 3.100708] regulator-dummy: no parameters\r
-[ 3.101069] NET: Registered protocol family 16\r
-[ 3.101188] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101196] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101685] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101689] Serial: AMBA PL011 UART driver\r
-[ 3.101859] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101891] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102431] console [ttyAMA0] enabled\r
-[ 3.102499] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102529] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102560] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102589] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130477] 3V3: 3300 mV \r
-[ 3.130516] vgaarb: loaded\r
-[ 3.130558] SCSI subsystem initialized\r
-[ 3.130594] libata version 3.00 loaded.\r
-[ 3.130636] usbcore: registered new interface driver usbfs\r
-[ 3.130652] usbcore: registered new interface driver hub\r
-[ 3.130683] usbcore: registered new device driver usb\r
-[ 3.130706] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130715] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130733] PTP clock support registered\r
-[ 3.130839] Switched to clocksource arch_sys_counter\r
-[ 3.131808] NET: Registered protocol family 2\r
-[ 3.131874] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131890] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131908] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131922] TCP: reno registered\r
-[ 3.131928] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131941] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131975] NET: Registered protocol family 1\r
-[ 3.132021] RPC: Registered named UNIX socket transport module.\r
-[ 3.132031] RPC: Registered udp transport module.\r
-[ 3.132039] RPC: Registered tcp transport module.\r
-[ 3.132047] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132058] PCI: CLS 0 bytes, default 64\r
-[ 3.132196] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132285] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133797] fuse init (API version 7.23)\r
-[ 3.133873] msgmni has been set to 469\r
-[ 3.135927] io scheduler noop registered\r
-[ 3.135975] io scheduler cfq registered (default)\r
-[ 3.136358] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136370] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136381] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136393] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136402] pci_bus 0000:00: scanning bus\r
-[ 3.136412] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136424] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136438] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136471] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136483] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136493] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136503] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136513] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136524] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136534] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136567] pci_bus 0000:00: fixups for bus\r
-[ 3.136574] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136586] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136603] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136611] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136621] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136629] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136639] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136651] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136664] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136676] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136687] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136698] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136709] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136720] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.137151] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137378] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137387] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137408] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137658] scsi0 : ata_piix\r
-[ 3.137744] scsi1 : ata_piix\r
-[ 3.137771] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137783] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137876] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137888] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137902] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137913] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290861] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290871] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290896] ata1.00: configured for UDMA/33\r
-[ 3.290937] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.291037] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.291060] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.291095] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.291104] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.291123] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291229] sda: sda1\r
-[ 3.291331] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411127] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411139] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411159] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411168] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411187] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411198] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411260] usbcore: registered new interface driver usb-storage\r
-[ 3.411309] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411443] usbcore: registered new interface driver usbhid\r
-[ 3.411452] usbhid: USB HID core driver\r
-[ 3.411480] TCP: cubic registered\r
-[ 3.411487] NET: Registered protocol family 17\r
-\0[ 3.411792] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411823] devtmpfs: mounted\r
-[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000022] Console: colour dummy device 80x25\r
+[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000025] pid_max: default: 32768 minimum: 301\r
+[ 0.000037] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000038] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000160] hw perfevents: no hardware support available\r
+[ 1.060066] CPU1: failed to come online\r
+[ 2.080128] CPU2: failed to come online\r
+[ 3.100190] CPU3: failed to come online\r
+[ 3.100193] Brought up 1 CPUs\r
+[ 3.100194] SMP: Total of 1 processors activated.\r
+[ 3.100250] devtmpfs: initialized\r
+[ 3.100699] atomic64_test: passed\r
+[ 3.100742] regulator-dummy: no parameters\r
+[ 3.101165] NET: Registered protocol family 16\r
+[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101300] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.102009] Serial: AMBA PL011 UART driver\r
+[ 3.102199] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.102234] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102775] console [ttyAMA0] enabled\r
+[ 3.102856] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102886] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102917] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102946] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130499] 3V3: 3300 mV \r
+[ 3.130541] vgaarb: loaded\r
+[ 3.130587] SCSI subsystem initialized\r
+[ 3.130624] libata version 3.00 loaded.\r
+[ 3.130668] usbcore: registered new interface driver usbfs\r
+[ 3.130685] usbcore: registered new interface driver hub\r
+[ 3.130716] usbcore: registered new device driver usb\r
+[ 3.130740] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130749] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130767] PTP clock support registered\r
+[ 3.130884] Switched to clocksource arch_sys_counter\r
+[ 3.131878] NET: Registered protocol family 2\r
+[ 3.131953] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131970] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131991] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.132006] TCP: reno registered\r
+[ 3.132013] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132027] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132067] NET: Registered protocol family 1\r
+[ 3.132117] RPC: Registered named UNIX socket transport module.\r
+[ 3.132127] RPC: Registered udp transport module.\r
+[ 3.132135] RPC: Registered tcp transport module.\r
+[ 3.132142] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132154] PCI: CLS 0 bytes, default 64\r
+[ 3.132300] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132399] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133955] fuse init (API version 7.23)\r
+[ 3.134034] msgmni has been set to 469\r
+[ 3.136162] io scheduler noop registered\r
+[ 3.136212] io scheduler cfq registered (default)\r
+[ 3.136647] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136660] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136670] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136682] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136692] pci_bus 0000:00: scanning bus\r
+[ 3.136702] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136715] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136729] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136765] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136776] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136787] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136797] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136807] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136817] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136828] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136861] pci_bus 0000:00: fixups for bus\r
+[ 3.136869] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136881] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136900] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136908] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136918] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136926] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136937] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136949] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136962] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136974] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136985] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136996] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.137007] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.137018] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.137463] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137704] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137714] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137738] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.138003] scsi0 : ata_piix\r
+[ 3.138095] scsi1 : ata_piix\r
+[ 3.138123] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.138135] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.138234] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.138245] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.138260] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.138271] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290909] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290918] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290944] ata1.00: configured for UDMA/33\r
+[ 3.290993] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.291096] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.291119] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.291156] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.291164] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.291183] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291296] sda: sda1\r
+[ 3.291402] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411176] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411189] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411209] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411218] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411237] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411249] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411312] usbcore: registered new interface driver usb-storage\r
+[ 3.411363] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411500] usbcore: registered new interface driver usbhid\r
+[ 3.411510] usbhid: USB HID core driver\r
+[ 3.411540] TCP: cubic registered\r
+[ 3.411547] NET: Registered protocol family 17\r
+\0[ 3.411879] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411912] devtmpfs: mounted\r
+[ 3.411960] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450179] udevd[607]: starting version 182\r
+[ 3.450384] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.543317] random: dd urandom read with 19 bits of entropy available\r
+[ 3.543428] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
Mon Jan 27 08:00:00 UTC 2014\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... [ 3.671067] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Configuring network interfaces... [ 3.671113] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
udhcpc (v1.21.1) started\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu0.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.cpu0.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu1.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+[system.cpu1.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
warn: allocating bonus target for snoop
warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
+warn: allocating bonus target for snoop
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 14 2015 23:59:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 04:14:20
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47309815475000 because m5_exit instruction encountered
+Exiting @ tick 47395178174000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 47.434893 # Number of seconds simulated
-sim_ticks 47434893411000 # Number of ticks simulated
-final_tick 47434893411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.395178 # Number of seconds simulated
+sim_ticks 47395178174000 # Number of ticks simulated
+final_tick 47395178174000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99639 # Simulator instruction rate (inst/s)
-host_op_rate 117176 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5152463712 # Simulator tick rate (ticks/s)
-host_mem_usage 784704 # Number of bytes of host memory used
-host_seconds 9206.25 # Real time elapsed on the host
-sim_insts 917301737 # Number of instructions simulated
-sim_ops 1078753903 # Number of ops (including micro ops) simulated
+host_inst_rate 85380 # Simulator instruction rate (inst/s)
+host_op_rate 100389 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4378207332 # Simulator tick rate (ticks/s)
+host_mem_usage 733200 # Number of bytes of host memory used
+host_seconds 10825.25 # Real time elapsed on the host
+sim_insts 924259255 # Number of instructions simulated
+sim_ops 1086731985 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 208192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 203648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 4658336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 45847432 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 22095168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 91328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 66368 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2323808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 12264528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 10934912 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 422080 # Number of bytes read from this memory
-system.physmem.bytes_read::total 99115800 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4658336 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2323808 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6982144 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 83002560 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 173952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 172224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 5051936 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 46751112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 21558016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 154688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 128576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2266144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 13742800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 14572608 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 453056 # Number of bytes read from this memory
+system.physmem.bytes_read::total 105025112 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 5051936 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2266144 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 7318080 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 87763520 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 83023144 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 3253 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 3182 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 88739 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 716379 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 345237 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 1427 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 1037 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 36353 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 191646 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 170858 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6595 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1564706 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1296915 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 87784104 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2718 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2691 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 94889 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 730499 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 336844 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 2417 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 2009 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 35452 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 214744 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 227697 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 7079 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1657039 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1371305 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1299489 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 4389 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 4293 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 98205 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 966534 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 465800 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 1925 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 1399 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 48989 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 258555 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 230525 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8898 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2089512 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 98205 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 48989 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 147194 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1749821 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1373879 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 3670 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 3634 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 106592 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 986411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 454857 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 3264 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 2713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 47814 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 289962 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 307470 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 9559 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2215945 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 106592 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 47814 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 154406 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1851739 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1750255 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1749821 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 4389 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 4293 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 98205 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 966968 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 465800 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 1925 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 1399 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 48989 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 258555 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 230525 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8898 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3839767 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1564706 # Number of read requests accepted
-system.physmem.writeReqs 1299489 # Number of write requests accepted
-system.physmem.readBursts 1564706 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1299489 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 100111296 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 29888 # Total number of bytes read from write queue
-system.physmem.bytesWritten 83021568 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 99115800 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 83023144 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 467 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1852174 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1851739 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 3670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 3634 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 106592 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 986845 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 454857 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 3264 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 2713 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 47814 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 289962 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 47434891912500 # Total gap between requests
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::mean 187.273406 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::stdev 243.900483 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::40-43 179 0.24% 98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 107 0.15% 98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 91 0.12% 98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 122 0.17% 98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 36 0.05% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 46 0.06% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 419 0.57% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 29 0.04% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 25 0.03% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 117 0.16% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 10 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 3 0.00% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.00% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 4 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.01% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 3 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 2 0.00% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 27 0.04% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 3 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 78027 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 78027 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.578710 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.107570 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 6.499017 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 72603 93.05% 93.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 2990 3.83% 96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 480 0.62% 97.50% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 334 0.43% 97.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 81 0.10% 98.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 301 0.39% 98.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 173 0.22% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 106 0.14% 98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 88 0.11% 98.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 126 0.16% 99.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 37 0.05% 99.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 56 0.07% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 406 0.52% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 31 0.04% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 24 0.03% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 123 0.16% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 13 0.02% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 4 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 5 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 17 0.02% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::184-187 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 73621 # Writes before turning the bus around for reads
-system.physmem.totQLat 78457411069 # Total ticks spent queuing
-system.physmem.totMemAccLat 107786892319 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 7821195000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 50156.92 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::236-239 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 78027 # Writes before turning the bus around for reads
+system.physmem.totQLat 82234419314 # Total ticks spent queuing
+system.physmem.totMemAccLat 113295181814 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 8282870000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 49641.26 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 68906.92 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.75 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 2.09 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.75 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 68391.26 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.14 # Average write queue length when enqueuing
-system.physmem.readRowHits 1261076 # Number of row buffer hits during reads
-system.physmem.writeRowHits 622485 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 80.62 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 47.99 # Row buffer hit rate for writes
-system.physmem.avgGap 16561334.66 # Average gap between requests
-system.physmem.pageHitRate 65.82 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3784611600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2065016250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 6155541600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4268064960 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1175166619965 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27430083930000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31719739959975 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.700662 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45632003284876 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1583955100000 # Time in different power states
+system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing
+system.physmem.readRowHits 1332435 # Number of row buffer hits during reads
+system.physmem.writeRowHits 649185 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 80.43 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 47.33 # Row buffer hit rate for writes
+system.physmem.avgGap 15637234.88 # Average gap between requests
+system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4004169120 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2184814500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 6475833000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 4480207200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1180796903550 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27401319159750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31694883606720 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.736482 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45584100048214 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1582629100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 218928032624 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 228448334286 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3608221680 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1968771750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 6045468000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4137868800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3098216175600 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1172302278480 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27432596510250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31718875294560 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.682434 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45636187348814 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1583955100000 # Time in different power states
+system.physmem_1.actEnergy 3907869840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2132270250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 6445397400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4407851520 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1181668397355 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27400554691500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31694738997465 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.733431 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45582807436264 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1582629100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 214746668686 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 229740006236 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 146144434 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 97047776 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 7141884 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 102585049 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 68142392 # Number of BTB hits
+system.cpu0.branchPred.lookups 146971248 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 97492286 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 7372479 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 103605243 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 68020426 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 66.425266 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 20061645 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 208019 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 65.653459 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 20148210 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 220615 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 627056 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 627056 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13350 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 99805 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 293358 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 333698 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 2422.801455 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 15109.123610 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 330908 99.16% 99.16% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 1425 0.43% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 1094 0.33% 99.92% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 126 0.04% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 71 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 333698 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 325671 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 20358.917435 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 16786.442146 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 23186.053079 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 321319 98.66% 98.66% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 949 0.29% 98.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2404 0.74% 99.69% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 140 0.04% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 546 0.17% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 110 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 121 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 26 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 325671 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 568195090048 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.606171 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.541778 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 566772056048 99.75% 99.75% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 811255500 0.14% 99.89% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 288193500 0.05% 99.94% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 133409000 0.02% 99.97% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 101036500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 47966000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 17568000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 22933000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 641000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::18-19 31500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 568195090048 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 99806 88.20% 88.20% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 13350 11.80% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 113156 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 627056 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 621589 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 621589 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13120 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97816 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 286624 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 334965 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 2330.974878 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535 332297 99.20% 99.20% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071 1432 0.43% 99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607 943 0.28% 99.91% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215 84 0.03% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 334965 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 317874 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 314157 98.83% 98.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.26% 99.09% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2043 0.64% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 147 0.05% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 407 0.13% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 108 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 100 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 317874 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 575732613804 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.609948 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.538779 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 574368413804 99.76% 99.76% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 774580000 0.13% 99.90% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 276702000 0.05% 99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 125012500 0.02% 99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 99386000 0.02% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 49877000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 16787500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 21052000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 785500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 575732613804 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 97816 88.17% 88.17% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 13120 11.83% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 110936 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 621589 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 627056 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 113156 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 621589 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110936 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 113156 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 740212 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110936 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 732525 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 106442927 # DTB read hits
-system.cpu0.dtb.read_misses 452572 # DTB read misses
-system.cpu0.dtb.write_hits 87367482 # DTB write hits
-system.cpu0.dtb.write_misses 174484 # DTB write misses
+system.cpu0.dtb.read_hits 106854280 # DTB read hits
+system.cpu0.dtb.read_misses 451291 # DTB read misses
+system.cpu0.dtb.write_hits 87452638 # DTB write hits
+system.cpu0.dtb.write_misses 170298 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 43076 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 336 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 7862 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 41576 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 658 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 7382 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 41749 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 106895499 # DTB read accesses
-system.cpu0.dtb.write_accesses 87541966 # DTB write accesses
+system.cpu0.dtb.perms_faults 40291 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 107305571 # DTB read accesses
+system.cpu0.dtb.write_accesses 87622936 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 193810409 # DTB hits
-system.cpu0.dtb.misses 627056 # DTB misses
-system.cpu0.dtb.accesses 194437465 # DTB accesses
+system.cpu0.dtb.hits 194306918 # DTB hits
+system.cpu0.dtb.misses 621589 # DTB misses
+system.cpu0.dtb.accesses 194928507 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 89572 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 89572 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1024 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63745 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 10456 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 79116 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1699.586683 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 13044.450560 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767 78197 98.84% 98.84% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535 434 0.55% 99.39% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303 37 0.05% 99.43% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071 79 0.10% 99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839 275 0.35% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679 8 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 79116 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 75225 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 26620.711200 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 21926.293248 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 30000.304563 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 72890 96.90% 96.90% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 127 0.17% 97.06% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 1867 2.48% 99.55% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 130 0.17% 99.72% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 117 0.16% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 47 0.06% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 75225 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 417841685688 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.859653 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.347613 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 58676119976 14.04% 14.04% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 359136359212 85.95% 99.99% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 25573000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 3283500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 186000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5 60000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6 104000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 417841685688 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 63745 98.42% 98.42% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 1024 1.58% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 64769 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 88821 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 88821 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1050 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63713 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 10161 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 78660 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1640.999237 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767 77771 98.87% 98.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535 446 0.57% 99.44% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303 46 0.06% 99.50% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071 60 0.08% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839 236 0.30% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607 63 0.08% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 78660 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 74924 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 72785 97.15% 97.15% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 128 0.17% 97.32% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 1706 2.28% 99.59% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 120 0.16% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 74924 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 438261516832 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.857100 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 62664607652 14.30% 14.30% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 375564750680 85.69% 99.99% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 27774000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 4139500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5 57000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 438261516832 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 63713 98.38% 98.38% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 1050 1.62% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 64763 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 89572 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 89572 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88821 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88821 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64769 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64769 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 154341 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 230754760 # ITB inst hits
-system.cpu0.itb.inst_misses 89572 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64763 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64763 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 153584 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 231690538 # ITB inst hits
+system.cpu0.itb.inst_misses 88821 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 31365 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 30101 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 227814 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 229340 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 230844332 # ITB inst accesses
-system.cpu0.itb.hits 230754760 # DTB hits
-system.cpu0.itb.misses 89572 # DTB misses
-system.cpu0.itb.accesses 230844332 # DTB accesses
-system.cpu0.numCycles 860058385 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 231779359 # ITB inst accesses
+system.cpu0.itb.hits 231690538 # DTB hits
+system.cpu0.itb.misses 88821 # DTB misses
+system.cpu0.itb.accesses 231779359 # DTB accesses
+system.cpu0.numCycles 863793222 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 93823767 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 647034006 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 146144434 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 88204037 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 713428063 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 15421284 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 2142608 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 370377 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 6662477 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 811703 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 935488 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 230526197 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 1802314 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 29828 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 825885125 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.917836 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.204243 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 99193613 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 650316460 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 146971248 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 88168636 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 710473999 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 15870286 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 2085677 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 375453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 6582690 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 821108 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 973136 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 231460528 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 1900058 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 29560 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 828440819 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.919217 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.204961 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 462725297 56.03% 56.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 141134334 17.09% 73.12% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 49183945 5.96% 79.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 172841549 20.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 463819781 55.99% 55.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 141489715 17.08% 73.07% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 49366419 5.96% 79.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 173764904 20.97% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 825885125 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.169924 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.752314 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 112769742 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 426082666 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 241448796 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 40086734 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5497187 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 21049410 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 2256773 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 670218998 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 24585217 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5497187 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 150343342 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 70257974 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 265091659 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 243360217 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 91334746 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 651968055 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 6322268 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 11333163 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 398238 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 892987 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 53687870 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 12055 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 623161441 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1008090615 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 769730678 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 803084 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 561865875 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 61295566 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 16618595 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 14448752 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 81009207 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 106588320 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 90921259 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 9791542 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 8386441 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 628410475 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 16690332 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 633219394 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 2873840 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 57472988 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 37517559 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 288712 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 825885125 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.766716 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.051496 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 828440819 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.170146 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.752861 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 116939951 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 422028211 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 244586455 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 39268558 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5617644 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 21189817 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 2362286 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 672848975 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 25418616 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5617644 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 154577177 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 70595603 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 261705373 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 245642920 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 90302102 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 654266166 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 6467849 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 11101204 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 403453 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 928162 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 53323892 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 11721 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 625141147 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1009026275 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 772228505 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 892399 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 562735066 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 62406074 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 16247606 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 14088158 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 79534921 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 107241964 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 91079408 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 9519471 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 8265411 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 630985849 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 16282634 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 634912655 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 2916139 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 58420750 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 480372364 58.16% 58.16% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 144500445 17.50% 75.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 122618774 14.85% 90.51% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 70098834 8.49% 99.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 8288641 1.00% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 6067 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 482464203 58.24% 58.24% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 143786503 17.36% 75.59% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 123657330 14.93% 90.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 70325398 8.49% 99.01% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 8201627 0.99% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 5758 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 825885125 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 828440819 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 65372240 45.40% 45.40% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 70238 0.05% 45.45% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 24747 0.02% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 29 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.46% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 37918627 26.33% 71.79% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 40615883 28.21% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 65751499 45.58% 45.58% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 72629 0.05% 45.63% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 24296 0.02% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 30 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.64% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 37784970 26.19% 71.84% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 40630472 28.16% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 10 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 433018605 68.38% 68.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1583156 0.25% 68.63% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 81666 0.01% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 80947 0.01% 68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.66% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 109728452 17.33% 85.99% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 88726558 14.01% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 434162938 68.38% 68.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 1557110 0.25% 68.63% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 85116 0.01% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 3 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 85507 0.01% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 110176891 17.35% 86.01% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 88845090 13.99% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 633219394 # Type of FU issued
-system.cpu0.iq.rate 0.736252 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 144001764 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.227412 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 2237858803 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 702176142 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 615023589 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 1340714 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 546565 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 499647 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 776393889 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 827259 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 2940154 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 634912655 # Type of FU issued
+system.cpu0.iq.rate 0.735029 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 144263896 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.227218 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 2243978291 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 705234549 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 616677073 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 1467869 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 599303 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 545442 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 778270494 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 906057 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 2895519 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 13228982 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 17998 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 150420 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 6097724 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 13298175 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 18246 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 145606 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 6202009 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2855732 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 4944067 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2767326 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 4824800 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5497187 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 8555370 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 7804154 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 645228891 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 5617644 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 8735359 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 7907130 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 647396791 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 106588320 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 90921259 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 14154267 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 60797 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 7667643 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 150420 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2190803 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 3056972 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 5247775 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 624930976 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 106438227 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 7669606 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 107241964 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 91079408 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 13794371 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 59022 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 7772545 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 145606 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 2195305 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 3186569 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 5381874 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 626447733 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 106847652 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 7850968 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 128084 # number of nop insts executed
-system.cpu0.iew.exec_refs 193805308 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 117788400 # Number of branches executed
-system.cpu0.iew.exec_stores 87367081 # Number of stores executed
-system.cpu0.iew.exec_rate 0.726615 # Inst execution rate
-system.cpu0.iew.wb_sent 616360773 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 615523236 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 299533919 # num instructions producing a value
-system.cpu0.iew.wb_consumers 491459888 # num instructions consuming a value
+system.cpu0.iew.exec_nop 128308 # number of nop insts executed
+system.cpu0.iew.exec_refs 194298385 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 118240799 # Number of branches executed
+system.cpu0.iew.exec_stores 87450733 # Number of stores executed
+system.cpu0.iew.exec_rate 0.725229 # Inst execution rate
+system.cpu0.iew.wb_sent 618051464 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 617222515 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 300479191 # num instructions producing a value
+system.cpu0.iew.wb_consumers 493067457 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.715676 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.609478 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.714549 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.609408 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 50152735 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 16401620 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4928429 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 816336878 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.719835 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.528210 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 50926327 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 15994032 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 5054980 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 818740070 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.719212 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.525829 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 559210939 68.50% 68.50% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 132620550 16.25% 84.75% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 57447612 7.04% 91.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 19359516 2.37% 94.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 13667086 1.67% 95.83% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 9472900 1.16% 96.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 6300261 0.77% 97.76% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3865026 0.47% 98.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 14392988 1.76% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 561213375 68.55% 68.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 132109065 16.14% 84.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 58113446 7.10% 91.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 19548895 2.39% 94.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 13854430 1.69% 95.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 9447713 1.15% 97.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 6268110 0.77% 97.78% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3880157 0.47% 98.25% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 14304879 1.75% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 816336878 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 500561663 # Number of instructions committed
-system.cpu0.commit.committedOps 587627818 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 818740070 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 501771314 # Number of instructions committed
+system.cpu0.commit.committedOps 588847718 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 178182873 # Number of memory references committed
-system.cpu0.commit.loads 93359338 # Number of loads committed
-system.cpu0.commit.membars 3999106 # Number of memory barriers committed
-system.cpu0.commit.branches 111869987 # Number of branches committed
-system.cpu0.commit.fp_insts 487433 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 538915028 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 14906557 # Number of function calls committed.
+system.cpu0.commit.refs 178821180 # Number of memory references committed
+system.cpu0.commit.loads 93943789 # Number of loads committed
+system.cpu0.commit.membars 3938709 # Number of memory barriers committed
+system.cpu0.commit.branches 112215548 # Number of branches committed
+system.cpu0.commit.fp_insts 531565 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 540152053 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 14962116 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 407981366 69.43% 69.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 1327807 0.23% 69.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 64470 0.01% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.67% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 71302 0.01% 69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.68% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 93359338 15.89% 85.57% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 84823535 14.43% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 408576800 69.39% 69.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 1307130 0.22% 69.61% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 67517 0.01% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 75091 0.01% 69.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 93943789 15.95% 85.59% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 84877391 14.41% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 587627818 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 14392988 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 1435053387 # The number of ROB reads
-system.cpu0.rob.rob_writes 1285071513 # The number of ROB writes
-system.cpu0.timesIdled 1102508 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 34173260 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 94009700955 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 500561663 # Number of Instructions Simulated
-system.cpu0.committedOps 587627818 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.718187 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.718187 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 0.582009 # IPC: Total IPC of All Threads
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system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency::total 18854.165669 # average overall miss latency
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-system.cpu0.dcache.blocked::no_mshrs 772694 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 787427 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.251090 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 34.299404 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 31639371 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 26128725 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 779388 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 763893 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.595148 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 34.204692 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 4324525 # number of writebacks
-system.cpu0.dcache.writebacks::total 4324525 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3632070 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 3632070 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6394266 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 6394266 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4384 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total 4384 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 147311 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 147311 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 10026336 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 10026336 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 10026336 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 10026336 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3482974 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 3482974 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1556060 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1556060 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 753575 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 753575 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 837006 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 837006 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139984 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139984 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195309 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 195309 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 5039034 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 5039034 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 5792609 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 5792609 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31951 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31951 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31485 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31485 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 63436 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 63436 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56753773500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56753773500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38838935578 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38838935578 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19682576500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19682576500 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 98248508406 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 98248508406 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1973900000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1973900000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4567861500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4567861500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4933000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4933000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95592709078 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 95592709078 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115275285578 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 115275285578 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5771319500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5771319500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5597630000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5597630000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11368949500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11368949500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037206 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019082 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019082 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765434 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765434 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.758934 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.758934 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063807 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063807 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.090621 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.090621 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028768 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.028768 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032886 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.032886 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16294.630250 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16294.630250 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 24959.793053 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 24959.793053 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26118.935076 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26118.935076 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 117380.889033 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 117380.889033 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14100.897245 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14100.897245 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23387.869991 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23387.869991 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 4315919 # number of writebacks
+system.cpu0.dcache.writebacks::total 4315919 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3584647 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 3584647 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6264689 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 6264689 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4628 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total 4628 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 139100 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 139100 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 9849336 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 9849336 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 9849336 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 9849336 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3503381 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 3503381 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1533946 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1533946 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733362 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 733362 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 846352 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total 846352 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 134236 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134236 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194661 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 194661 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 5037327 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 5037327 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 5770689 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 5770689 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33238 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66643 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56780867000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56780867000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38418617555 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38418617555 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19943250500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19943250500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1962249500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1962249500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4554969500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4554969500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4736500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4736500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95199484555 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 95199484555 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5997592500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5997592500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5944742000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5944742000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11942334500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11942334500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037149 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037149 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018797 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018797 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756571 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756571 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759164 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.759164 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061757 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061757 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091243 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091243 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028635 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.028635 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032624 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.032624 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18970.443358 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18970.443358 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19900.408534 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19900.408534 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180630.324559 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180630.324559 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177787.200254 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177787.200254 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179219.205183 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179219.205183 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 6358728 # number of replacements
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system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable
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-system.cpu0.icache.demand_mshr_miss_latency::total 70398317173 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles
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-system.cpu0.icache.demand_avg_mshr_miss_latency::total 11070.171021 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11070.171021 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency
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system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3387.843530 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4871 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3657 # Occupied blocks per task id
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40647.608610 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 47986.051890 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56301.577378 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33413.183246 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44085.821155 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80780.391099 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52336.642247 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219344 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469 # average ReadCleanReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875 # average ReadSharedReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721 # average InvalidateReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172628.571876 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 155801.953235 # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170114.005622 # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170114.005622 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171380.524734 # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161120.199068 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.snoop_filter.tot_requests 26498119 # Total number of requests made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13615382 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2337 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.snoop_filter.tot_snoops 550917 # Total number of snoops made to the snoop filter.
-system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 550892 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 25 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu0.toL2Bus.trans_dist::ReadReq 1014324 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 11851775 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 31486 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 31485 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 5956604 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::CleanEvict 10410037 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1088232 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 474368 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351600 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 519661 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1396851 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1324661 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6359280 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5366614 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateReq 842272 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::InvalidateResp 835494 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19118379 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20677259 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 436050 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348581 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 41580269 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407332384 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 648350241 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1616944 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4971488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1062271057 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 6461178 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 33294085 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 0.028312 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.165866 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_filter.tot_requests 27252548 # Total number of requests made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13981170 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2244 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.snoop_filter.tot_snoops 570842 # Total number of snoops made to the snoop filter.
+system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 570828 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu0.toL2Bus.trans_dist::ReadReq 1016473 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 12252394 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 33406 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33405 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 5923375 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::CleanEvict 10861944 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1063583 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 463812 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352945 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 515465 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1384026 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1310731 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6758031 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5399513 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateReq 852147 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::InvalidateResp 844897 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20314687 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20641650 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 432749 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348262 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 42737348 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 432852704 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 646893668 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1600696 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4951880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1086298948 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 6525445 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 34111599 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 0.027918 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.164740 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 32351497 97.17% 97.17% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 942563 2.83% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 25 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 33159285 97.21% 97.21% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 952300 2.79% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 33294085 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 17918792438 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 34111599 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 18295414402 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 208202715 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 218599021 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 9565441520 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 10163463729 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 9227310290 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 9200637125 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 234328206 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 233049222 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 727701378 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 729789968 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 122053066 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 81331643 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6140345 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 85523370 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 55672017 # Number of BTB hits
+system.cpu1.branchPred.lookups 123149965 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 82495484 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5956200 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 86779618 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 56690061 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 65.095677 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16431061 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 166790 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 65.326470 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16440472 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 156518 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 513343 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 513343 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10145 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 80504 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 231589 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 281754 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2191.677847 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 13834.020871 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535 279857 99.33% 99.33% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071 1045 0.37% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607 593 0.21% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143 154 0.05% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679 32 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215 54 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751 12 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 281754 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 256242 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 18411.043076 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 15820.375131 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 14815.596994 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 254819 99.44% 99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 556 0.22% 99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 633 0.25% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 56 0.02% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 78 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 63 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::983040-1.04858e+06 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 256242 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 430767474576 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.581742 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.547950 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 429773436576 99.77% 99.77% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 519356000 0.12% 99.89% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 211618500 0.05% 99.94% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 107822000 0.03% 99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 75775500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 45293000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 13801500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 19976000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 394000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 430767474576 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 80504 88.81% 88.81% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 10145 11.19% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 90649 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 513343 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 527411 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 527411 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10595 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86487 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 240409 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 287002 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 2359.187392 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535 284807 99.24% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071 1123 0.39% 99.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607 785 0.27% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.06% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 287002 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 269681 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 266977 99.00% 99.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 731 0.27% 99.27% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1349 0.50% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 143 0.05% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 295 0.11% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 94 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::851968-917503 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 269681 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 429707115240 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.574612 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.551988 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 428613446240 99.75% 99.75% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3 584261000 0.14% 99.88% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5 233148000 0.05% 99.94% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7 115723000 0.03% 99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9 78401000 0.02% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11 45162000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13 15712000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15 20912500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19 2000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 429707115240 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 86487 89.09% 89.09% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 10595 10.91% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 97082 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527411 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 513343 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 90649 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527411 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97082 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 90649 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 603992 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97082 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 624493 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 90392235 # DTB read hits
-system.cpu1.dtb.read_misses 355030 # DTB read misses
-system.cpu1.dtb.write_hits 74292452 # DTB write hits
-system.cpu1.dtb.write_misses 158313 # DTB write misses
+system.cpu1.dtb.read_hits 91393564 # DTB read hits
+system.cpu1.dtb.read_misses 362569 # DTB read misses
+system.cpu1.dtb.write_hits 75279430 # DTB write hits
+system.cpu1.dtb.write_misses 164842 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 34737 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 572 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 5833 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 36642 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 5827 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 38175 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 90747265 # DTB read accesses
-system.cpu1.dtb.write_accesses 74450765 # DTB write accesses
+system.cpu1.dtb.perms_faults 40054 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 91756133 # DTB read accesses
+system.cpu1.dtb.write_accesses 75444272 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 164684687 # DTB hits
-system.cpu1.dtb.misses 513343 # DTB misses
-system.cpu1.dtb.accesses 165198030 # DTB accesses
+system.cpu1.dtb.hits 166672994 # DTB hits
+system.cpu1.dtb.misses 527411 # DTB misses
+system.cpu1.dtb.accesses 167200405 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 79836 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 79836 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 812 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 57876 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 9466 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 70370 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1202.877647 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 9654.881733 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-65535 70178 99.73% 99.73% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-131071 41 0.06% 99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-196607 131 0.19% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-262143 11 0.02% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-327679 7 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 82282 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 82282 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 773 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59282 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 9946 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 72336 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1446.824541 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535 71995 99.53% 99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071 83 0.11% 99.64% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607 237 0.33% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 70370 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 68154 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 22918.860228 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 20570.604774 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17513.278330 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 67528 99.08% 99.08% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 75 0.11% 99.19% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 455 0.67% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 42 0.06% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 28 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkWaitTime::total 72336 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 70001 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 68717 98.17% 98.17% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 87 0.12% 98.29% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 984 1.41% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 73 0.10% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 83 0.12% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 68154 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 396407660708 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.833666 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.372525 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 65955607768 16.64% 16.64% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 330434317940 83.36% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 16293000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 1234500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 163500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 44000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 396407660708 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 57876 98.62% 98.62% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 812 1.38% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 58688 # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 70001 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 391052327076 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.846616 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.360520 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 60001678208 15.34% 15.34% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 331032470368 84.65% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 15971500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 2073000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 134000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 391052327076 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 59282 98.71% 98.71% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 773 1.29% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 60055 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 79836 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 79836 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82282 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82282 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58688 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58688 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 138524 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 192024896 # ITB inst hits
-system.cpu1.itb.inst_misses 79836 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60055 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60055 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 142337 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 193960223 # ITB inst hits
+system.cpu1.itb.inst_misses 82282 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 44087 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 24498 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 26113 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 203556 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 206259 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 192104732 # ITB inst accesses
-system.cpu1.itb.hits 192024896 # DTB hits
-system.cpu1.itb.misses 79836 # DTB misses
-system.cpu1.itb.accesses 192104732 # DTB accesses
-system.cpu1.numCycles 663967264 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 194042505 # ITB inst accesses
+system.cpu1.itb.hits 193960223 # DTB hits
+system.cpu1.itb.misses 82282 # DTB misses
+system.cpu1.itb.accesses 194042505 # DTB accesses
+system.cpu1.numCycles 680051209 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 80600357 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 540678400 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 122053066 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 72103078 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 547218750 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 13194102 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 1722175 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 292741 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 5852987 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 747163 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 786410 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 191800841 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 1580435 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 27130 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 643817634 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.987423 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.222838 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 76309039 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 545586843 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 123149965 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 73130533 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 567094976 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 12846360 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 1862646 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 285569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 6032568 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 729307 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 772817 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 193732934 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 1488213 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 27982 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 659510102 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.972600 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.218843 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 339738489 52.77% 52.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 118160249 18.35% 71.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 40196713 6.24% 77.37% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 145722183 22.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 352323655 53.42% 53.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 119769188 18.16% 71.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 40581175 6.15% 77.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 146836084 22.26% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 643817634 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.183824 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.814315 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 95925032 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 307565159 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 202328162 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 33349835 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 4649446 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 17381659 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 1984856 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 561624259 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 21210320 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 4649446 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 127605464 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 43917048 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 205458777 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 203595973 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 58590926 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 546425758 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 5335623 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 9251054 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 227617 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 291872 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 27374536 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 10500 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 518347442 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 840457464 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 646223551 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 691924 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 466279930 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 52067506 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 14268129 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 12524757 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 67234415 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 90658674 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 77385188 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 8528695 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 7392702 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 526120257 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 14498185 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 530312729 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 2450487 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 49492350 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 31830796 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 264307 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 643817634 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.823700 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.068099 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 659510102 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.181089 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.802273 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 93216709 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 325116567 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 201438015 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 35171632 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 4567179 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 17405067 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 1892222 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 567399835 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 20537774 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 4567179 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 125466899 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 47033211 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 215743407 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 203915656 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 62783750 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 552356795 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 5241539 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 9909237 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 240791 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 292344 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 29944703 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 11393 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 524936389 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 854810992 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 653637843 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 615050 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 473696954 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 51239429 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 15119385 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 13351935 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 70628253 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 91219643 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 78311402 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 8799360 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 7480777 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 531265202 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 15384643 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 536975559 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 2409415 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 48765571 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 31310459 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 261406 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 659510102 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.814204 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.064087 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 353942401 54.98% 54.98% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 122398683 19.01% 73.99% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 101611501 15.78% 89.77% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 58772797 9.13% 98.90% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 7088607 1.10% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 3645 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 364889522 55.33% 55.33% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 126119203 19.12% 74.45% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 101926801 15.45% 89.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 59299384 8.99% 98.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 7271358 1.10% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 3834 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 643817634 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 659510102 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 53425749 43.94% 43.94% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 46790 0.04% 43.97% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 9685 0.01% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 19 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.98% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 32795787 26.97% 70.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 35319606 29.05% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 53688772 43.65% 43.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 42849 0.03% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 9758 0.01% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 12 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 33350405 27.12% 70.81% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 35903096 29.19% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 360430820 67.97% 67.97% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1171247 0.22% 68.19% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 68672 0.01% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.20% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 45220 0.01% 68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 93137728 17.56% 85.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 75458910 14.23% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 365127801 68.00% 68.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1207443 0.22% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 64356 0.01% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 5 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 40592 0.01% 68.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.24% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 94109837 17.53% 85.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 76425394 14.23% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 530312729 # Type of FU issued
-system.cpu1.iq.rate 0.798703 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 121597636 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.229294 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1827371450 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 589808611 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 515064806 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1119763 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 442884 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 412109 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 651211996 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 698285 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 2417067 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 536975559 # Type of FU issued
+system.cpu1.iq.rate 0.789610 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 122994892 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.229051 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 1857852304 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 595160433 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 521544916 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1013221 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 400944 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 372548 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 659338375 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 631992 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 2462766 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 11379314 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 14413 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 141714 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 5438356 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 11273364 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 14330 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 146929 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 5363484 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 2432171 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 3747564 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 2532880 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 4046276 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 4649446 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 5786949 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 2152685 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 540731877 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 4567179 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 5912411 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 2185508 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 546765447 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 90658674 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 77385188 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 12325629 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 58000 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2039251 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 141714 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 1867697 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2587615 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 4455312 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 523333067 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 90385914 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 6476972 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 91219643 # Number of dispatched load instructions
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+system.cpu1.iew.iewIQFullEvents 62909 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2062449 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 146929 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 1850208 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2506307 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 4356515 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 530131647 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 91388835 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 6328626 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 113435 # number of nop insts executed
-system.cpu1.iew.exec_refs 164677509 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 98047931 # Number of branches executed
-system.cpu1.iew.exec_stores 74291595 # Number of stores executed
-system.cpu1.iew.exec_rate 0.788191 # Inst execution rate
-system.cpu1.iew.wb_sent 516143321 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 515476915 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 249234254 # num instructions producing a value
-system.cpu1.iew.wb_consumers 407965513 # num instructions consuming a value
+system.cpu1.iew.exec_nop 115602 # number of nop insts executed
+system.cpu1.iew.exec_refs 166669354 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 99325061 # Number of branches executed
+system.cpu1.iew.exec_stores 75280519 # Number of stores executed
+system.cpu1.iew.exec_rate 0.779547 # Inst execution rate
+system.cpu1.iew.wb_sent 522591798 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 521917464 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 252132377 # num instructions producing a value
+system.cpu1.iew.wb_consumers 413034686 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.776359 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.610920 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.767468 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.610439 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 43327267 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 14233878 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4192740 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 635627275 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.772664 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.570415 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 42738935 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 15123237 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4100199 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 651431241 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.764293 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.565341 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 419865335 66.06% 66.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 112371204 17.68% 83.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 47717309 7.51% 91.24% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 15913228 2.50% 93.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 11392527 1.79% 95.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 7668933 1.21% 96.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5369975 0.84% 97.59% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3184156 0.50% 98.09% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 12144608 1.91% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 432003686 66.32% 66.32% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 115523895 17.73% 84.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 47761812 7.33% 91.38% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 15857432 2.43% 93.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 11422302 1.75% 95.57% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 7738049 1.19% 96.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5451213 0.84% 97.59% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3205095 0.49% 98.09% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 12467757 1.91% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 635627275 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 416740074 # Number of instructions committed
-system.cpu1.commit.committedOps 491126085 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 651431241 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 422487941 # Number of instructions committed
+system.cpu1.commit.committedOps 497884267 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 151226191 # Number of memory references committed
-system.cpu1.commit.loads 79279359 # Number of loads committed
-system.cpu1.commit.membars 3502305 # Number of memory barriers committed
-system.cpu1.commit.branches 92953281 # Number of branches committed
-system.cpu1.commit.fp_insts 403468 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 451237639 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 12195676 # Number of function calls committed.
+system.cpu1.commit.refs 152894196 # Number of memory references committed
+system.cpu1.commit.loads 79946278 # Number of loads committed
+system.cpu1.commit.membars 3616952 # Number of memory barriers committed
+system.cpu1.commit.branches 94285217 # Number of branches committed
+system.cpu1.commit.fp_insts 364520 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 457066504 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 12254498 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 338863536 69.00% 69.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 941904 0.19% 69.19% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 54586 0.01% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.20% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 39826 0.01% 69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.21% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 79279359 16.14% 85.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 71946832 14.65% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 343931170 69.08% 69.08% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 972359 0.20% 69.27% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 50623 0.01% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.28% # Class of committed instruction
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+system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.28% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.28% # Class of committed instruction
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+system.cpu1.commit.op_class_0::SimdFloatMisc 35877 0.01% 69.29% # Class of committed instruction
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system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 491126085 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 12144608 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1154417922 # The number of ROB reads
-system.cpu1.rob.rob_writes 1077060232 # The number of ROB writes
-system.cpu1.timesIdled 910594 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 20149630 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 94205821171 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 416740074 # Number of Instructions Simulated
-system.cpu1.committedOps 491126085 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.593241 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.593241 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.627652 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.627652 # IPC: Total IPC of All Threads
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-system.cpu1.int_regfile_writes 366638237 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 681038 # number of floating regfile reads
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-system.cpu1.cc_regfile_writes 111901561 # number of cc regfile writes
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-system.cpu1.dcache.tags.sampled_refs 5008789 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 28.173755 # Average number of references to valid blocks.
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+system.cpu1.idleCycles 20541107 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu1.committedOps 497884267 # Number of Ops (including micro ops) Simulated
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+system.cpu1.cpi_total 1.609635 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.621259 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.621259 # IPC: Total IPC of All Threads
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+system.cpu1.dcache.tags.avg_refs 27.544805 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
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system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu1.dcache.ReadReq_hits::total 73808968 # number of ReadReq hits
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-system.cpu1.dcache.SoftPFReq_hits::total 166300 # number of SoftPFReq hits
-system.cpu1.dcache.WriteLineReq_hits::cpu1.data 49799 # number of WriteLineReq hits
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-system.cpu1.dcache.LoadLockedReq_hits::total 1689842 # number of LoadLockedReq hits
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-system.cpu1.dcache.SoftPFReq_misses::total 617645 # number of SoftPFReq misses
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23934.149375 # average StoreCondReq miss latency
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174 # average WriteReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654 # average WriteLineReq miss latency
+system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654 # average WriteLineReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15504.129815 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15504.129815 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23849.275437 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23849.275437 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18055.362007 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18055.362007 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17203.374120 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 17203.374120 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 4151520 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 21118604 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 339495 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 658226 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.228516 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 32.084123 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 4190229 # number of cycles access was blocked
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+system.cpu1.dcache.blocked::no_mshrs 332306 # number of cycles access was blocked
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+system.cpu1.dcache.avg_blocked_cycles::no_targets 33.375567 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3259663 # number of writebacks
-system.cpu1.dcache.writebacks::total 3259663 # number of writebacks
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-system.cpu1.dcache.WriteLineReq_mshr_hits::total 3866 # number of WriteLineReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 125871 # number of LoadLockedReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 8312424 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 2896107 # number of ReadReq MSHR misses
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-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 617580 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 617580 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 413172 # number of WriteLineReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 117237 # number of LoadLockedReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::total 189777 # number of StoreCondReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1682703500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787785 # mshr miss rate for SoftPFReq accesses
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-system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.885046 # mshr miss rate for WriteLineReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.060652 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.overall_mshr_miss_rate::total 0.031828 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14492.690187 # average ReadReq mshr miss latency
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-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22959.909647 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22959.909647 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 37337.151070 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 37337.151070 # average WriteLineReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14353.007156 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14353.007156 # average LoadLockedReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22934.575844 # average StoreCondReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198 # average WriteLineReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16688.461382 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16688.461382 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17499.302791 # average overall mshr miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496937.125000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45685.429720 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45685.429720 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29329.808020 # average ReadCleanReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31064.411200 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31064.411200 # average ReadSharedReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 53610.629337 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 53610.629337 # average InvalidateReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32513.032004 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 35898.239772 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35401.239558 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29329.808020 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 34006.016519 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55678.903673 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38916.070629 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.236233 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 46295.659092 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64713.594163 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32826.799579 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32826.799579 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18485.698746 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 802083 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 802083 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048 # average ReadCleanReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508 # average ReadSharedReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312 # average InvalidateReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104049.809552 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 104257.725228 # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 119981.453075 # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 119981.453075 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 112211.973994 # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 112274.992890 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.snoop_filter.tot_requests 21930537 # Total number of requests made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11284587 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1296 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.snoop_filter.tot_snoops 520648 # Total number of snoops made to the snoop filter.
-system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 520636 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 12 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu1.toL2Bus.trans_dist::ReadReq 828450 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 10092423 # Transaction distribution
+system.cpu1.toL2Bus.snoop_filter.tot_requests 21572446 # Total number of requests made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11121796 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.snoop_filter.tot_snoops 524506 # Total number of snoops made to the snoop filter.
+system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 524489 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 17 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu1.toL2Bus.trans_dist::ReadReq 847854 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9869269 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 7171 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 7171 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 4200793 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::CleanEvict 9135588 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 838070 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 423377 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345989 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 462829 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 66 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1138657 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1069017 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5544744 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4688366 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateReq 419379 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::InvalidateResp 411859 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16633313 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16198816 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385145 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1121131 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 34338405 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 354864624 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 515112392 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1411752 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4066000 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 875454768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 5438478 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 27571945 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 0.031057 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.173474 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::WriteReq 4882 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 4882 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 4416651 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::CleanEvict 8880510 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 907695 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 421769 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350236 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 471619 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1189775 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1122660 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5203338 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4763767 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateReq 409409 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::InvalidateResp 401778 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15609171 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16649345 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 393406 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1143795 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 33795717 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333013936 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 531452177 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1432064 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4124520 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 870022697 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5627139 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 27397107 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 0.032027 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.176075 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 26715663 96.89% 96.89% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 856270 3.11% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 12 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 26519684 96.80% 96.80% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 877406 3.20% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 17 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 27571945 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 14479823475 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 27397107 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 14402314458 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 180399406 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 173479331 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8321735869 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7809268085 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7455510168 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7687735490 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 208987874 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 214700392 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 613445865 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 628828296 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40368 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40368 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40404 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40404 # Transaction distribution
system.iobus.trans_dist::WriteReq 136681 # Transaction distribution
system.iobus.trans_dist::WriteResp 136681 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231192 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231192 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354098 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 354170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338784 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338784 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496803 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7497091 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 565777885 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 566086533 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 147888000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
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+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222008 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159068 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246626 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.332404 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.332404 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73616.390294 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73553.635707 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73586.071387 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76461.516819 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.098585 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.084354 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168609.821410 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139760.614749 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 163870.610859 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137909.099139 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134512.466714 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 156548.463338 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154627.836374 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154441.302124 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 86074.662954 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 131897.898098 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153111.943243 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 102979.361316 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 143811.944666 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74922.726391 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132599.588326 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153294.552702 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88074.559607 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 144978.309426 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153875.457674 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153866.490599 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 94736.584494 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 136559.706586 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81318.507820 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 137433.631498 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 60136 # Transaction distribution
-system.membus.trans_dist::ReadResp 965246 # Transaction distribution
-system.membus.trans_dist::WriteReq 38656 # Transaction distribution
-system.membus.trans_dist::WriteResp 38656 # Transaction distribution
-system.membus.trans_dist::Writeback 1296915 # Transaction distribution
-system.membus.trans_dist::CleanEvict 243951 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 452760 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 304384 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 121976 # Transaction distribution
+system.membus.trans_dist::ReadReq 59756 # Transaction distribution
+system.membus.trans_dist::ReadResp 1037606 # Transaction distribution
+system.membus.trans_dist::WriteReq 38287 # Transaction distribution
+system.membus.trans_dist::WriteResp 38287 # Transaction distribution
+system.membus.trans_dist::Writeback 1371305 # Transaction distribution
+system.membus.trans_dist::CleanEvict 262648 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 440849 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 306045 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 117782 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
-system.membus.trans_dist::ReadExReq 662340 # Transaction distribution
-system.membus.trans_dist::ReadExResp 641281 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 905110 # Transaction distribution
+system.membus.trans_dist::ReadExReq 681386 # Transaction distribution
+system.membus.trans_dist::ReadExResp 660425 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 977850 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26816 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5450054 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5599774 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342030 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 342030 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5941804 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5711814 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5860036 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343033 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 343033 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6203069 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53632 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174888448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 175098585 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7250496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7250496 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 182349081 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 659296 # Total snoops (count)
-system.membus.snoop_fanout::samples 4073524 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 185527680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 185734821 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7281536 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 193016357 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 652692 # Total snoops (count)
+system.membus.snoop_fanout::samples 4246933 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4073524 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4246933 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4073524 # Request fanout histogram
-system.membus.reqLayer0.occupancy 98143499 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 4246933 # Request fanout histogram
+system.membus.reqLayer0.occupancy 98658999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22747469 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21380469 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9016528809 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9518454911 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 8432717951 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 8904498116 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 230475062 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 230513312 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 11519638 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 5862055 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 2048796 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 167370 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 156134 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 11236 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 60138 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4755206 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38656 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38656 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 3790142 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 1500041 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 506577 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 316392 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 822969 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 115 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 115 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1127077 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1127077 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 4702306 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 11772030 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 5986527 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2060183 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 193514 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 180675 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 12839 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 59758 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4863251 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38287 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38287 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 3950228 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 1568757 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 493482 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 318513 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 811995 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1145198 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1145198 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 4810734 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9146865 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6326733 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15473598 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 285949105 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 180962856 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 466911961 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 3420267 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 13372960 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.331842 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.472656 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9122705 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6709100 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15831805 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283955252 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196820081 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 480775333 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 3520564 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 13735314 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.326662 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.470981 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 8946480 66.90% 66.90% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 4415244 33.02% 99.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 11236 0.08% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 9261350 67.43% 67.43% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 4461125 32.48% 99.91% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 12839 0.09% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 13372960 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8776402150 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 13735314 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 9000721880 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2601544 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2650288 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 5338662327 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 5320683808 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3896618177 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4098533956 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 14407 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 13032 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 7094 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 5368 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000015] Console: colour dummy device 80x25\r
-[ 0.000017] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000018] pid_max: default: 32768 minimum: 301\r
-[ 0.000026] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000111] hw perfevents: no hardware support available\r
-[ 0.060027] CPU1: Booted secondary processor\r
-[ 1.080050] CPU2: failed to come online\r
-[ 2.100095] CPU3: failed to come online\r
-[ 2.100098] Brought up 2 CPUs\r
-[ 2.100098] SMP: Total of 2 processors activated.\r
-[ 2.100137] devtmpfs: initialized\r
-[ 2.100450] atomic64_test: passed\r
-[ 2.100480] regulator-dummy: no parameters\r
-[ 2.100708] NET: Registered protocol family 16\r
-[ 2.100794] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.100801] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.101261] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.101264] Serial: AMBA PL011 UART driver\r
-[ 2.101390] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.101415] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.101971] console [ttyAMA0] enabled\r
-[ 2.102037] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.102065] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.102093] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.102119] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.130210] 3V3: 3300 mV \r
-[ 2.130252] vgaarb: loaded\r
-[ 2.130305] SCSI subsystem initialized\r
-[ 2.130337] libata version 3.00 loaded.\r
-[ 2.130399] usbcore: registered new interface driver usbfs\r
-[ 2.130418] usbcore: registered new interface driver hub\r
-[ 2.130440] usbcore: registered new device driver usb\r
-[ 2.130474] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.130483] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.130504] PTP clock support registered\r
-[ 2.130625] Switched to clocksource arch_sys_counter\r
-[ 2.131645] NET: Registered protocol family 2\r
-[ 2.131709] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.131723] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.131738] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.131760] TCP: reno registered\r
-[ 2.131766] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.131777] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.131803] NET: Registered protocol family 1\r
-[ 2.131837] RPC: Registered named UNIX socket transport module.\r
-[ 2.131847] RPC: Registered udp transport module.\r
-[ 2.131855] RPC: Registered tcp transport module.\r
-[ 2.131863] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.131875] PCI: CLS 0 bytes, default 64\r
-[ 2.132032] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.132111] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.133524] fuse init (API version 7.23)\r
-[ 2.133604] msgmni has been set to 469\r
-[ 2.133679] io scheduler noop registered\r
-[ 2.133713] io scheduler cfq registered (default)\r
-[ 2.133988] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.134000] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.134011] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.134023] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.134032] pci_bus 0000:00: scanning bus\r
-[ 2.134042] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.134054] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.134067] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.134094] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.134105] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.134115] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.134125] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.134135] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.134145] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.134156] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.134182] pci_bus 0000:00: fixups for bus\r
-[ 2.134190] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.134201] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.134217] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.134225] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.134234] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.134242] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.134252] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.134264] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.134276] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.134289] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.134299] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.134310] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.134321] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.134331] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.134762] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.134944] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.134953] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.134973] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.135150] scsi0 : ata_piix\r
-[ 2.135206] scsi1 : ata_piix\r
-[ 2.135226] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.135238] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.135311] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.135322] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.135335] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.135345] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.280657] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.280666] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.280690] ata1.00: configured for UDMA/33\r
-[ 2.280728] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.280821] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.280854] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.280863] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.280878] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.280929] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.280990] sda: sda1\r
-[ 2.281073] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.400906] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.400919] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.400938] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.400948] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.400966] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.400977] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.401027] usbcore: registered new interface driver usb-storage\r
-[ 2.401068] mousedev: PS/2 mouse device common for all mice\r
-[ 2.401175] usbcore: registered new interface driver usbhid\r
-[ 2.401185] usbhid: USB HID core driver\r
-[ 2.401212] TCP: cubic registered\r
-[ 2.401219] NET: Registered protocol family 17\r
-\0[ 2.401455] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.401484] devtmpfs: mounted\r
-[ 2.401519] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000018] Console: colour dummy device 80x25\r
+[ 0.000020] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000022] pid_max: default: 32768 minimum: 301\r
+[ 0.000030] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000031] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000136] hw perfevents: no hardware support available\r
+[ 0.060032] CPU1: Booted secondary processor\r
+[ 1.080057] CPU2: failed to come online\r
+[ 2.100108] CPU3: failed to come online\r
+[ 2.100110] Brought up 2 CPUs\r
+[ 2.100111] SMP: Total of 2 processors activated.\r
+[ 2.100156] devtmpfs: initialized\r
+[ 2.100483] atomic64_test: passed\r
+[ 2.100516] regulator-dummy: no parameters\r
+[ 2.100758] NET: Registered protocol family 16\r
+[ 2.100850] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.100857] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.101451] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.101454] Serial: AMBA PL011 UART driver\r
+[ 2.101592] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.101619] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.102176] console [ttyAMA0] enabled\r
+[ 2.102288] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.102335] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.102382] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.102428] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140243] 3V3: 3300 mV \r
+[ 2.140289] vgaarb: loaded\r
+[ 2.140336] SCSI subsystem initialized\r
+[ 2.140372] libata version 3.00 loaded.\r
+[ 2.140431] usbcore: registered new interface driver usbfs\r
+[ 2.140450] usbcore: registered new interface driver hub\r
+[ 2.140473] usbcore: registered new device driver usb\r
+[ 2.140506] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140516] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140536] PTP clock support registered\r
+[ 2.140665] Switched to clocksource arch_sys_counter\r
+[ 2.141709] NET: Registered protocol family 2\r
+[ 2.141778] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.141793] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.141808] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.141830] TCP: reno registered\r
+[ 2.141837] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141848] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.141877] NET: Registered protocol family 1\r
+[ 2.141911] RPC: Registered named UNIX socket transport module.\r
+[ 2.141921] RPC: Registered udp transport module.\r
+[ 2.141929] RPC: Registered tcp transport module.\r
+[ 2.141937] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.141949] PCI: CLS 0 bytes, default 64\r
+[ 2.142112] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.142195] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.143645] fuse init (API version 7.23)\r
+[ 2.143728] msgmni has been set to 469\r
+[ 2.143809] io scheduler noop registered\r
+[ 2.143844] io scheduler cfq registered (default)\r
+[ 2.144150] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.144162] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.144173] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.144185] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.144194] pci_bus 0000:00: scanning bus\r
+[ 2.144204] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.144216] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.144230] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.144257] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.144269] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.144279] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.144289] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.144299] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.144309] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.144319] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.144346] pci_bus 0000:00: fixups for bus\r
+[ 2.144354] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.144365] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.144382] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.144390] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.144400] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.144408] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.144418] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.144430] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.144443] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.144455] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.144466] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.144477] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.144487] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.144498] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.144950] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.145140] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.145150] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.145172] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.145357] scsi0 : ata_piix\r
+[ 2.145416] scsi1 : ata_piix\r
+[ 2.145436] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.145448] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.145524] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.145536] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.145549] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.145560] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.290700] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.290710] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.290734] ata1.00: configured for UDMA/33\r
+[ 2.290779] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.290877] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.290910] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.290919] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.290935] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.290988] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.291054] sda: sda1\r
+[ 2.291141] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.410945] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.410958] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.410975] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.410985] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.411002] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.411014] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.411063] usbcore: registered new interface driver usb-storage\r
+[ 2.411110] mousedev: PS/2 mouse device common for all mice\r
+[ 2.411217] usbcore: registered new interface driver usbhid\r
+[ 2.411226] usbhid: USB HID core driver\r
+[ 2.411251] TCP: cubic registered\r
+[ 2.411258] NET: Registered protocol family 17\r
+\0[ 2.411564] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.411604] devtmpfs: mounted\r
+[ 2.411643] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.437521] udevd[609]: starting version 182\r
+[ 2.447767] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.512528] random: dd urandom read with 18 bits of entropy available\r
+[ 2.522729] random: dd urandom read with 18 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.620850] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.630897] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 01:57:07
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 02:15:31
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3 -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-o3
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51562169701000 because m5_exit instruction encountered
+Exiting @ tick 51331518104000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 51.291801 # Number of seconds simulated
-sim_ticks 51291801227000 # Number of ticks simulated
-final_tick 51291801227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.331518 # Number of seconds simulated
+sim_ticks 51331518104000 # Number of ticks simulated
+final_tick 51331518104000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 104106 # Simulator instruction rate (inst/s)
-host_op_rate 122333 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6261768882 # Simulator tick rate (ticks/s)
-host_mem_usage 729608 # Number of bytes of host memory used
-host_seconds 8191.26 # Real time elapsed on the host
-sim_insts 852762944 # Number of instructions simulated
-sim_ops 1002063356 # Number of ops (including micro ops) simulated
+host_inst_rate 87398 # Simulator instruction rate (inst/s)
+host_op_rate 102692 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5304439586 # Simulator tick rate (ticks/s)
+host_mem_usage 679424 # Number of bytes of host memory used
+host_seconds 9677.09 # Real time elapsed on the host
+sim_insts 845761974 # Number of instructions simulated
+sim_ops 993759083 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 238464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 234560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 5768352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 75242504 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 407680 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81891560 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 5768352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 5768352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 69965824 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.dtb.walker 205120 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 196736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 5673888 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 72271240 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 441728 # Number of bytes read from this memory
+system.physmem.bytes_read::total 78788712 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 5673888 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 5673888 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 67330112 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 69986404 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 3726 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3665 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 106083 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1175677 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6370 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1295521 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1093216 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 67350692 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 3205 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 3074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 104607 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 1129251 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6902 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1247039 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1052033 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1095789 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 4649 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 4573 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 112461 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1466950 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 7948 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1596582 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 112461 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 112461 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1364074 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1054606 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 3996 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 3833 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 110534 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1407931 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8605 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1534899 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 110534 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 110534 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1311672 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1364475 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1364074 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 4649 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 4573 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 112461 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1467351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 7948 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2961057 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 1295521 # Number of read requests accepted
-system.physmem.writeReqs 1095789 # Number of write requests accepted
-system.physmem.readBursts 1295521 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1095789 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 82863680 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 49664 # Total number of bytes read from write queue
-system.physmem.bytesWritten 69985152 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 81891560 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 69986404 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 776 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 141837 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 78118 # Per bank write bursts
-system.physmem.perBankRdBursts::1 81473 # Per bank write bursts
-system.physmem.perBankRdBursts::2 82762 # Per bank write bursts
-system.physmem.perBankRdBursts::3 80112 # Per bank write bursts
-system.physmem.perBankRdBursts::4 77452 # Per bank write bursts
-system.physmem.perBankRdBursts::5 84131 # Per bank write bursts
-system.physmem.perBankRdBursts::6 77443 # Per bank write bursts
-system.physmem.perBankRdBursts::7 77113 # Per bank write bursts
-system.physmem.perBankRdBursts::8 74240 # Per bank write bursts
-system.physmem.perBankRdBursts::9 104872 # Per bank write bursts
-system.physmem.perBankRdBursts::10 79788 # Per bank write bursts
-system.physmem.perBankRdBursts::11 80502 # Per bank write bursts
-system.physmem.perBankRdBursts::12 82162 # Per bank write bursts
-system.physmem.perBankRdBursts::13 82091 # Per bank write bursts
-system.physmem.perBankRdBursts::14 76266 # Per bank write bursts
-system.physmem.perBankRdBursts::15 76220 # Per bank write bursts
-system.physmem.perBankWrBursts::0 65460 # Per bank write bursts
-system.physmem.perBankWrBursts::1 68510 # Per bank write bursts
-system.physmem.perBankWrBursts::2 70351 # Per bank write bursts
-system.physmem.perBankWrBursts::3 69772 # Per bank write bursts
-system.physmem.perBankWrBursts::4 67735 # Per bank write bursts
-system.physmem.perBankWrBursts::5 71090 # Per bank write bursts
-system.physmem.perBankWrBursts::6 66311 # Per bank write bursts
-system.physmem.perBankWrBursts::7 67773 # Per bank write bursts
-system.physmem.perBankWrBursts::8 64800 # Per bank write bursts
-system.physmem.perBankWrBursts::9 72411 # Per bank write bursts
-system.physmem.perBankWrBursts::10 67462 # Per bank write bursts
-system.physmem.perBankWrBursts::11 69064 # Per bank write bursts
-system.physmem.perBankWrBursts::12 70238 # Per bank write bursts
-system.physmem.perBankWrBursts::13 69848 # Per bank write bursts
-system.physmem.perBankWrBursts::14 66451 # Per bank write bursts
-system.physmem.perBankWrBursts::15 66242 # Per bank write bursts
+system.physmem.bw_write::total 1312073 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1311672 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 3996 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 3833 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 110534 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1408332 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8605 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2846972 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 1247039 # Number of read requests accepted
+system.physmem.writeReqs 1054606 # Number of write requests accepted
+system.physmem.readBursts 1247039 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 1054606 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 79759552 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 50944 # Total number of bytes read from write queue
+system.physmem.bytesWritten 67349568 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 78788712 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 67350692 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 796 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 141264 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 74145 # Per bank write bursts
+system.physmem.perBankRdBursts::1 81438 # Per bank write bursts
+system.physmem.perBankRdBursts::2 79571 # Per bank write bursts
+system.physmem.perBankRdBursts::3 74681 # Per bank write bursts
+system.physmem.perBankRdBursts::4 75850 # Per bank write bursts
+system.physmem.perBankRdBursts::5 80076 # Per bank write bursts
+system.physmem.perBankRdBursts::6 74234 # Per bank write bursts
+system.physmem.perBankRdBursts::7 74770 # Per bank write bursts
+system.physmem.perBankRdBursts::8 71012 # Per bank write bursts
+system.physmem.perBankRdBursts::9 102127 # Per bank write bursts
+system.physmem.perBankRdBursts::10 78424 # Per bank write bursts
+system.physmem.perBankRdBursts::11 78933 # Per bank write bursts
+system.physmem.perBankRdBursts::12 75355 # Per bank write bursts
+system.physmem.perBankRdBursts::13 78384 # Per bank write bursts
+system.physmem.perBankRdBursts::14 73014 # Per bank write bursts
+system.physmem.perBankRdBursts::15 74229 # Per bank write bursts
+system.physmem.perBankWrBursts::0 61794 # Per bank write bursts
+system.physmem.perBankWrBursts::1 67391 # Per bank write bursts
+system.physmem.perBankWrBursts::2 68136 # Per bank write bursts
+system.physmem.perBankWrBursts::3 64875 # Per bank write bursts
+system.physmem.perBankWrBursts::4 65862 # Per bank write bursts
+system.physmem.perBankWrBursts::5 67755 # Per bank write bursts
+system.physmem.perBankWrBursts::6 63835 # Per bank write bursts
+system.physmem.perBankWrBursts::7 65687 # Per bank write bursts
+system.physmem.perBankWrBursts::8 61691 # Per bank write bursts
+system.physmem.perBankWrBursts::9 69909 # Per bank write bursts
+system.physmem.perBankWrBursts::10 65651 # Per bank write bursts
+system.physmem.perBankWrBursts::11 67939 # Per bank write bursts
+system.physmem.perBankWrBursts::12 65356 # Per bank write bursts
+system.physmem.perBankWrBursts::13 67578 # Per bank write bursts
+system.physmem.perBankWrBursts::14 64108 # Per bank write bursts
+system.physmem.perBankWrBursts::15 64770 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 28 # Number of times write queue was full causing retry
-system.physmem.totGap 51291799925500 # Total gap between requests
+system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
+system.physmem.totGap 51331516800500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 21272 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 1274236 # Read request sizes (log2)
+system.physmem.readPktSize::6 1225754 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 1 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1093216 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 662611 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 344322 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 153233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 129247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 652 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 521 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 1152 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 692 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 296 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 333 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 199 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 143 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 127 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 120 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 105 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 1052033 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 635607 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 328525 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 149631 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 126665 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 692 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 573 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 581 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 1305 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 789 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 347 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 405 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 175 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 172 # What read queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 302.648619 # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::512-639 19234 3.81% 81.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12076 2.39% 83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 11328 2.24% 86.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 8283 1.64% 87.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 62379 12.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 505036 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 62413 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 20.744284 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 264.086390 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.totMemAccLat 57572001434 # Total ticks spent from burst creation until serviced by the DRAM
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-system.physmem.avgQLat 25715.90 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::total 59915 # Writes before turning the bus around for reads
+system.physmem.totQLat 31917471814 # Total ticks spent queuing
+system.physmem.totMemAccLat 55284528064 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6231215000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 25610.95 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44465.90 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.62 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.60 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 1.36 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 44360.95 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.34 # Average write queue length when enqueuing
-system.physmem.readRowHits 1061078 # Number of row buffer hits during reads
-system.physmem.writeRowHits 822147 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.18 # Row buffer hit rate for writes
-system.physmem.avgGap 21449247.45 # Average gap between requests
-system.physmem.pageHitRate 78.85 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1917609120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1046314500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 4981072200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3544572960 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1242137154015 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29685484530000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34289242115835 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.513169 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49384250074028 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1712745840000 # Time in different power states
+system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.76 # Average write queue length when enqueuing
+system.physmem.readRowHits 1024444 # Number of row buffer hits during reads
+system.physmem.writeRowHits 797630 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes
+system.physmem.avgGap 22302099.93 # Average gap between requests
+system.physmem.pageHitRate 79.27 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1809644760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 987405375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4795167000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3404170800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1235982378375 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29714714061000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34314417854910 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.486362 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49432942986454 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1714072100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 194804679972 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 184500143546 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1900463040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1036959000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 5117892000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3541423680 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3350130863040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1242496599435 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29685169227000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34289393427195 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.516119 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49383714226365 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1712745840000 # Time in different power states
+system.physmem_1.actEnergy 1792725480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 978173625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4925481600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 3414972960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3352725027600 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1238461921980 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29712539014500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34314837317745 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.494534 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49429295042072 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1714072100000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 195340926635 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 188150328928 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory
system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 225483777 # Number of BP lookups
-system.cpu.branchPred.condPredicted 150731207 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 12226483 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 159238670 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 104065621 # Number of BTB hits
+system.cpu.branchPred.lookups 223690256 # Number of BP lookups
+system.cpu.branchPred.condPredicted 149470273 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 12181359 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 157723580 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 103180902 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 65.351978 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 30986634 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 344493 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 65.418818 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 30739943 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 342702 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 951545 # Table walker walks requested
-system.cpu.dtb.walker.walksLong 951545 # Table walker walks initiated with long descriptors
-system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16343 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksLongTerminationLevel::Level3 155686 # Level at which table walker walks with long descriptors terminate
-system.cpu.dtb.walker.walksSquashedBefore 435595 # Table walks squashed before starting
-system.cpu.dtb.walker.walkWaitTime::samples 515950 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::mean 2268.523113 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::stdev 15037.920153 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0-65535 512394 99.31% 99.31% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::65536-131071 1973 0.38% 99.69% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::131072-196607 1076 0.21% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::196608-262143 204 0.04% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::262144-327679 151 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::393216-458751 58 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::524288-589823 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 515950 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 484012 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 23030.337058 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 17887.395943 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 21586.118666 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-65535 472338 97.59% 97.59% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::65536-131071 7777 1.61% 99.19% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::131072-196607 2811 0.58% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::196608-262143 207 0.04% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::262144-327679 566 0.12% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::327680-393215 131 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::393216-458751 146 0.03% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::458752-524287 21 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 484012 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walksPending::samples 787280100836 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::mean 0.726034 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::stdev 0.521586 # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::0-1 785046223336 99.72% 99.72% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::2-3 1194986000 0.15% 99.87% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::4-5 471189500 0.06% 99.93% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::6-7 205721500 0.03% 99.95% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::8-9 152825500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::10-11 122394500 0.02% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::12-13 28887000 0.00% 99.99% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::14-15 55269000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::16-17 2572500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::18-19 32000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.dtb.walker.walksPending::total 787280100836 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 155687 90.50% 90.50% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::2M 16343 9.50% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 172030 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 951545 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walks 934978 # Table walker walks requested
+system.cpu.dtb.walker.walksLong 934978 # Table walker walks initiated with long descriptors
+system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15042 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154863 # Level at which table walker walks with long descriptors terminate
+system.cpu.dtb.walker.walksSquashedBefore 425141 # Table walks squashed before starting
+system.cpu.dtb.walker.walkWaitTime::samples 509837 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::mean 2238.847906 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::stdev 14877.677912 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0-65535 506434 99.33% 99.33% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::65536-131071 1917 0.38% 99.71% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::131072-196607 986 0.19% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::196608-262143 211 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::262144-327679 153 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::327680-393215 25 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::393216-458751 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::458752-524287 51 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::655360-720895 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 509837 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 473320 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 22997.265064 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 18038.108072 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 20298.605153 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-65535 462482 97.71% 97.71% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-131071 7672 1.62% 99.33% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::131072-196607 2249 0.48% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::196608-262143 179 0.04% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::262144-327679 532 0.11% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::327680-393215 62 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::393216-458751 112 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::458752-524287 23 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 473320 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walksPending::samples 784047304876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::mean 0.724244 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::stdev 0.519446 # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::0-1 781857637876 99.72% 99.72% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::2-3 1171824000 0.15% 99.87% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::4-5 476098500 0.06% 99.93% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::6-7 199009000 0.03% 99.96% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::8-9 143211000 0.02% 99.97% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::10-11 120940000 0.02% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::12-13 26747000 0.00% 99.99% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::14-15 49238000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::16-17 2599500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.dtb.walker.walksPending::total 784047304876 # Table walker pending requests distribution
+system.cpu.dtb.walker.walkPageSizes::4K 154864 91.15% 91.15% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::2M 15042 8.85% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 169906 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 934978 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 951545 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 172030 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 934978 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169906 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 172030 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 1123575 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169906 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 1104884 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 170217039 # DTB read hits
-system.cpu.dtb.read_misses 674912 # DTB read misses
-system.cpu.dtb.write_hits 148367148 # DTB write hits
-system.cpu.dtb.write_misses 276633 # DTB write misses
+system.cpu.dtb.read_hits 168982671 # DTB read hits
+system.cpu.dtb.read_misses 669792 # DTB read misses
+system.cpu.dtb.write_hits 147065605 # DTB write hits
+system.cpu.dtb.write_misses 265186 # DTB write misses
system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 72532 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 10694 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID
+system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID
+system.cpu.dtb.flush_entries 71824 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 98 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 9312 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 70020 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 170891951 # DTB read accesses
-system.cpu.dtb.write_accesses 148643781 # DTB write accesses
+system.cpu.dtb.perms_faults 69742 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 169652463 # DTB read accesses
+system.cpu.dtb.write_accesses 147330791 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 318584187 # DTB hits
-system.cpu.dtb.misses 951545 # DTB misses
-system.cpu.dtb.accesses 319535732 # DTB accesses
+system.cpu.dtb.hits 316048276 # DTB hits
+system.cpu.dtb.misses 934978 # DTB misses
+system.cpu.dtb.accesses 316983254 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 161585 # Table walker walks requested
-system.cpu.itb.walker.walksLong 161585 # Table walker walks initiated with long descriptors
-system.cpu.itb.walker.walksLongTerminationLevel::Level2 1428 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksLongTerminationLevel::Level3 121821 # Level at which table walker walks with long descriptors terminate
-system.cpu.itb.walker.walksSquashedBefore 17557 # Table walks squashed before starting
-system.cpu.itb.walker.walkWaitTime::samples 144028 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::mean 1321.829783 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::stdev 9926.807145 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0-32767 142959 99.26% 99.26% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::32768-65535 572 0.40% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::65536-98303 68 0.05% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::98304-131071 87 0.06% 99.76% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::131072-163839 270 0.19% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::163840-196607 28 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::196608-229375 7 0.00% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::229376-262143 14 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::262144-294911 11 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::360448-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::393216-425983 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 144028 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 140806 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 29194.196270 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 24049.387193 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 24612.430029 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-65535 137481 97.64% 97.64% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::65536-131071 705 0.50% 98.14% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::131072-196607 2241 1.59% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::196608-262143 147 0.10% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::262144-327679 149 0.11% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::327680-393215 40 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::393216-458751 28 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 161206 # Table walker walks requested
+system.cpu.itb.walker.walksLong 161206 # Table walker walks initiated with long descriptors
+system.cpu.itb.walker.walksLongTerminationLevel::Level2 1436 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksLongTerminationLevel::Level3 121549 # Level at which table walker walks with long descriptors terminate
+system.cpu.itb.walker.walksSquashedBefore 17620 # Table walks squashed before starting
+system.cpu.itb.walker.walkWaitTime::samples 143586 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::mean 1244.532893 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::stdev 9274.227664 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0-32767 142628 99.33% 99.33% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::32768-65535 542 0.38% 99.71% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::65536-98303 55 0.04% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::98304-131071 79 0.06% 99.80% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::131072-163839 218 0.15% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::163840-196607 29 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::262144-294911 14 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 143586 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 140605 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 28864.162014 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 24089.686815 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 22873.385810 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-65535 137806 98.01% 98.01% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::65536-131071 710 0.50% 98.51% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::131072-196607 1778 1.26% 99.78% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::196608-262143 108 0.08% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::262144-327679 117 0.08% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::327680-393215 38 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::393216-458751 35 0.02% 99.99% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 140806 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walksPending::samples 671312841344 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::mean 0.944614 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::stdev 0.229094 # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::0 37236199060 5.55% 5.55% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::1 634022806284 94.45% 99.99% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::2 53008500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::3 825500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::589824-655359 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::851968-917503 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 140605 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walksPending::samples 663785102088 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::mean 0.942542 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::stdev 0.233053 # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::0 38191035356 5.75% 5.75% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::1 625543374232 94.24% 99.99% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::2 49878500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu.itb.walker.walksPending::3 812000 0.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4 2000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu.itb.walker.walksPending::total 671312841344 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 121821 98.84% 98.84% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::2M 1428 1.16% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 123249 # Table walker page sizes translated
+system.cpu.itb.walker.walksPending::total 663785102088 # Table walker pending requests distribution
+system.cpu.itb.walker.walkPageSizes::4K 121549 98.83% 98.83% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::2M 1436 1.17% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 122985 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161585 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 161585 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161206 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 161206 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123249 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 123249 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 284834 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 358536824 # ITB inst hits
-system.cpu.itb.inst_misses 161585 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122985 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 122985 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 284191 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 355626065 # ITB inst hits
+system.cpu.itb.inst_misses 161206 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 39773 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 1023 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 53279 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_tlb_mva_asid 39152 # Number of times TLB was flushed by MVA & ASID
+system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID
+system.cpu.itb.flush_entries 52940 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 371261 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 369021 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 358698409 # ITB inst accesses
-system.cpu.itb.hits 358536824 # DTB hits
-system.cpu.itb.misses 161585 # DTB misses
-system.cpu.itb.accesses 358698409 # DTB accesses
-system.cpu.numCycles 1657263364 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 355787271 # ITB inst accesses
+system.cpu.itb.hits 355626065 # DTB hits
+system.cpu.itb.misses 161206 # DTB misses
+system.cpu.itb.accesses 355787271 # DTB accesses
+system.cpu.numCycles 1638586091 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 646687588 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1006138467 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 225483777 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 135052255 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 923834525 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 26119142 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 3836248 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 30247 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 9382773 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1057490 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 1024 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 358148752 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6114742 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 1597889466 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.737838 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.145066 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 642614268 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 998103903 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 223690256 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133920845 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 910005464 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 26014386 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 3801464 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 28966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 9302327 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1031206 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 853 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 355240310 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 6091194 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 48629 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 1579791741 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.740255 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.146164 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1037892560 64.95% 64.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 215037687 13.46% 78.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 70931005 4.44% 82.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 274028214 17.15% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1024362050 64.84% 64.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 213190505 13.49% 78.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 70458696 4.46% 82.80% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 271780490 17.20% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1597889466 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.136058 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.607108 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 525509961 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 577968560 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 434692108 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 50467392 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 9251445 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 33765808 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 3868232 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1090395947 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 29075856 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 9251445 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 570461027 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 71248505 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 374528556 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 440187114 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 132212819 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1070563825 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 6799460 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 5139795 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 352432 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 543797 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 80592393 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 20524 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 1018210604 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1650018567 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1266293182 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1471142 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 952425146 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 65785455 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 27183969 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23507268 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 103615043 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 174251996 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 151954482 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 9963478 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 9058683 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1035258502 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 27485968 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1050977707 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3302134 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 60681110 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33832223 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 315804 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1597889466 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.657729 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.917270 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 1579791741 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.136514 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.609125 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 522893988 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 566130284 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 431833495 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 49726107 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 9207867 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 33553949 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 3859168 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 1081567524 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 28956293 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 9207867 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 567372760 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 69190624 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 368823691 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 437050453 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 128146346 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1061861877 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 6771880 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 5087051 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 328687 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 662195 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 77193560 # Number of times rename has blocked due to SQ full
+system.cpu.rename.FullRegisterEvents 20256 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 1009820206 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1635273516 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1255804175 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 1470464 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 944392449 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 65427754 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 26765768 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 23112103 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 102007080 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 173010630 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 150618329 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 9860591 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 8967243 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 1027007600 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 27059230 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1042343751 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 3268943 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 60307743 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33600701 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 312855 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 1579791741 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.659798 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 0.917984 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 947140839 59.27% 59.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 336074269 21.03% 80.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 235675867 14.75% 95.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 72461429 4.53% 99.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 6517893 0.41% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 934526324 59.16% 59.16% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 332943694 21.08% 80.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 234048480 14.82% 95.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 71809082 4.55% 99.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 6444954 0.41% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 19207 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1597889466 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 1579791741 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 58047509 35.02% 35.02% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 99216 0.06% 35.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 26736 0.02% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 621 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.10% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44536420 26.87% 61.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 63031836 38.03% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 57575402 35.04% 35.04% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 100057 0.06% 35.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 26740 0.02% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 764 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 44168987 26.88% 62.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 62424891 38.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 723805798 68.87% 68.87% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2543227 0.24% 69.11% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 122751 0.01% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 717769712 68.86% 68.86% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 2531817 0.24% 69.10% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 122691 0.01% 69.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 120969 0.01% 69.13% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 121277 0.01% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 174113455 16.57% 85.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 150271445 14.30% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 172853843 16.58% 85.71% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 148944351 14.29% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1050977707 # Type of FU issued
-system.cpu.iq.rate 0.634165 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 165742338 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.157703 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3866409671 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1122621449 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1032956403 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 2479680 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 948183 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 910717 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1215162069 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 1557965 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 4345381 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1042343751 # Type of FU issued
+system.cpu.iq.rate 0.636124 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 164296841 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157623 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 3829567748 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1113568735 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1024464263 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 2477278 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 947290 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 909965 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1205083989 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 1556592 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 4287735 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 13856832 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 14557 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 145376 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 6348158 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 13755130 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 14415 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 142727 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 6290239 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 2556112 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1569383 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 2513645 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1546946 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 9251445 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 7205871 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 9780746 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1062967049 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 9207867 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 6935208 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 9652893 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 1054288001 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 174251996 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 151954482 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 23081360 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 59250 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 9646548 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 145376 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3669738 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 5114532 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 8784270 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1039771083 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 170205641 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10266382 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewDispLoadInsts 173010630 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 150618329 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 22687803 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 56498 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 9524585 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 142727 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 3650015 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 5096410 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 8746425 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1031209628 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 168969861 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 10209992 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 222579 # number of nop insts executed
-system.cpu.iew.exec_refs 318568485 # number of memory reference insts executed
-system.cpu.iew.exec_branches 197267293 # Number of branches executed
-system.cpu.iew.exec_stores 148362844 # Number of stores executed
-system.cpu.iew.exec_rate 0.627402 # Inst execution rate
-system.cpu.iew.wb_sent 1034679114 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1033867120 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 440084197 # num instructions producing a value
-system.cpu.iew.wb_consumers 711913770 # num instructions consuming a value
+system.cpu.iew.exec_nop 221171 # number of nop insts executed
+system.cpu.iew.exec_refs 316030804 # number of memory reference insts executed
+system.cpu.iew.exec_branches 195653401 # Number of branches executed
+system.cpu.iew.exec_stores 147060943 # Number of stores executed
+system.cpu.iew.exec_rate 0.629329 # Inst execution rate
+system.cpu.iew.wb_sent 1026179606 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1025374228 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 436457494 # num instructions producing a value
+system.cpu.iew.wb_consumers 705894723 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.623840 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.618171 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.625768 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.618304 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 51558670 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 27170164 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 8418357 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1585876661 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.631867 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.268709 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 51232529 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 26746375 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 8382033 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 1567845308 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 0.633837 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.270098 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 1071299476 67.55% 67.55% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 289640402 18.26% 85.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 120963875 7.63% 93.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 36621114 2.31% 95.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 28592038 1.80% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14082122 0.89% 98.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8687118 0.55% 98.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4193736 0.26% 99.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11796780 0.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 1057713558 67.46% 67.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 286814809 18.29% 85.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 120141410 7.66% 93.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 36433500 2.32% 95.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 28325160 1.81% 97.55% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 13966043 0.89% 98.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 8603569 0.55% 98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 4169387 0.27% 99.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 11677872 0.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1585876661 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 852762944 # Number of instructions committed
-system.cpu.commit.committedOps 1002063356 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 1567845308 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 845761974 # Number of instructions committed
+system.cpu.commit.committedOps 993759083 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 306001487 # Number of memory references committed
-system.cpu.commit.loads 160395163 # Number of loads committed
-system.cpu.commit.membars 6971183 # Number of memory barriers committed
-system.cpu.commit.branches 190333133 # Number of branches committed
-system.cpu.commit.fp_insts 897329 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 920660333 # Number of committed integer instructions.
-system.cpu.commit.function_calls 25420821 # Number of function calls committed.
+system.cpu.commit.refs 303583589 # Number of memory references committed
+system.cpu.commit.loads 159255499 # Number of loads committed
+system.cpu.commit.membars 6904959 # Number of memory barriers committed
+system.cpu.commit.branches 188760643 # Number of branches committed
+system.cpu.commit.fp_insts 896514 # Number of committed floating point instructions.
+system.cpu.commit.int_insts 913055926 # Number of committed integer instructions.
+system.cpu.commit.function_calls 25211674 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu.commit.op_class_0::IntMult 2156692 0.22% 69.44% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 98172 0.01% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 111800 0.01% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 160395163 16.01% 85.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 145606324 14.53% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 687818920 69.21% 69.21% # Class of committed instruction
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+system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction
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+system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction
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+system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction
+system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction
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+system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction
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system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 1002063356 # Class of committed instruction
-system.cpu.commit.bw_lim_events 11796780 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 2620126782 # The number of ROB reads
-system.cpu.rob.rob_writes 2119163855 # The number of ROB writes
-system.cpu.timesIdled 8145872 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 59373898 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 100926342082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 852762944 # Number of Instructions Simulated
-system.cpu.committedOps 1002063356 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.943405 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.943405 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.514561 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.514561 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1230978083 # number of integer regfile reads
-system.cpu.int_regfile_writes 734956592 # number of integer regfile writes
-system.cpu.fp_regfile_reads 1462594 # number of floating regfile reads
-system.cpu.fp_regfile_writes 785720 # number of floating regfile writes
-system.cpu.cc_regfile_reads 226481409 # number of cc regfile reads
-system.cpu.cc_regfile_writes 227147205 # number of cc regfile writes
-system.cpu.misc_regfile_reads 2590605655 # number of misc regfile reads
-system.cpu.misc_regfile_writes 27218545 # number of misc regfile writes
-system.cpu.dcache.tags.replacements 9745793 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.972785 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 284478201 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9746305 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 29.188313 # Average number of references to valid blocks.
+system.cpu.commit.op_class_0::total 993759083 # Class of committed instruction
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+system.cpu.rob.rob_reads 2593635375 # The number of ROB reads
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+system.cpu.timesIdled 8111566 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 58794350 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 101024450248 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 845761974 # Number of Instructions Simulated
+system.cpu.committedOps 993759083 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 1.937408 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.937408 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.516154 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.516154 # IPC: Total IPC of All Threads
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system.cpu.dcache.tags.warmup_cycle 2742937500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 385 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.dcache.tags.data_accesses 1242843351 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 147746281 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 147746281 # number of ReadReq hits
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-system.cpu.dcache.SoftPFReq_hits::total 378897 # number of SoftPFReq hits
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-system.cpu.dcache.WriteLineReq_hits::total 324717 # number of WriteLineReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 3321055 # number of LoadLockedReq hits
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-system.cpu.dcache.StoreCondReq_hits::total 3719262 # number of StoreCondReq hits
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-system.cpu.dcache.overall_hits::total 277068775 # number of overall hits
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-system.cpu.dcache.SoftPFReq_misses::total 1183380 # number of SoftPFReq misses
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-system.cpu.dcache.LoadLockedReq_misses::total 450358 # number of LoadLockedReq misses
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system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 276500 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 276500 # number of StoreCondReq miss cycles
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-system.cpu.dcache.StoreCondReq_accesses::total 3719267 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.overall_accesses::total 299225673 # number of overall (read+write) accesses
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-system.cpu.dcache.ReadReq_miss_rate::total 0.061010 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081057 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.081057 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.757471 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.757471 # miss rate for SoftPFReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791568 # miss rate for WriteLineReq accesses
-system.cpu.dcache.WriteLineReq_miss_rate::total 0.791568 # miss rate for WriteLineReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119414 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119414 # miss rate for LoadLockedReq accesses
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+system.cpu.dcache.WriteReq_accesses::total 139083363 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 54300 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 54300 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23134.060911 # average overall mshr miss latency
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.040343 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.409431 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.409431 # mshr miss rate for InvalidateReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.031106 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004742 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.012225 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005633 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079226 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.031106 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128612.839940 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70763.655401 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70763.655401 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.198000 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.198000 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005556 # mshr miss rate for ReadCleanReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038377 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038377 # mshr miss rate for ReadSharedReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.404153 # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.404153 # mshr miss rate for InvalidateReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.029592 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004095 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010201 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005556 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075405 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.029592 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 128635.929288 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70759.652909 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70759.652909 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70666.666667 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70666.666667 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 129127.304187 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 129127.304187 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124571.716553 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124571.716553 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 129275.526257 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 129275.526257 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145142.032882 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145142.032882 # average InvalidateReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129110.574342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128106.821282 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124571.716553 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 129185.230480 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128669.629299 # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128804.456762 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128804.456762 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124553.154731 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124553.154731 # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128827.977905 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128827.977905 # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145030.976188 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145030.976188 # average InvalidateReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 128052.262090 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129244.469746 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124553.154731 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128813.650717 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128322.659874 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160589.390700 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142372.364615 # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161581.908832 # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161581.908832 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160581.477522 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 142367.516781 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161580.662393 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161580.662393 # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113562.174219 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161085.782349 # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149672.377043 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 161081.203432 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149668.897811 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.snoop_filter.tot_requests 50352882 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 25547569 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3505 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 2096 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2096 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_requests 50050277 # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 25391485 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3463 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2168 # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2168 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.trans_dist::ReadReq 1630756 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 23229377 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 1617253 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 23096406 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 8639097 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 17453404 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 43769 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 8520965 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::CleanEvict 17374022 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 43114 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 43774 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 1981151 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1981151 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 15059021 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 6547690 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateReq 1332988 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::InvalidateResp 1226324 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45216170 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29460715 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728722 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1932656 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 77338263 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964104688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1028452958 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2398344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6286416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 2001242406 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 1898399 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 52724879 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.013444 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.115165 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::UpgradeResp 43119 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 1956286 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 1956286 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15001430 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 6485775 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateReq 1330832 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::InvalidateResp 1224168 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45043419 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29192673 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 728958 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917333 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 76882383 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 960419312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017977630 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2410856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6261232 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 1987069030 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 1835462 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 52366647 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 0.013365 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.114833 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 52016056 98.66% 98.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 708823 1.34% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 51666749 98.66% 98.66% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 699898 1.34% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 52724879 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 33221521499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 52366647 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 32990991996 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1449383 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.occupancy 1490388 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 22617176752 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 22530796241 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 13467693225 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 13336103780 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 429237366 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 427917846 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 1147199772 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 1135029759 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40289 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40289 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
system.iobus.trans_dist::WriteResp 136571 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230954 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230936 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353738 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353720 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334248 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334176 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 144645964 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144815950 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7232000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7232000 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 152047950 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 3147 # Total snoops (count)
-system.membus.snoop_fanout::samples 2799608 # Request fanout histogram
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138873356 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 139043342 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7266048 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 146309390 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2606 # Total snoops (count)
+system.membus.snoop_fanout::samples 2698981 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2799608 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2698981 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2799608 # Request fanout histogram
-system.membus.reqLayer0.occupancy 104476500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2698981 # Request fanout histogram
+system.membus.reqLayer0.occupancy 104149000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5464500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5470500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 7417701934 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 7144084722 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6905958013 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6645299856 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 228360981 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 228305891 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 19016 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 16105 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4\r
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
-[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000019] Console: colour dummy device 80x25\r
-[ 0.000021] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000022] pid_max: default: 32768 minimum: 301\r
-[ 0.000032] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000033] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000129] hw perfevents: no hardware support available\r
-[ 1.060065] CPU1: failed to come online\r
-[ 2.080127] CPU2: failed to come online\r
-[ 3.100189] CPU3: failed to come online\r
-[ 3.100192] Brought up 1 CPUs\r
-[ 3.100193] SMP: Total of 1 processors activated.\r
-[ 3.100240] devtmpfs: initialized\r
-[ 3.100669] atomic64_test: passed\r
-[ 3.100708] regulator-dummy: no parameters\r
-[ 3.101069] NET: Registered protocol family 16\r
-[ 3.101188] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101196] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101685] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101689] Serial: AMBA PL011 UART driver\r
-[ 3.101859] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101891] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.102431] console [ttyAMA0] enabled\r
-[ 3.102499] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102529] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102560] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102589] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130477] 3V3: 3300 mV \r
-[ 3.130516] vgaarb: loaded\r
-[ 3.130558] SCSI subsystem initialized\r
-[ 3.130594] libata version 3.00 loaded.\r
-[ 3.130636] usbcore: registered new interface driver usbfs\r
-[ 3.130652] usbcore: registered new interface driver hub\r
-[ 3.130683] usbcore: registered new device driver usb\r
-[ 3.130706] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130715] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130733] PTP clock support registered\r
-[ 3.130839] Switched to clocksource arch_sys_counter\r
-[ 3.131808] NET: Registered protocol family 2\r
-[ 3.131874] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131890] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131908] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131922] TCP: reno registered\r
-[ 3.131928] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131941] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131975] NET: Registered protocol family 1\r
-[ 3.132021] RPC: Registered named UNIX socket transport module.\r
-[ 3.132031] RPC: Registered udp transport module.\r
-[ 3.132039] RPC: Registered tcp transport module.\r
-[ 3.132047] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132058] PCI: CLS 0 bytes, default 64\r
-[ 3.132196] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132285] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133797] fuse init (API version 7.23)\r
-[ 3.133873] msgmni has been set to 469\r
-[ 3.135927] io scheduler noop registered\r
-[ 3.135975] io scheduler cfq registered (default)\r
-[ 3.136358] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136370] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136381] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136393] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136402] pci_bus 0000:00: scanning bus\r
-[ 3.136412] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136424] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136438] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136471] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136483] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136493] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136503] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136513] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136524] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136534] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136567] pci_bus 0000:00: fixups for bus\r
-[ 3.136574] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136586] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136603] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136611] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136621] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136629] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136639] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136651] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136664] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136676] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136687] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136698] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136709] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136720] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.137151] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137378] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137387] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137408] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137658] scsi0 : ata_piix\r
-[ 3.137744] scsi1 : ata_piix\r
-[ 3.137771] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137783] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137876] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137888] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137902] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137913] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290861] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290871] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290896] ata1.00: configured for UDMA/33\r
-[ 3.290937] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.291037] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.291060] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.291095] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.291104] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.291123] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291229] sda: sda1\r
-[ 3.291331] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411127] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411139] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411159] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411168] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411187] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411198] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411260] usbcore: registered new interface driver usb-storage\r
-[ 3.411309] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411443] usbcore: registered new interface driver usbhid\r
-[ 3.411452] usbhid: USB HID core driver\r
-[ 3.411480] TCP: cubic registered\r
-[ 3.411487] NET: Registered protocol family 17\r
-\0[ 3.411792] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411823] devtmpfs: mounted\r
-[ 3.411860] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
+[ 0.000022] Console: colour dummy device 80x25\r
+[ 0.000024] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000025] pid_max: default: 32768 minimum: 301\r
+[ 0.000037] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000038] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000160] hw perfevents: no hardware support available\r
+[ 1.060066] CPU1: failed to come online\r
+[ 2.080128] CPU2: failed to come online\r
+[ 3.100190] CPU3: failed to come online\r
+[ 3.100193] Brought up 1 CPUs\r
+[ 3.100194] SMP: Total of 1 processors activated.\r
+[ 3.100250] devtmpfs: initialized\r
+[ 3.100699] atomic64_test: passed\r
+[ 3.100742] regulator-dummy: no parameters\r
+[ 3.101165] NET: Registered protocol family 16\r
+[ 3.101292] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101300] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.102003] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.102009] Serial: AMBA PL011 UART driver\r
+[ 3.102199] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.102234] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102775] console [ttyAMA0] enabled\r
+[ 3.102856] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102886] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102917] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102946] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130499] 3V3: 3300 mV \r
+[ 3.130541] vgaarb: loaded\r
+[ 3.130587] SCSI subsystem initialized\r
+[ 3.130624] libata version 3.00 loaded.\r
+[ 3.130668] usbcore: registered new interface driver usbfs\r
+[ 3.130685] usbcore: registered new interface driver hub\r
+[ 3.130716] usbcore: registered new device driver usb\r
+[ 3.130740] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130749] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130767] PTP clock support registered\r
+[ 3.130884] Switched to clocksource arch_sys_counter\r
+[ 3.131878] NET: Registered protocol family 2\r
+[ 3.131953] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131970] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131991] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.132006] TCP: reno registered\r
+[ 3.132013] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132027] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132067] NET: Registered protocol family 1\r
+[ 3.132117] RPC: Registered named UNIX socket transport module.\r
+[ 3.132127] RPC: Registered udp transport module.\r
+[ 3.132135] RPC: Registered tcp transport module.\r
+[ 3.132142] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132154] PCI: CLS 0 bytes, default 64\r
+[ 3.132300] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132399] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133955] fuse init (API version 7.23)\r
+[ 3.134034] msgmni has been set to 469\r
+[ 3.136162] io scheduler noop registered\r
+[ 3.136212] io scheduler cfq registered (default)\r
+[ 3.136647] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136660] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136670] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136682] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136692] pci_bus 0000:00: scanning bus\r
+[ 3.136702] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136715] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136729] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136765] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136776] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136787] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136797] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136807] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136817] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136828] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136861] pci_bus 0000:00: fixups for bus\r
+[ 3.136869] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136881] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136900] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136908] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136918] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136926] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136937] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136949] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136962] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136974] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136985] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136996] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.137007] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.137018] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.137463] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137704] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137714] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137738] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.138003] scsi0 : ata_piix\r
+[ 3.138095] scsi1 : ata_piix\r
+[ 3.138123] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.138135] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.138234] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.138245] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.138260] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.138271] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290909] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290918] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290944] ata1.00: configured for UDMA/33\r
+[ 3.290993] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.291096] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.291119] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.291156] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.291164] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.291183] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291296] sda: sda1\r
+[ 3.291402] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411176] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411189] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411209] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411218] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411237] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411249] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411312] usbcore: registered new interface driver usb-storage\r
+[ 3.411363] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411500] usbcore: registered new interface driver usbhid\r
+[ 3.411510] usbhid: USB HID core driver\r
+[ 3.411540] TCP: cubic registered\r
+[ 3.411547] NET: Registered protocol family 17\r
+\0[ 3.411879] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411912] devtmpfs: mounted\r
+[ 3.411960] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450179] udevd[607]: starting version 182\r
+[ 3.450384] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.543317] random: dd urandom read with 19 bits of entropy available\r
+[ 3.543428] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
Mon Jan 27 08:00:00 UTC 2014\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
-Configuring network interfaces... [ 3.671067] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+Configuring network interfaces... [ 3.671113] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
udhcpc (v1.21.1) started\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
"mmap_using_noreserve": false,
"kernel_addr_check": true,
"highest_el_is_64": false,
- "kernel": "/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821",
+ "kernel": "/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821",
"iobus": {
"slave": {
"peer": [
"frontend_latency": 2
},
"symbolfile": "",
- "readfile": "/scratch/nilay/GEM5/gem5/tests/halt.sh",
+ "readfile": "/home/joel/research/gem5/gem5/tests/halt.sh",
"have_large_asid_64": false,
"phys_addr_range_64": 40,
"have_lpae": false,
"multi_proc": true,
"early_kernel_symbols": false,
"panic_on_oops": true,
- "dtb_filename": "/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb",
+ "dtb_filename": "/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb",
+ "panic_on_panic": true,
"enable_context_switch_stats_dump": false,
"work_begin_ckpt_count": 0,
"clk_domain": {
"MSIXCAPNextCapability": 0,
"PXCAPLinkCtrl": 0,
"Revision": 0,
- "hardware_address": "<m5.params.EthernetAddr object at 0x511b690>",
+ "hardware_address": "<m5.params.EthernetAddr object at 0x7f5e39f1b590>",
"LegacyIOBase": 0,
"pio_latency": 30000,
"platform": "system.realview",
"use_default_range": false,
"frontend_latency": 3
},
- "panic_on_panic": true,
+ "multi_thread": false,
"eventq_index": 0,
"iocache": {
"cpu_side": {
"role": "SLAVE"
},
"name": "toL2Bus",
- "snoop_filter": null,
+ "snoop_filter": {
+ "name": "snoop_filter",
+ "system": "system",
+ "max_capacity": 8388608,
+ "eventq_index": 0,
+ "cxx_class": "SnoopFilter",
+ "path": "system.cpu.toL2Bus.snoop_filter",
+ "type": "SnoopFilter",
+ "lookup_latency": 0
+ },
"forward_latency": 0,
"clk_domain": "system.cpu_clk_domain",
"system": "system",
"sequential_access": false,
"assoc": 1
},
- "interrupts": {
- "eventq_index": 0,
- "path": "system.cpu.interrupts",
- "type": "ArmInterrupts",
- "name": "interrupts",
- "cxx_class": "ArmISA::Interrupts"
- },
+ "interrupts": [
+ {
+ "eventq_index": 0,
+ "path": "system.cpu.interrupts",
+ "type": "ArmInterrupts",
+ "name": "interrupts",
+ "cxx_class": "ArmISA::Interrupts"
+ }
+ ],
"dcache_port": {
"peer": "system.cpu.dcache.cpu_side",
"role": "MASTER"
"eventq_index": 0,
"cxx_class": "RawDiskImage",
"path": "system.cf0.image.child",
- "image_file": "/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img",
+ "image_file": "/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img",
"type": "RawDiskImage"
},
"path": "system.cf0.image",
"system.realview.vram"
],
"work_begin_cpu_id_exit": -1,
- "boot_loader": "/scratch/nilay/GEM5/system/binaries/boot_emm.arm64",
+ "boot_loader": "/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64",
"num_work_ids": 16
},
"time_sync_period": 100000000000,
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1154147 # Simulator instruction rate (inst/s)
-host_op_rate 1356312 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59914222846 # Simulator tick rate (ticks/s)
-host_mem_usage 725376 # Number of bytes of host memory used
-host_seconds 853.07 # Real time elapsed on the host
+host_inst_rate 549288 # Simulator instruction rate (inst/s)
+host_op_rate 645503 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 28514691627 # Simulator tick rate (ticks/s)
+host_mem_usage 672288 # Number of bytes of host memory used
+host_seconds 1792.45 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.itb.hits 985047321 # DTB hits
system.cpu.itb.misses 126837 # DTB misses
system.cpu.itb.accesses 985174158 # DTB accesses
-system.cpu.numCycles 102222325018 # number of cpu cycles simulated
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu.committedInsts 984570519 # Number of instructions committed
system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
system.cpu.num_mem_refs 352465606 # number of memory refs
system.cpu.num_load_insts 184180431 # Number of load instructions
system.cpu.num_store_insts 168285175 # Number of store instructions
-system.cpu.num_idle_cycles 101064646448.926407 # Number of idle cycles
-system.cpu.num_busy_cycles 1157678569.073592 # Number of busy cycles
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
system.cpu.Branches 220088562 # Number of branches fetched
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1157666593 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 19653 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 11612141 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu0.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.cpu0.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu1.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+[system.cpu1.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:11:51
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 05:11:30
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 47216814145000 because m5_exit instruction encountered
sim_ticks 47216814145000 # Number of ticks simulated
final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1096625 # Simulator instruction rate (inst/s)
-host_op_rate 1290081 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 53081906922 # Simulator tick rate (ticks/s)
-host_mem_usage 734248 # Number of bytes of host memory used
-host_seconds 889.51 # Real time elapsed on the host
+host_inst_rate 645560 # Simulator instruction rate (inst/s)
+host_op_rate 759443 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 31248192864 # Simulator tick rate (ticks/s)
+host_mem_usage 683532 # Number of bytes of host memory used
+host_seconds 1511.03 # Real time elapsed on the host
sim_insts 975457230 # Number of instructions simulated
sim_ops 1147538415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.itb.hits 497696393 # DTB hits
system.cpu0.itb.misses 61377 # DTB misses
system.cpu0.itb.accesses 497757770 # DTB accesses
-system.cpu0.numCycles 94433643486 # number of cpu cycles simulated
+system.cpu0.numCycles 94433641544 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
system.cpu0.committedInsts 497466384 # Number of instructions committed
system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses
system.cpu0.num_mem_refs 178459396 # number of memory refs
system.cpu0.num_load_insts 92737001 # Number of load instructions
system.cpu0.num_store_insts 85722395 # Number of store instructions
-system.cpu0.num_idle_cycles 93848339121.288452 # Number of idle cycles
-system.cpu0.num_busy_cycles 585304364.711543 # Number of busy cycles
+system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles
+system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles
system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles
system.cpu0.Branches 111287587 # Number of branches fetched
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 585300003 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 15195 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 6272771 # number of replacements
system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 172015771 # Total number of references to valid blocks.
system.cpu1.itb.hits 478248118 # DTB hits
system.cpu1.itb.misses 60885 # DTB misses
system.cpu1.itb.accesses 478309003 # DTB accesses
-system.cpu1.numCycles 94433635490 # number of cpu cycles simulated
+system.cpu1.numCycles 94433634550 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed
system.cpu1.committedInsts 477990846 # Number of instructions committed
system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses
system.cpu1.num_mem_refs 171406825 # number of memory refs
system.cpu1.num_load_insts 90251973 # Number of load instructions
system.cpu1.num_store_insts 81154852 # Number of store instructions
-system.cpu1.num_idle_cycles 93870751219.397461 # Number of idle cycles
-system.cpu1.num_busy_cycles 562884270.602548 # Number of busy cycles
+system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles
+system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles
system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles
system.cpu1.Branches 106497601 # Number of branches fetched
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 562879339 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 7199 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 5945049 # number of replacements
system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks.
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 03:06:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 04:45:04
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-atomic
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 51111152682000 because m5_exit instruction encountered
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1157716 # Simulator instruction rate (inst/s)
-host_op_rate 1360507 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 60099512933 # Simulator tick rate (ticks/s)
-host_mem_usage 720388 # Number of bytes of host memory used
-host_seconds 850.44 # Real time elapsed on the host
+host_inst_rate 625482 # Simulator instruction rate (inst/s)
+host_op_rate 735044 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32470102586 # Simulator tick rate (ticks/s)
+host_mem_usage 669952 # Number of bytes of host memory used
+host_seconds 1574.10 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.itb.hits 985047321 # DTB hits
system.cpu.itb.misses 126837 # DTB misses
system.cpu.itb.accesses 985174158 # DTB accesses
-system.cpu.numCycles 102222325018 # number of cpu cycles simulated
+system.cpu.numCycles 102222322140 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu.committedInsts 984570519 # Number of instructions committed
system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses
system.cpu.num_mem_refs 352465606 # number of memory refs
system.cpu.num_load_insts 184180431 # Number of load instructions
system.cpu.num_store_insts 168285175 # Number of store instructions
-system.cpu.num_idle_cycles 101064646448.926407 # Number of idle cycles
-system.cpu.num_busy_cycles 1157678569.073592 # Number of busy cycles
+system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles
+system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles
system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.988675 # Percentage of idle cycles
system.cpu.Branches 220088562 # Number of branches fetched
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1157666593 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 19653 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 11612141 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks.
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu0.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu0.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu0.l2cache.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.cpu0.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu0.tracer]
type=ExeTracer
eventq_index=0
[system.cpu1.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu1.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu1.l2cache.cpu_side
slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port
+[system.cpu1.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu1.tracer]
type=ExeTracer
eventq_index=0
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 02:37:28
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 09:57:43
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing-dual
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 47456679626500 because m5_exit instruction encountered
+Exiting @ tick 47474700369500 because m5_exit instruction encountered
sim_ticks 47474700369500 # Number of ticks simulated
final_tick 47474700369500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 631720 # Simulator instruction rate (inst/s)
-host_op_rate 743100 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34016391858 # Simulator tick rate (ticks/s)
-host_mem_usage 766400 # Number of bytes of host memory used
-host_seconds 1395.64 # Real time elapsed on the host
+host_inst_rate 794386 # Simulator instruction rate (inst/s)
+host_op_rate 934446 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 42775515400 # Simulator tick rate (ticks/s)
+host_mem_usage 715280 # Number of bytes of host memory used
+host_seconds 1109.86 # Real time elapsed on the host
sim_insts 881655060 # Number of instructions simulated
sim_ops 1037101350 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.numCycles 94949400739 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 5268 # number of quiesce instructions executed
system.cpu0.committedInsts 440958495 # Number of instructions committed
system.cpu0.committedOps 519578987 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 478066113 # Number of integer alu accesses
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 519868732 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 7168 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 5565465 # number of replacements
system.cpu0.dcache.tags.tagsinuse 503.695844 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 153367622 # Total number of references to valid blocks.
system.cpu1.numCycles 94949400719 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 13508 # number of quiesce instructions executed
system.cpu1.committedInsts 440696565 # Number of instructions committed
system.cpu1.committedOps 517522363 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 474820793 # Number of integer alu accesses
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 517832459 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 14490 # number of quiesce instructions executed
system.cpu1.dcache.tags.replacements 5147651 # number of replacements
system.cpu1.dcache.tags.tagsinuse 420.489425 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 152204564 # Total number of references to valid blocks.
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000029] Console: colour dummy device 80x25\r
-[ 0.000031] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000033] pid_max: default: 32768 minimum: 301\r
-[ 0.000048] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000050] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000222] hw perfevents: no hardware support available\r
-[ 0.060058] CPU1: Booted secondary processor\r
-[ 1.080093] CPU2: failed to come online\r
-[ 2.100180] CPU3: failed to come online\r
-[ 2.100183] Brought up 2 CPUs\r
-[ 2.100185] SMP: Total of 2 processors activated.\r
-[ 2.100258] devtmpfs: initialized\r
-[ 2.100912] atomic64_test: passed\r
-[ 2.100971] regulator-dummy: no parameters\r
-[ 2.101423] NET: Registered protocol family 16\r
-[ 2.101601] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 2.101609] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 2.103309] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 2.103313] Serial: AMBA PL011 UART driver\r
-[ 2.103557] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 2.103606] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 2.104158] console [ttyAMA0] enabled\r
-[ 2.104242] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 2.104279] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 2.104316] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 2.104350] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 2.130486] 3V3: 3300 mV \r
-[ 2.130544] vgaarb: loaded\r
-[ 2.130608] SCSI subsystem initialized\r
-[ 2.130645] libata version 3.00 loaded.\r
-[ 2.130706] usbcore: registered new interface driver usbfs\r
-[ 2.130725] usbcore: registered new interface driver hub\r
-[ 2.130751] usbcore: registered new device driver usb\r
-[ 2.130779] pps_core: LinuxPPS API ver. 1 registered\r
-[ 2.130788] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 2.130807] PTP clock support registered\r
-[ 2.130959] Switched to clocksource arch_sys_counter\r
-[ 2.132580] NET: Registered protocol family 2\r
-[ 2.132678] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 2.132697] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 2.132716] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 2.132756] TCP: reno registered\r
-[ 2.132763] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132776] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 2.132818] NET: Registered protocol family 1\r
-[ 2.132885] RPC: Registered named UNIX socket transport module.\r
-[ 2.132895] RPC: Registered udp transport module.\r
-[ 2.132903] RPC: Registered tcp transport module.\r
-[ 2.132911] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 2.132923] PCI: CLS 0 bytes, default 64\r
-[ 2.133119] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 2.133227] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 2.135972] fuse init (API version 7.23)\r
-[ 2.136086] msgmni has been set to 469\r
-[ 2.136303] io scheduler noop registered\r
-[ 2.136365] io scheduler cfq registered (default)\r
-[ 2.137096] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 2.137109] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 2.137120] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 2.137132] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 2.137143] pci_bus 0000:00: scanning bus\r
-[ 2.137154] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 2.137167] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 2.137182] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.137222] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 2.137234] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 2.137245] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 2.137256] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 2.137267] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 2.137277] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 2.137289] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 2.137330] pci_bus 0000:00: fixups for bus\r
-[ 2.137339] pci_bus 0000:00: bus scan returning with max=00\r
-[ 2.137351] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 2.137371] pci 0000:00:00.0: fixup irq: got 33\r
-[ 2.137379] pci 0000:00:00.0: assigning IRQ 33\r
-[ 2.137390] pci 0000:00:01.0: fixup irq: got 34\r
-[ 2.137399] pci 0000:00:01.0: assigning IRQ 34\r
-[ 2.137410] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 2.137423] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 2.137436] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 2.137449] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 2.137461] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 2.137472] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 2.137484] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 2.137495] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 2.138294] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 2.138626] ata_piix 0000:00:01.0: version 2.13\r
-[ 2.138636] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 2.138670] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 2.139006] scsi0 : ata_piix\r
-[ 2.139097] scsi1 : ata_piix\r
-[ 2.139131] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 2.139143] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 2.139268] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 2.139280] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 2.139297] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 2.139308] e1000 0000:00:00.0: enabling bus mastering\r
-[ 2.291000] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 2.291010] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 2.291039] ata1.00: configured for UDMA/33\r
-[ 2.291099] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 2.291228] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 2.291262] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 2.291303] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 2.291313] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 2.291334] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 2.291502] sda: sda1\r
-[ 2.291677] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 2.411277] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 2.411290] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 2.411316] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 2.411326] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 2.411349] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 2.411361] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 2.411451] usbcore: registered new interface driver usb-storage\r
-[ 2.411518] mousedev: PS/2 mouse device common for all mice\r
-[ 2.411720] usbcore: registered new interface driver usbhid\r
-[ 2.411730] usbhid: USB HID core driver\r
-[ 2.411767] TCP: cubic registered\r
-[ 2.411774] NET: Registered protocol family 17\r
-\0[ 2.412217] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 2.412254] devtmpfs: mounted\r
-[ 2.412348] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000034] Console: colour dummy device 80x25\r
+[ 0.000037] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000039] pid_max: default: 32768 minimum: 301\r
+[ 0.000056] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000058] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000283] hw perfevents: no hardware support available\r
+[ 0.060072] CPU1: Booted secondary processor\r
+[ 1.080102] CPU2: failed to come online\r
+[ 2.100198] CPU3: failed to come online\r
+[ 2.100202] Brought up 2 CPUs\r
+[ 2.100203] SMP: Total of 2 processors activated.\r
+[ 2.100288] devtmpfs: initialized\r
+[ 2.100965] atomic64_test: passed\r
+[ 2.101032] regulator-dummy: no parameters\r
+[ 2.101510] NET: Registered protocol family 16\r
+[ 2.101705] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 2.101713] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 2.104254] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 2.104259] Serial: AMBA PL011 UART driver\r
+[ 2.104528] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 2.104583] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 2.105136] console [ttyAMA0] enabled\r
+[ 2.105312] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 2.105383] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 2.105454] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 2.105525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 2.140512] 3V3: 3300 mV \r
+[ 2.140575] vgaarb: loaded\r
+[ 2.140646] SCSI subsystem initialized\r
+[ 2.140688] libata version 3.00 loaded.\r
+[ 2.140754] usbcore: registered new interface driver usbfs\r
+[ 2.140773] usbcore: registered new interface driver hub\r
+[ 2.140799] usbcore: registered new device driver usb\r
+[ 2.140827] pps_core: LinuxPPS API ver. 1 registered\r
+[ 2.140836] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 2.140855] PTP clock support registered\r
+[ 2.141021] Switched to clocksource arch_sys_counter\r
+[ 2.142836] NET: Registered protocol family 2\r
+[ 2.142944] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 2.142963] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 2.142983] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 2.143021] TCP: reno registered\r
+[ 2.143028] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.143042] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 2.143086] NET: Registered protocol family 1\r
+[ 2.143165] RPC: Registered named UNIX socket transport module.\r
+[ 2.143175] RPC: Registered udp transport module.\r
+[ 2.143183] RPC: Registered tcp transport module.\r
+[ 2.143191] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 2.143204] PCI: CLS 0 bytes, default 64\r
+[ 2.143400] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 2.143510] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 2.145590] fuse init (API version 7.23)\r
+[ 2.145695] msgmni has been set to 469\r
+[ 2.145852] io scheduler noop registered\r
+[ 2.145915] io scheduler cfq registered (default)\r
+[ 2.146816] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 2.146829] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 2.146841] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 2.146853] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 2.146863] pci_bus 0000:00: scanning bus\r
+[ 2.146876] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 2.146890] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 2.146905] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.146947] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 2.146959] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 2.146970] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 2.146981] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 2.146992] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 2.147003] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 2.147014] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 2.147055] pci_bus 0000:00: fixups for bus\r
+[ 2.147064] pci_bus 0000:00: bus scan returning with max=00\r
+[ 2.147076] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 2.147097] pci 0000:00:00.0: fixup irq: got 33\r
+[ 2.147106] pci 0000:00:00.0: assigning IRQ 33\r
+[ 2.147117] pci 0000:00:01.0: fixup irq: got 34\r
+[ 2.147125] pci 0000:00:01.0: assigning IRQ 34\r
+[ 2.147138] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 2.147151] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 2.147164] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 2.147177] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 2.147188] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 2.147200] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 2.147211] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 2.147223] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 2.147859] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 2.148201] ata_piix 0000:00:01.0: version 2.13\r
+[ 2.148212] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 2.148254] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 2.148612] scsi0 : ata_piix\r
+[ 2.148712] scsi1 : ata_piix\r
+[ 2.148751] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 2.148763] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 2.148915] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 2.148927] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 2.148942] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 2.148954] e1000 0000:00:00.0: enabling bus mastering\r
+[ 2.301068] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 2.301078] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 2.301108] ata1.00: configured for UDMA/33\r
+[ 2.301184] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 2.301329] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 2.301345] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 2.301418] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 2.301427] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 2.301448] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 2.301621] sda: sda1\r
+[ 2.301758] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 2.421351] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 2.421364] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 2.421389] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 2.421399] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 2.421422] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 2.421433] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 2.421523] usbcore: registered new interface driver usb-storage\r
+[ 2.421602] mousedev: PS/2 mouse device common for all mice\r
+[ 2.421816] usbcore: registered new interface driver usbhid\r
+[ 2.421826] usbhid: USB HID core driver\r
+[ 2.421867] TCP: cubic registered\r
+[ 2.421875] NET: Registered protocol family 17\r
+\0[ 2.422336] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 2.422376] devtmpfs: mounted\r
+[ 2.422508] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 2.452452] udevd[608]: starting version 182\r
+[ 2.462853] udevd[609]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 2.534107] random: dd urandom read with 18 bits of entropy available\r
+[ 2.544315] random: dd urandom read with 18 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 2.661194] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 2.681254] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu cpu_clk_domain dvfs_handler intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Sep 14 2015 23:29:19
-gem5 started Sep 15 2015 00:24:53
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 05:27:57
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-simple-timing
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
-info: Loading DTB file: /scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
+info: Loading DTB file: /home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb at address 0x88000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 51832458543500 because m5_exit instruction encountered
+Exiting @ tick 51811426272500 because m5_exit instruction encountered
sim_ticks 51811426272500 # Number of ticks simulated
final_tick 51811426272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 673469 # Simulator instruction rate (inst/s)
-host_op_rate 791455 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 42067688868 # Simulator tick rate (ticks/s)
-host_mem_usage 720644 # Number of bytes of host memory used
-host_seconds 1231.62 # Real time elapsed on the host
+host_inst_rate 429786 # Simulator instruction rate (inst/s)
+host_op_rate 505081 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26846252166 # Simulator tick rate (ticks/s)
+host_mem_usage 669952 # Number of bytes of host memory used
+host_seconds 1929.93 # Real time elapsed on the host
sim_insts 829457901 # Number of instructions simulated
sim_ops 974772546 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.numCycles 103622852545 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 15973 # number of quiesce instructions executed
system.cpu.committedInsts 829457901 # Number of instructions committed
system.cpu.committedOps 974772546 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 896189211 # Number of integer alu accesses
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 975326961 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 18851 # number of quiesce instructions executed
system.cpu.dcache.tags.replacements 9274254 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 288519025 # Total number of references to valid blocks.
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000040] Console: colour dummy device 80x25\r
-[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000045] pid_max: default: 32768 minimum: 301\r
-[ 0.000067] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000281] hw perfevents: no hardware support available\r
-[ 1.060134] CPU1: failed to come online\r
-[ 2.080264] CPU2: failed to come online\r
-[ 3.100395] CPU3: failed to come online\r
-[ 3.100400] Brought up 1 CPUs\r
-[ 3.100402] SMP: Total of 1 processors activated.\r
-[ 3.100503] devtmpfs: initialized\r
-[ 3.101580] atomic64_test: passed\r
-[ 3.101658] regulator-dummy: no parameters\r
-[ 3.102417] NET: Registered protocol family 16\r
-[ 3.102687] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.102698] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.104168] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.104175] Serial: AMBA PL011 UART driver\r
-[ 3.104541] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.104609] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.105167] console [ttyAMA0] enabled\r
-[ 3.105294] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.105343] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.105393] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.105437] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130927] 3V3: 3300 mV \r
-[ 3.131005] vgaarb: loaded\r
-[ 3.131096] SCSI subsystem initialized\r
-[ 3.131165] libata version 3.00 loaded.\r
-[ 3.131250] usbcore: registered new interface driver usbfs\r
-[ 3.131276] usbcore: registered new interface driver hub\r
-[ 3.131330] usbcore: registered new device driver usb\r
-[ 3.131374] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131383] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131406] PTP clock support registered\r
-[ 3.131631] Switched to clocksource arch_sys_counter\r
-[ 3.133692] NET: Registered protocol family 2\r
-[ 3.133845] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.133872] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.133905] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.133943] TCP: reno registered\r
-[ 3.133951] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.133968] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134032] NET: Registered protocol family 1\r
-[ 3.134102] RPC: Registered named UNIX socket transport module.\r
-[ 3.134112] RPC: Registered udp transport module.\r
-[ 3.134121] RPC: Registered tcp transport module.\r
-[ 3.134129] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.134142] PCI: CLS 0 bytes, default 64\r
-[ 3.134458] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.134657] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.138123] fuse init (API version 7.23)\r
-[ 3.138286] msgmni has been set to 469\r
-[ 3.142763] io scheduler noop registered\r
-[ 3.142858] io scheduler cfq registered (default)\r
-[ 3.143781] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.143795] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.143807] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.143821] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.143832] pci_bus 0000:00: scanning bus\r
-[ 3.143845] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.143859] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.143876] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.143936] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.143950] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.143962] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.143974] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.143986] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.143999] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.144012] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.144070] pci_bus 0000:00: fixups for bus\r
-[ 3.144079] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.144093] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.144117] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.144127] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.144140] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.144149] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.144164] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.144178] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.144193] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.144207] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.144220] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.144232] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.144245] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.144258] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.145146] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.145648] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.145659] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.145695] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.146265] scsi0 : ata_piix\r
-[ 3.146439] scsi1 : ata_piix\r
-[ 3.146491] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.146504] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.146696] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.146709] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.146730] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.146742] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301663] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301673] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301707] ata1.00: configured for UDMA/33\r
-[ 3.301781] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.301972] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.302006] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.302063] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.302073] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.302101] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.302304] sda: sda1\r
-[ 3.302503] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.421983] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.421997] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.422026] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.422037] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.422067] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.422079] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.422208] usbcore: registered new interface driver usb-storage\r
-[ 3.422298] mousedev: PS/2 mouse device common for all mice\r
-[ 3.422583] usbcore: registered new interface driver usbhid\r
-[ 3.422593] usbhid: USB HID core driver\r
-[ 3.422643] TCP: cubic registered\r
-[ 3.422652] NET: Registered protocol family 17\r
-\0[ 3.423238] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.423282] devtmpfs: mounted\r
-[ 3.423373] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000045] Console: colour dummy device 80x25\r
+[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000051] pid_max: default: 32768 minimum: 301\r
+[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000351] hw perfevents: no hardware support available\r
+[ 1.060135] CPU1: failed to come online\r
+[ 2.080265] CPU2: failed to come online\r
+[ 3.100397] CPU3: failed to come online\r
+[ 3.100402] Brought up 1 CPUs\r
+[ 3.100404] SMP: Total of 1 processors activated.\r
+[ 3.100520] devtmpfs: initialized\r
+[ 3.101635] atomic64_test: passed\r
+[ 3.101723] regulator-dummy: no parameters\r
+[ 3.102566] NET: Registered protocol family 16\r
+[ 3.102856] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.102868] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.105188] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.105196] Serial: AMBA PL011 UART driver\r
+[ 3.105598] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.105673] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.106233] console [ttyAMA0] enabled\r
+[ 3.106381] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.106430] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.106480] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.106525] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130846] 3V3: 3300 mV \r
+[ 3.130935] vgaarb: loaded\r
+[ 3.131031] SCSI subsystem initialized\r
+[ 3.131105] libata version 3.00 loaded.\r
+[ 3.131196] usbcore: registered new interface driver usbfs\r
+[ 3.131223] usbcore: registered new interface driver hub\r
+[ 3.131280] usbcore: registered new device driver usb\r
+[ 3.131327] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.131337] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.131360] PTP clock support registered\r
+[ 3.131601] Switched to clocksource arch_sys_counter\r
+[ 3.133812] NET: Registered protocol family 2\r
+[ 3.133978] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.134010] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.134049] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.134102] TCP: reno registered\r
+[ 3.134110] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134130] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134205] NET: Registered protocol family 1\r
+[ 3.134284] RPC: Registered named UNIX socket transport module.\r
+[ 3.134295] RPC: Registered udp transport module.\r
+[ 3.134303] RPC: Registered tcp transport module.\r
+[ 3.134312] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.134325] PCI: CLS 0 bytes, default 64\r
+[ 3.134668] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.134906] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.138674] fuse init (API version 7.23)\r
+[ 3.138847] msgmni has been set to 469\r
+[ 3.143613] io scheduler noop registered\r
+[ 3.143710] io scheduler cfq registered (default)\r
+[ 3.144765] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.144779] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.144791] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.144805] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.144816] pci_bus 0000:00: scanning bus\r
+[ 3.144830] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.144845] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.144863] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.144927] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.144940] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.144953] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.144965] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.144977] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.144989] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.145002] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.145062] pci_bus 0000:00: fixups for bus\r
+[ 3.145072] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.145086] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.145114] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.145124] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.145137] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.145147] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.145161] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.145176] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.145190] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.145204] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.145217] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.145229] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.145242] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.145255] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.146169] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.146701] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.146713] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.146758] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.147367] scsi0 : ata_piix\r
+[ 3.147556] scsi1 : ata_piix\r
+[ 3.147609] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.147622] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.147827] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.147840] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.147862] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.147875] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.301637] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.301648] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.301682] ata1.00: configured for UDMA/33\r
+[ 3.301771] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.301967] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.302002] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.302060] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.302070] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.302099] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.302301] sda: sda1\r
+[ 3.302507] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.421962] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.421977] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.422006] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.422017] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.422047] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.422060] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.422190] usbcore: registered new interface driver usb-storage\r
+[ 3.422283] mousedev: PS/2 mouse device common for all mice\r
+[ 3.422576] usbcore: registered new interface driver usbhid\r
+[ 3.422586] usbhid: USB HID core driver\r
+[ 3.422642] TCP: cubic registered\r
+[ 3.422651] NET: Registered protocol family 17\r
+\0[ 3.423281] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.423327] devtmpfs: mounted\r
+[ 3.423453] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.470155] udevd[607]: starting version 182\r
+[ 3.470409] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.606530] random: dd urandom read with 20 bits of entropy available\r
+[ 3.586522] random: dd urandom read with 21 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.801865] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.791837] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
fastmem=false
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:28:27
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 06:00:18
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-atomic
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1150787 # Simulator instruction rate (inst/s)
-host_op_rate 1352364 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59739798990 # Simulator tick rate (ticks/s)
-host_mem_usage 722184 # Number of bytes of host memory used
-host_seconds 855.56 # Real time elapsed on the host
+host_inst_rate 564761 # Simulator instruction rate (inst/s)
+host_op_rate 663687 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 29317960092 # Simulator tick rate (ticks/s)
+host_mem_usage 669948 # Number of bytes of host memory used
+host_seconds 1743.34 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.itb.hits 493558289 # DTB hits
system.cpu0.itb.misses 70623 # DTB misses
system.cpu0.itb.accesses 493628912 # DTB accesses
-system.cpu0.numCycles 98036734134 # number of cpu cycles simulated
+system.cpu0.numCycles 98036732821 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed
system.cpu0.committedInsts 493343054 # Number of instructions committed
system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses
system.cpu0.num_mem_refs 176296730 # number of memory refs
system.cpu0.num_load_insts 91967123 # Number of load instructions
system.cpu0.num_store_insts 84329607 # Number of store instructions
-system.cpu0.num_idle_cycles 96926192639.173721 # Number of idle cycles
-system.cpu0.num_busy_cycles 1110541494.826277 # Number of busy cycles
+system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles
+system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles
system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles
system.cpu0.Branches 110281342 # Number of branches fetched
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 579643698 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 19653 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 11612141 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks.
system.cpu1.itb.hits 491475383 # DTB hits
system.cpu1.itb.misses 69863 # DTB misses
system.cpu1.itb.accesses 491545246 # DTB accesses
-system.cpu1.numCycles 97463066094 # number of cpu cycles simulated
+system.cpu1.numCycles 97463064529 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 491227465 # Number of instructions committed
system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses
system.cpu1.num_mem_refs 176168876 # number of memory refs
system.cpu1.num_load_insts 92213308 # Number of load instructions
system.cpu1.num_store_insts 83955568 # Number of store instructions
-system.cpu1.num_idle_cycles 96357045557.909821 # Number of idle cycles
-system.cpu1.num_busy_cycles 1106020536.090176 # Number of busy cycles
+system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles
+system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles
system.cpu1.Branches 109807220 # Number of branches fetched
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 578022895 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
eventq_index=0
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
fetch2ToDecodeForwardDelay=1
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu2.isa
istage2_mmu=system.cpu2.istage2_mmu
itb=system.cpu2.itb
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-interrupts=Null
+interrupts=
isa=system.cpu3.isa
issueToExecuteDelay=1
issueWidth=8
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7794, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10910, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9535, Bank: 3
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10604, Bank: 7
-warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
-warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: Tried to read RealView I/O at offset 0x8 that doesn't exist
+warn: Tried to read RealView I/O at offset 0x48 that doesn't exist
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is not active!
+Command: 2, Timestamp: 3608, Bank: 6
+WARNING: Bank is not active!
+Command: 2, Timestamp: 3612, Bank: 6
+WARNING: Bank is not active!
+Command: 2, Timestamp: 3616, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12396, Bank: 7
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11836, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6875, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9461, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7145, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6518, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12331, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9979, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10161, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11757, Bank: 2
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
Command: 0, Timestamp: 6448, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6479, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8819, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7980, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11719, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7906, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7826, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11471, Bank: 5
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9641, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7050, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11868, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7774, Bank: 3
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6660, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11864, Bank: 4
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11447, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10349, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10073, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8213, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 4
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6702, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9316, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6550, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 7
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10397, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7532, Bank: 2
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7045, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9050, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11416, Bank: 6
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8249, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9760, Bank: 4
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9437, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10498, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 7036, Bank: 4
+Command: 0, Timestamp: 11073, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 7706, Bank: 7
+Command: 0, Timestamp: 10545, Bank: 6
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6762, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10016, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6463, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 8714, Bank: 0
+Command: 0, Timestamp: 6457, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7453, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6792, Bank: 5
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10152, Bank: 5
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11476, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9430, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:44:30
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 06:16:45
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-sim_seconds 51.357853 # Number of seconds simulated
-sim_ticks 51357853367000 # Number of ticks simulated
-final_tick 51357853367000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.397579 # Number of seconds simulated
+sim_ticks 51397578885000 # Number of ticks simulated
+final_tick 51397578885000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 254475 # Simulator instruction rate (inst/s)
-host_op_rate 295745 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 14267482520 # Simulator tick rate (ticks/s)
-host_mem_usage 733332 # Number of bytes of host memory used
-host_seconds 3599.64 # Real time elapsed on the host
-sim_insts 916019679 # Number of instructions simulated
-sim_ops 1064576900 # Number of ops (including micro ops) simulated
+host_inst_rate 213094 # Simulator instruction rate (inst/s)
+host_op_rate 250423 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 11187167929 # Simulator tick rate (ticks/s)
+host_mem_usage 682236 # Number of bytes of host memory used
+host_seconds 4594.33 # Real time elapsed on the host
+sim_insts 979026656 # Number of instructions simulated
+sim_ops 1150528336 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 95168 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2358260 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 43599240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 19200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 20160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 451648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5774336 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 28864 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 24640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 1511104 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 8165824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker 62272 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker 59136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 1907392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 14522560 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 410688 # Number of bytes read from this memory
-system.physmem.bytes_read::total 79096764 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2358260 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 451648 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 1511104 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 1907392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6228404 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 67268864 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 187840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 177856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2851188 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 60331016 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 46336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 44800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 415360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 9688384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 76288 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 60224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 1747072 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 13459648 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 113856 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker 106880 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 1985280 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 25411584 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 412224 # Number of bytes read from this memory
+system.physmem.bytes_read::total 117115836 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2851188 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 415360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 1747072 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 1985280 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6998900 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 101778880 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 67289444 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1487 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 77255 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 681251 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 300 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 315 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 7057 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 90224 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 451 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 385 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 23611 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 127591 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker 973 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker 924 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 29803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 226915 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6417 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1276307 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1051076 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 101799460 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 2935 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 2779 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 84957 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 942685 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 724 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 700 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6490 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 151381 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 1192 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 941 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 27298 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 210307 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker 1779 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker 1670 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 31020 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 397056 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6441 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1870355 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1590295 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1053649 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1680 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1853 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 45918 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 848930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 374 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 393 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu3.dtb.walker 1213 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::realview.ide 7997 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1540110 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 45918 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 121275 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_total::cpu0.inst 45918 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu1.itb.walker 393 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.bw_total::cpu3.itb.walker 1151 # Total bandwidth to/from this memory (bytes/s)
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-system.physmem.readReqs 512711 # Number of read requests accepted
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-system.physmem.writeBursts 445331 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 32795328 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 18176 # Total number of bytes read from write queue
-system.physmem.bytesWritten 28499456 # Total number of bytes written to DRAM
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-system.physmem.bytesWrittenSys 28501184 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 284 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 68360 # Number of requests that are neither read nor write
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 11 # Number of times write queue was full causing retry
-system.physmem.totGap 51356853146000 # Total gap between requests
+system.physmem.numWrRetry 15 # Number of times write queue was full causing retry
+system.physmem.totGap 51396578546000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::63 24 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 259364 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 236.325041 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 143.327680 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 277.441771 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 119855 46.21% 46.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 64854 25.01% 71.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 23816 9.18% 80.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 11723 4.52% 84.92% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 8762 3.38% 88.30% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5465 2.11% 90.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4497 1.73% 92.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3594 1.39% 93.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16798 6.48% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 259364 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 24808 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 20.654708 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 12.973882 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-31 22443 90.47% 90.47% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-63 2162 8.71% 99.18% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-95 162 0.65% 99.83% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-127 16 0.06% 99.90% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-159 10 0.04% 99.94% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::160-191 3 0.01% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::192-223 3 0.01% 99.96% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::224-255 3 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-287 2 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::384-415 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::544-575 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::608-639 2 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 24808 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 24808 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.950016 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.268943 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.650949 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 27 0.11% 0.11% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 16 0.06% 0.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 10 0.04% 0.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 35 0.14% 0.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 23050 92.91% 93.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 468 1.89% 95.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 156 0.63% 95.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 288 1.16% 96.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 65 0.26% 97.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 175 0.71% 97.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 65 0.26% 98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 18 0.07% 98.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 53 0.21% 98.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 60 0.24% 98.70% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 15 0.06% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 13 0.05% 98.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 191 0.77% 99.58% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 12 0.05% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 13 0.05% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 46 0.19% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 3 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 3 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.00% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 3 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 11 0.04% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 1 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::156-159 3 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 24808 # Writes before turning the bus around for reads
-system.physmem.totQLat 10667534010 # Total ticks spent queuing
-system.physmem.totMemAccLat 20275540260 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2562135000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20817.67 # Average queueing delay per DRAM burst
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+system.physmem.wrQLenPdf::52 81 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63 37 # What write queue length does an incoming req see
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+system.physmem.bytesPerActivate::mean 255.102976 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 152.689482 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 290.846029 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 173695 44.10% 44.10% # Bytes accessed per row activation
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+system.physmem.bytesPerActivate::256-383 37135 9.43% 77.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 19371 4.92% 82.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 15343 3.90% 86.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 9742 2.47% 88.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 8567 2.17% 91.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6531 1.66% 92.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 28529 7.24% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 393907 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 42633 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 19.534281 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 9.731161 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31 39808 93.37% 93.37% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63 2621 6.15% 99.52% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95 170 0.40% 99.92% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-127 21 0.05% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-159 5 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255 4 0.01% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::352-383 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::544-575 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::608-639 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 42633 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 42633 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.293270 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.880471 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 5.837851 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 31 0.07% 0.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 7 0.02% 0.09% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 18 0.04% 0.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 54 0.13% 0.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 40522 95.05% 95.31% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 728 1.71% 97.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 202 0.47% 97.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 312 0.73% 98.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 57 0.13% 98.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 185 0.43% 98.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 71 0.17% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 15 0.04% 98.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 39 0.09% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 54 0.13% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 14 0.03% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 19 0.04% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 210 0.49% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 11 0.03% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 9 0.02% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 44 0.10% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 4 0.01% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 1 0.00% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 3 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.00% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 11 0.03% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 42633 # Writes before turning the bus around for reads
+system.physmem.totQLat 19475290366 # Total ticks spent queuing
+system.physmem.totMemAccLat 35091134116 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4164225000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 23384.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39567.67 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.64 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.55 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.64 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.55 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 42134.05 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.92 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.92 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.01 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
+system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 10.01 # Average write queue length when enqueuing
-system.physmem.readRowHits 389460 # Number of row buffer hits during reads
-system.physmem.writeRowHits 308905 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.00 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.37 # Row buffer hit rate for writes
-system.physmem.avgGap 53606056.05 # Average gap between requests
-system.physmem.pageHitRate 72.92 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1011233160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 550085250 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2051392200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1470435120 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1181011387995 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 30447742538250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34948731846855 # Total energy per rank (pJ)
-system.physmem_0.averagePower 666.034408 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 48934758214122 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1694731480000 # Time in different power states
+system.physmem.avgWrQLen 13.53 # Average write queue length when enqueuing
+system.physmem.readRowHits 652462 # Number of row buffer hits during reads
+system.physmem.writeRowHits 523738 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 78.34 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.04 # Row buffer hit rate for writes
+system.physmem.avgGap 32727856.47 # Average gap between requests
+system.physmem.pageHitRate 74.91 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 1529501400 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 832833375 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3285765600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 2429740800 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1212289072380 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29739570673500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34275922206015 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.648127 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 48905170971226 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1695288660000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 123339078628 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 169075280274 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 949558680 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 516544875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1945468200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 1415134800 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3314894774880 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1177770817440 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29706179302500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34203671601375 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.620773 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 48939527598915 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1694731480000 # Time in different power states
+system.physmem_1.actEnergy 1448412840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 788411250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3210347400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 2347729920 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3315984618960 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1209778712865 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29729309949000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34262868182235 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.663987 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 48908958102968 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1695288660000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 118558226835 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 165299992532 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 89680 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 89680 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 89680 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 89680 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 89680 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.578670 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -221375171178 -57.87% -57.87% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 603933894750 157.87% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 382558723572 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 65458 84.89% 84.89% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11653 15.11% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 77111 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 89680 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 119866 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 119866 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 119866 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 119866 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 119866 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.652647 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -247578241138 -65.26% -65.26% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 626923323250 165.26% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 379345082112 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 88729 84.84% 84.84% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 15861 15.16% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 104590 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 119866 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 89680 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77111 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 119866 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 104590 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77111 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 166791 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 104590 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 224456 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 70228403 # DTB read hits
-system.cpu0.dtb.read_misses 67978 # DTB read misses
-system.cpu0.dtb.write_hits 59109334 # DTB write hits
-system.cpu0.dtb.write_misses 21702 # DTB write misses
-system.cpu0.dtb.flush_tlb 1217 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 75642766 # DTB read hits
+system.cpu0.dtb.read_misses 89640 # DTB read misses
+system.cpu0.dtb.write_hits 69609144 # DTB write hits
+system.cpu0.dtb.write_misses 30226 # DTB write misses
+system.cpu0.dtb.flush_tlb 1263 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 40606 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 47006 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2912 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 3911 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 7556 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 70296381 # DTB read accesses
-system.cpu0.dtb.write_accesses 59131036 # DTB write accesses
+system.cpu0.dtb.perms_faults 8593 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 75732406 # DTB read accesses
+system.cpu0.dtb.write_accesses 69639370 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 129337737 # DTB hits
-system.cpu0.dtb.misses 89680 # DTB misses
-system.cpu0.dtb.accesses 129427417 # DTB accesses
+system.cpu0.dtb.hits 145251910 # DTB hits
+system.cpu0.dtb.misses 119866 # DTB misses
+system.cpu0.dtb.accesses 145371776 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 52945 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 52945 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 52945 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 52945 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 52945 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 382558723572 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.578782 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -221418129178 -57.88% -57.88% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 603976852750 157.88% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 382558723572 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 46017 94.83% 94.83% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2511 5.17% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 48528 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 57950 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 57950 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 57950 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 57950 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 57950 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 379345082112 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.652788 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -247631753638 -65.28% -65.28% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 626976835750 165.28% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 379345082112 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 50452 94.94% 94.94% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2688 5.06% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 53140 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 52945 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 52945 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 57950 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 57950 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 48528 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 48528 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 101473 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 364915659 # ITB inst hits
-system.cpu0.itb.inst_misses 52945 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 53140 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 53140 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 111090 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 405381622 # ITB inst hits
+system.cpu0.itb.inst_misses 57950 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1217 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1263 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 16331 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 386 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 28384 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 20153 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 452 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 33228 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 364968604 # ITB inst accesses
-system.cpu0.itb.hits 364915659 # DTB hits
-system.cpu0.itb.misses 52945 # DTB misses
-system.cpu0.itb.accesses 364968604 # DTB accesses
-system.cpu0.numCycles 436289438 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 405439572 # ITB inst accesses
+system.cpu0.itb.hits 405381622 # DTB hits
+system.cpu0.itb.misses 57950 # DTB misses
+system.cpu0.itb.accesses 405439572 # DTB accesses
+system.cpu0.numCycles 487302102 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 364774665 # Number of instructions committed
-system.cpu0.committedOps 425727567 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 388492427 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 355504 # Number of float alu accesses
-system.cpu0.num_func_calls 20838410 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 59397900 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 388492427 # number of integer instructions
-system.cpu0.num_fp_insts 355504 # number of float instructions
-system.cpu0.num_int_register_reads 563346906 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 307286794 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 569525 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 310180 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 98350677 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 98136627 # number of times the CC registers were written
-system.cpu0.num_mem_refs 129410259 # number of memory refs
-system.cpu0.num_load_insts 70285041 # Number of load instructions
-system.cpu0.num_store_insts 59125218 # Number of store instructions
-system.cpu0.num_idle_cycles 425895176.866435 # Number of idle cycles
-system.cpu0.num_busy_cycles 10394261.133565 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.023824 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.976176 # Percentage of idle cycles
-system.cpu0.Branches 85458268 # Number of branches fetched
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 17144 # number of quiesce instructions executed
+system.cpu0.committedInsts 405220560 # Number of instructions committed
+system.cpu0.committedOps 476699664 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 436776878 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 371179 # Number of float alu accesses
+system.cpu0.num_func_calls 23615839 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 62442452 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 436776878 # number of integer instructions
+system.cpu0.num_fp_insts 371179 # number of float instructions
+system.cpu0.num_int_register_reads 647764481 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 347118708 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 591811 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 329388 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 109017876 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 108807189 # number of times the CC registers were written
+system.cpu0.num_mem_refs 145355316 # number of memory refs
+system.cpu0.num_load_insts 75721514 # Number of load instructions
+system.cpu0.num_store_insts 69633802 # Number of store instructions
+system.cpu0.num_idle_cycles 473916691.596574 # Number of idle cycles
+system.cpu0.num_busy_cycles 13385410.403426 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.027468 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.972532 # Percentage of idle cycles
+system.cpu0.Branches 90584626 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 295583613 69.39% 69.39% # Class of executed instruction
-system.cpu0.op_class::IntMult 876793 0.21% 69.60% # Class of executed instruction
-system.cpu0.op_class::IntDiv 40797 0.01% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 48752 0.01% 69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.62% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.62% # Class of executed instruction
-system.cpu0.op_class::MemRead 70285041 16.50% 86.12% # Class of executed instruction
-system.cpu0.op_class::MemWrite 59125218 13.88% 100.00% # Class of executed instruction
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+system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu0.op_class::MemRead 75721514 15.88% 85.40% # Class of executed instruction
+system.cpu0.op_class::MemWrite 69633802 14.60% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 425960214 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 19395 # number of quiesce instructions executed
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20143 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39118 # number of overall MSHR uncacheable misses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17078837500 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 24381845122 # number of WriteLineReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 623794000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 1175051500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2264099500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 75023758792 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 140065942292 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1196510000 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7301874963 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033545 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.034905 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.033387 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015293 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015147 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.015678 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009023 # mshr miss rate for WriteReq accesses
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.773740 # mshr miss rate for SoftPFReq accesses
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+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.735027 # mshr miss rate for WriteLineReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056390 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056797 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.056239 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.033474 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000001 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses
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+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025662 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.025185 # mshr miss rate for demand accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.029559 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.017467 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16067.320087 # average ReadReq mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17991.717311 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17145.486754 # average ReadReq mshr miss latency
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+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48289.929141 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 58904.363645 # average WriteReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20002.905196 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 18288.134922 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18687.903355 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 39087.215016 # average WriteLineReq mshr miss latency
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+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 47636.162682 # average WriteLineReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14615.262060 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 15144.563018 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184849.575535 # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 186662.788563 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 15725711 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.971450 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 600346119 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 15726223 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 38.174845 # Average number of references to valid blocks.
+system.cpu0.icache.tags.replacements 16734603 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.971494 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 650477960 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 16735115 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 38.869046 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 11779377500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 478.711386 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 2.924757 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 22.726644 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst 7.608663 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_percent::total 0.999944 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 74 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 632161102 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 632161102 # Number of data accesses
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-system.cpu0.icache.overall_hits::cpu3.inst 56555527 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 16088683 # number of ReadReq misses
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-system.cpu0.icache.demand_misses::cpu2.inst 3871552 # number of demand (read+write) misses
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-system.cpu0.icache.demand_misses::total 16088683 # number of demand (read+write) misses
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-system.cpu0.icache.overall_misses::cpu2.inst 3871552 # number of overall misses
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-system.cpu0.icache.overall_misses::total 16088683 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22610912000 # number of ReadReq miss cycles
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-system.cpu0.icache.ReadReq_miss_latency::total 143159898311 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_miss_latency::cpu3.inst 67287512311 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 143159898311 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::total 143159898311 # number of overall miss cycles
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+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.082047 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.016038 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12763.688775 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12763.688775 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12437.093740 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12812.047851 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12845.948102 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12763.688775 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 31829 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 31829 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4517 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23366 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 4 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 31825 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 1.131186 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 163.233809 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-2047 31823 99.99% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 42213 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 42213 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6241 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 31075 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 42204 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.853000 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 141.748477 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-2047 42202 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::26624-28671 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 31825 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 27887 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 24957.507082 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 21503.440195 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16346.397027 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 27726 99.42% 99.42% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.01% 99.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 135 0.48% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 2 0.01% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 12 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkWaitTime::total 42204 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 37325 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 26882.732753 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 23412.636165 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 18338.779624 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 37004 99.14% 99.14% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2 0.01% 99.15% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 275 0.74% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 7 0.02% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 19 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 27887 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples -2390831336 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 1.421124 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1006835500 -42.11% -42.11% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 -3397666836 142.11% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total -2390831336 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 23366 83.80% 83.80% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 4517 16.20% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 27883 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31829 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkCompletionTime::total 37325 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2908388356 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.649897 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.477002 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1018236500 35.01% 35.01% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 1890151856 64.99% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2908388356 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 31075 83.28% 83.28% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 6241 16.72% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 37316 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 42213 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31829 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27883 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 42213 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 37316 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27883 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 59712 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 37316 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 79529 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 22434815 # DTB read hits
-system.cpu1.dtb.read_misses 24397 # DTB read misses
-system.cpu1.dtb.write_hits 18279230 # DTB write hits
-system.cpu1.dtb.write_misses 7432 # DTB write misses
-system.cpu1.dtb.flush_tlb 1208 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 23441762 # DTB read hits
+system.cpu1.dtb.read_misses 32033 # DTB read misses
+system.cpu1.dtb.write_hits 21401339 # DTB write hits
+system.cpu1.dtb.write_misses 10180 # DTB write misses
+system.cpu1.dtb.flush_tlb 1255 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 18079 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 20769 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 971 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 1303 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 2561 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 22459212 # DTB read accesses
-system.cpu1.dtb.write_accesses 18286662 # DTB write accesses
+system.cpu1.dtb.perms_faults 2968 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 23473795 # DTB read accesses
+system.cpu1.dtb.write_accesses 21411519 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 40714045 # DTB hits
-system.cpu1.dtb.misses 31829 # DTB misses
-system.cpu1.dtb.accesses 40745874 # DTB accesses
+system.cpu1.dtb.hits 44843101 # DTB hits
+system.cpu1.dtb.misses 42213 # DTB misses
+system.cpu1.dtb.accesses 44885314 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 20237 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 20237 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 921 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17876 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 20237 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 20237 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 20237 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 18797 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 28270.362292 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 25022.223556 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18368.247187 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 18619 99.05% 99.05% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 2 0.01% 99.06% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 152 0.81% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 5 0.03% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 10 0.05% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 18797 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 21791 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 21791 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1072 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 19067 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 21791 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 21791 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 21791 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 20139 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29400.094344 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 25404.974001 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 23277.059653 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 19797 98.30% 98.30% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 293 1.45% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 9 0.04% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 20 0.10% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.07% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 20139 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 17876 95.10% 95.10% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 921 4.90% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 18797 # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::4K 19067 94.68% 94.68% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 1072 5.32% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 20139 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20237 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20237 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 21791 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 21791 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18797 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18797 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 39034 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 115530405 # ITB inst hits
-system.cpu1.itb.inst_misses 20237 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 20139 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 20139 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 41930 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 125648425 # ITB inst hits
+system.cpu1.itb.inst_misses 21791 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1208 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1255 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 5264 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 133 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 13570 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 6610 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 146 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 15047 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 115550642 # ITB inst accesses
-system.cpu1.itb.hits 115530405 # DTB hits
-system.cpu1.itb.misses 20237 # DTB misses
-system.cpu1.itb.accesses 115550642 # DTB accesses
-system.cpu1.numCycles 1208095250 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 125670216 # ITB inst accesses
+system.cpu1.itb.hits 125648425 # DTB hits
+system.cpu1.itb.misses 21791 # DTB misses
+system.cpu1.itb.accesses 125670216 # DTB accesses
+system.cpu1.numCycles 1254117353 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 115450057 # Number of instructions committed
-system.cpu1.committedOps 134166441 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 122283306 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 117326 # Number of float alu accesses
-system.cpu1.num_func_calls 6388598 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 19121650 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 122283306 # number of integer instructions
-system.cpu1.num_fp_insts 117326 # number of float instructions
-system.cpu1.num_int_register_reads 174904532 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 96587788 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 193112 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 90280 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 31170492 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 31100176 # number of times the CC registers were written
-system.cpu1.num_mem_refs 40711221 # number of memory refs
-system.cpu1.num_load_insts 22433949 # Number of load instructions
-system.cpu1.num_store_insts 18277272 # Number of store instructions
-system.cpu1.num_idle_cycles 1181365230.793780 # Number of idle cycles
-system.cpu1.num_busy_cycles 26730019.206220 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.022126 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.977874 # Percentage of idle cycles
-system.cpu1.Branches 27316623 # Number of branches fetched
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu1.committedInsts 125557631 # Number of instructions committed
+system.cpu1.committedOps 147479999 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 135255426 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 113335 # Number of float alu accesses
+system.cpu1.num_func_calls 7243553 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 19326205 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 135255426 # number of integer instructions
+system.cpu1.num_fp_insts 113335 # number of float instructions
+system.cpu1.num_int_register_reads 197658337 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 107430286 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 186014 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 88856 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 33354822 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 33290251 # number of times the CC registers were written
+system.cpu1.num_mem_refs 44840861 # number of memory refs
+system.cpu1.num_load_insts 23441337 # Number of load instructions
+system.cpu1.num_store_insts 21399524 # Number of store instructions
+system.cpu1.num_idle_cycles 1222996834.683689 # Number of idle cycles
+system.cpu1.num_busy_cycles 31120518.316311 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.024815 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.975185 # Percentage of idle cycles
+system.cpu1.Branches 28029112 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 93240195 69.45% 69.45% # Class of executed instruction
-system.cpu1.op_class::IntMult 272528 0.20% 69.66% # Class of executed instruction
-system.cpu1.op_class::IntDiv 10833 0.01% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 11970 0.01% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu1.op_class::MemRead 22433949 16.71% 86.39% # Class of executed instruction
-system.cpu1.op_class::MemWrite 18277272 13.61% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 102409853 69.40% 69.40% # Class of executed instruction
+system.cpu1.op_class::IntMult 296498 0.20% 69.60% # Class of executed instruction
+system.cpu1.op_class::IntDiv 11247 0.01% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 12292 0.01% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction
+system.cpu1.op_class::MemRead 23441337 15.88% 85.50% # Class of executed instruction
+system.cpu1.op_class::MemWrite 21399524 14.50% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 134246789 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 43822181 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 31010848 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 2006659 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 32869256 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 23105809 # Number of BTB hits
+system.cpu1.op_class::total 147570793 # Class of executed instruction
+system.cpu2.branchPred.lookups 45471146 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 31973875 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 2129408 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 32992156 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 23695609 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 70.296112 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 4850903 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 329695 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 71.821948 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 5443991 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 364384 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 93863 # Table walker walks requested
-system.cpu2.dtb.walker.walksLong 93863 # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 6661 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29634 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 93863 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 93863 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 93863 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 36295 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 24894.765119 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 21575.810526 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 16144.893393 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-65535 36098 99.46% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-196607 162 0.45% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-262143 6 0.02% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-327679 14 0.04% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::327680-393215 6 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::393216-458751 7 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 36295 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks 113177 # Table walker walks requested
+system.cpu2.dtb.walker.walksLong 113177 # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 8706 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 39954 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 113177 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 113177 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 113177 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 48660 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 26968.937526 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 23542.983422 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 19014.556180 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-65535 48252 99.16% 99.16% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-196607 346 0.71% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-262143 8 0.02% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-327679 19 0.04% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::393216-458751 17 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 48660 # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walksPending::samples 2000225500 # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::0 2000225500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.dtb.walker.walksPending::total 2000225500 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 29634 81.65% 81.65% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M 6661 18.35% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 36295 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 93863 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkPageSizes::4K 39954 82.11% 82.11% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M 8706 17.89% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 48660 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 113177 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 93863 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36295 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 113177 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 48660 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36295 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 130158 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 48660 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 161837 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 31221716 # DTB read hits
-system.cpu2.dtb.read_misses 78321 # DTB read misses
-system.cpu2.dtb.write_hits 24527548 # DTB write hits
-system.cpu2.dtb.write_misses 15542 # DTB write misses
-system.cpu2.dtb.flush_tlb 1208 # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits 32304432 # DTB read hits
+system.cpu2.dtb.read_misses 94453 # DTB read misses
+system.cpu2.dtb.write_hits 28220489 # DTB write hits
+system.cpu2.dtb.write_misses 18724 # DTB write misses
+system.cpu2.dtb.flush_tlb 1254 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 21789 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 2014 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 25531 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 107 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 2547 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 3746 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 31300037 # DTB read accesses
-system.cpu2.dtb.write_accesses 24543090 # DTB write accesses
+system.cpu2.dtb.perms_faults 4198 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 32398885 # DTB read accesses
+system.cpu2.dtb.write_accesses 28239213 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 55749264 # DTB hits
-system.cpu2.dtb.misses 93863 # DTB misses
-system.cpu2.dtb.accesses 55843127 # DTB accesses
+system.cpu2.dtb.hits 60524921 # DTB hits
+system.cpu2.dtb.misses 113177 # DTB misses
+system.cpu2.dtb.accesses 60638098 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 27202 # Table walker walks requested
-system.cpu2.itb.walker.walksLong 27202 # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1812 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22525 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 27202 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 27202 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 27202 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 24337 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 28096.416978 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 24969.362897 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 17267.916673 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767 12983 53.35% 53.35% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535 11116 45.68% 99.02% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839 182 0.75% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607 36 0.15% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375 2 0.01% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::262144-294911 10 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::393216-425983 4 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 24337 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walks 29761 # Table walker walks requested
+system.cpu2.itb.walker.walksLong 29761 # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1942 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3 24191 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 29761 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 29761 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 29761 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 26133 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 29367.313359 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25512.670377 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 21362.014142 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767 13922 53.27% 53.27% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535 11740 44.92% 98.20% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303 1 0.00% 98.20% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839 361 1.38% 99.58% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.25% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375 4 0.02% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143 6 0.02% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911 20 0.08% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679 6 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::393216-425983 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 26133 # Table walker service (enqueue to completion) latency
system.cpu2.itb.walker.walksPending::samples 2000197500 # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::0 2000197500 100.00% 100.00% # Table walker pending requests distribution
system.cpu2.itb.walker.walksPending::total 2000197500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 22525 92.55% 92.55% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M 1812 7.45% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 24337 # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::4K 24191 92.57% 92.57% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M 1942 7.43% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 26133 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27202 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27202 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 29761 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 29761 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24337 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24337 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 51539 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 74458235 # ITB inst hits
-system.cpu2.itb.inst_misses 27202 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 26133 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 26133 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 55894 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 78881959 # ITB inst hits
+system.cpu2.itb.inst_misses 29761 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 1208 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb 1254 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 6877 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 171 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 16288 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid 8683 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 195 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 18937 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 55804 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 67145 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 74485437 # ITB inst accesses
-system.cpu2.itb.hits 74458235 # DTB hits
-system.cpu2.itb.misses 27202 # DTB misses
-system.cpu2.itb.accesses 74485437 # DTB accesses
-system.cpu2.numCycles 6814615454 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 78911720 # ITB inst accesses
+system.cpu2.itb.hits 78881959 # DTB hits
+system.cpu2.itb.misses 29761 # DTB misses
+system.cpu2.itb.accesses 78911720 # DTB accesses
+system.cpu2.numCycles 7033284242 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 154831636 # Number of instructions committed
-system.cpu2.committedOps 179800875 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 13497272 # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends 1503 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 95900032594 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 44.013069 # CPI: cycles per instruction
-system.cpu2.ipc 0.022721 # IPC: instructions per cycle
+system.cpu2.committedInsts 166119965 # Number of instructions committed
+system.cpu2.committedOps 194630787 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 16695727 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 1592 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 95760838731 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 42.338585 # CPI: cycles per instruction
+system.cpu2.ipc 0.023619 # IPC: instructions per cycle
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 289096275 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 6525519179 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 86474104 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 60464005 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 3334878 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 62765880 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 44403586 # Number of BTB hits
+system.cpu2.tickCycles 311878847 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 6721405395 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 81889340 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 56169669 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 3380866 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 55493963 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 40219158 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 70.744784 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 9643745 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 102837 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 72.474835 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 10439836 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 109057 # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 507978 # Table walker walks requested
-system.cpu3.dtb.walker.walksLong 507978 # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8239 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 50131 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 318118 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 189860 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 2312.543453 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 14225.767965 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535 188735 99.41% 99.41% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071 609 0.32% 99.73% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607 339 0.18% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143 67 0.04% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679 60 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215 19 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::393216-458751 16 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287 13 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 189860 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 237967 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 22746.445936 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 18445.918313 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 18699.946785 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535 233152 97.98% 97.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3733 1.57% 99.55% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607 782 0.33% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143 40 0.02% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215 78 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751 40 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 237967 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -31430994140 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 0.113026 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -32002753640 101.82% 101.82% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7 312906500 -1.00% 100.82% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11 109321000 -0.35% 100.48% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15 69521000 -0.22% 100.25% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19 26278000 -0.08% 100.17% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23 15239000 -0.05% 100.12% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27 14010000 -0.04% 100.08% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31 20193000 -0.06% 100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35 4061500 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39 204000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43 20000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47 4000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51 1500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -31430994140 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 50131 85.88% 85.88% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M 8239 14.12% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 58370 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 507978 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walks 587832 # Table walker walks requested
+system.cpu3.dtb.walker.walksLong 587832 # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 11030 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 61410 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 367052 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 220780 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 2589.344596 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 16088.611072 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535 219110 99.24% 99.24% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071 781 0.35% 99.60% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607 609 0.28% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143 97 0.04% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679 110 0.05% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::393216-458751 21 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::458752-524287 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 220780 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 282413 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 23694.059764 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 19376.224176 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 20061.278653 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-65535 276792 98.01% 98.01% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3971 1.41% 99.42% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-196607 1088 0.39% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-262143 102 0.04% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-327679 289 0.10% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-393215 71 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-458751 75 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-524287 16 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::524288-589823 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::589824-655359 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 282413 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -34655191100 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean -0.302186 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -35339735100 101.98% 101.98% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7 378573500 -1.09% 100.88% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11 130659500 -0.38% 100.51% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15 81429500 -0.23% 100.27% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19 31558000 -0.09% 100.18% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23 16139000 -0.05% 100.13% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27 19404500 -0.06% 100.08% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31 22341500 -0.06% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35 4213500 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39 186000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43 24000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47 5000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51 6000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::52-55 2500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::56-59 1500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -34655191100 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 61410 84.77% 84.77% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M 11030 15.23% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 72440 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 587832 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 507978 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58370 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 587832 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 72440 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58370 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 566348 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 72440 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 660272 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 67144172 # DTB read hits
-system.cpu3.dtb.read_misses 346038 # DTB read misses
-system.cpu3.dtb.write_hits 45597024 # DTB write hits
-system.cpu3.dtb.write_misses 161940 # DTB write misses
-system.cpu3.dtb.flush_tlb 1207 # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits 65734744 # DTB read hits
+system.cpu3.dtb.read_misses 407673 # DTB read misses
+system.cpu3.dtb.write_hits 50830095 # DTB write hits
+system.cpu3.dtb.write_misses 180159 # DTB write misses
+system.cpu3.dtb.flush_tlb 1253 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 30283 # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults 73 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 4849 # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries 34753 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 86 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 6443 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 33322 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 67490210 # DTB read accesses
-system.cpu3.dtb.write_accesses 45758964 # DTB write accesses
+system.cpu3.dtb.perms_faults 35079 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 66142417 # DTB read accesses
+system.cpu3.dtb.write_accesses 51010254 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 112741196 # DTB hits
-system.cpu3.dtb.misses 507978 # DTB misses
-system.cpu3.dtb.accesses 113249174 # DTB accesses
+system.cpu3.dtb.hits 116564839 # DTB hits
+system.cpu3.dtb.misses 587832 # DTB misses
+system.cpu3.dtb.accesses 117152671 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 60738 # Table walker walks requested
-system.cpu3.itb.walker.walksLong 60738 # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1986 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42002 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 8255 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 52483 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1658.003544 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 10682.399901 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767 51962 99.01% 99.01% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535 312 0.59% 99.60% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303 51 0.10% 99.70% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.78% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839 81 0.15% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607 17 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::393216-425983 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 52483 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 52243 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 29328.072660 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 24939.652289 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 21269.473767 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767 27773 53.16% 53.16% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535 23452 44.89% 98.05% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303 257 0.49% 98.54% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071 44 0.08% 98.63% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839 455 0.87% 99.50% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607 157 0.30% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375 28 0.05% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143 20 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911 27 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679 13 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::425984-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 52243 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -31433784640 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean 0.872286 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::stdev 0.329149 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 -3971528800 12.63% 12.63% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 -27500486840 87.49% 100.12% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 33846500 -0.11% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 4000500 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 384000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -31433784640 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 42002 95.49% 95.49% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M 1986 4.51% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 43988 # Table walker page sizes translated
+system.cpu3.itb.walker.walks 63234 # Table walker walks requested
+system.cpu3.itb.walker.walksLong 63234 # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2 2096 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3 42908 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 8590 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 54644 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 2021.164263 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 13009.185259 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767 53981 98.79% 98.79% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535 301 0.55% 99.34% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303 60 0.11% 99.45% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071 76 0.14% 99.59% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839 174 0.32% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607 22 0.04% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375 8 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 54644 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 53594 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 30266.951524 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 25142.604210 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 25912.141235 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-65535 52174 97.35% 97.35% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-131071 327 0.61% 97.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-196607 902 1.68% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-262143 65 0.12% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-327679 86 0.16% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-393215 19 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::393216-458751 14 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::524288-589823 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 53594 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -34657916600 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 0.961535 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev 0.183175 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -1283225616 3.70% 3.70% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -33417551984 96.42% 100.12% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 37526500 -0.11% 100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 4293000 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 605000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 220500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6 216000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -34657916600 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 42908 95.34% 95.34% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M 2096 4.66% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 45004 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 60738 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 60738 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 63234 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 63234 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43988 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43988 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 104726 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 61673296 # ITB inst hits
-system.cpu3.itb.inst_misses 60738 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 45004 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 45004 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 108238 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 57820095 # ITB inst hits
+system.cpu3.itb.inst_misses 63234 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.flush_tlb 1207 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb 1253 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid 10894 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid 329 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 23902 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid 13974 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid 340 # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries 26508 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 114610 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 125417 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 61734034 # ITB inst accesses
-system.cpu3.itb.hits 61673296 # DTB hits
-system.cpu3.itb.misses 60738 # DTB misses
-system.cpu3.itb.accesses 61734034 # DTB accesses
-system.cpu3.numCycles 387266719 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 57883329 # ITB inst accesses
+system.cpu3.itb.hits 57820095 # DTB hits
+system.cpu3.itb.misses 63234 # DTB misses
+system.cpu3.itb.accesses 57883329 # DTB accesses
+system.cpu3.numCycles 434126905 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 147097588 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 357588328 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 86474104 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 54047331 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 217420350 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 7531775 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 1493858 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 6577 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 1847 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 2904102 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 100892 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 5652 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 61540793 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 2049174 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 24233 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 372796591 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.109243 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.309692 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 146156253 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 363700570 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 81889340 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 50658994 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 264117346 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 7731870 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 1657260 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 10621 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 2103 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 3389024 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 101744 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 6028 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 57676698 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 2068277 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 25207 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 419306139 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.016419 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.270112 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 281372813 75.48% 75.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 14372234 3.86% 79.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 10265019 2.75% 82.08% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 7499968 2.01% 84.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 21772422 5.84% 89.94% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 5084969 1.36% 91.30% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 5491693 1.47% 92.77% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 4844554 1.30% 94.07% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 22092919 5.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 329556532 78.60% 78.60% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 11088732 2.64% 81.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 11228658 2.68% 83.92% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 8092801 1.93% 85.85% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 18140495 4.33% 90.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 5492721 1.31% 91.48% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 6039069 1.44% 92.92% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 5230958 1.25% 94.17% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 24436173 5.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 372796591 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.223293 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.923364 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 121849508 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 170403265 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 70427838 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 7160823 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2953176 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 13216170 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 824708 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 387980290 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 2540688 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 2953176 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 125989175 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 14295648 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 134676071 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 73352513 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 21527795 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 379587949 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 66831 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 1271643 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 1003345 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 11147601 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents 2215 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 363999702 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 575721975 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 441176724 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 501598 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 310075973 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 53923724 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 7927696 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 6812130 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 39656771 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 65059563 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 47956782 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 7328499 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 8072218 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 362054747 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7911785 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 361524933 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 476222 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 45084510 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 28958350 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 197452 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 372796591 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.969765 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.646815 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 419306139 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.188630 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.837775 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 117967967 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 225080995 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 64189505 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 9003410 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 3062237 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 11922856 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 815112 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 398264937 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 2526332 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 3062237 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 122799246 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 19956782 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 172569750 # count of cycles rename stalled for serializing inst
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+system.cpu3.rename.UnblockCycles 32663221 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 389247398 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 82681 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1469691 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 1381042 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 19259922 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents 2209 # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands 374365889 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 605949673 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 460740509 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 465469 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 317859037 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 56506847 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 10256222 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 9051847 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 50890020 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 62384560 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 53396526 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 8272508 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 8814741 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 368973435 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 10287007 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 371458257 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 527403 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 47542551 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 30606523 # Number of squashed operands that are examined and possibly removed from graph
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+system.cpu3.iq.issued_per_cycle::mean 0.885888 # Number of insts issued each cycle
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system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 227072164 60.91% 60.91% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 63499277 17.03% 77.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 26503560 7.11% 85.05% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 19490025 5.23% 90.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 15060105 4.04% 94.32% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 9087170 2.44% 96.76% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 6095598 1.64% 98.39% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 3610933 0.97% 99.36% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 2377759 0.64% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 272370865 64.96% 64.96% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 63755387 15.20% 80.16% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 26527410 6.33% 86.49% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 18802792 4.48% 90.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 14265193 3.40% 94.38% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 9871415 2.35% 96.73% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 6899561 1.65% 98.38% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 4083667 0.97% 99.35% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 2729849 0.65% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 372796591 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 419306139 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 1687705 25.88% 25.88% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 16239 0.25% 26.13% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 1469 0.02% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.15% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 2644056 40.55% 66.70% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 2171786 33.30% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 1874044 25.07% 25.07% # attempts to use FU when none available
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+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.29% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 3115796 41.69% 66.97% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 2468334 33.03% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 19 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 246126710 68.08% 68.08% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 787460 0.22% 68.30% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 40199 0.01% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 173 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 43036 0.01% 68.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.32% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 68327195 18.90% 87.22% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 46200141 12.78% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 252023231 67.85% 67.85% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 873366 0.24% 68.08% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 40952 0.01% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 37311 0.01% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 67010678 18.04% 86.14% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 51472700 13.86% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 361524933 # Type of FU issued
-system.cpu3.iq.rate 0.933530 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 6521255 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.018038 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 1102172941 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 415098174 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 349515725 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 670993 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 333176 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 300023 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 367687576 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 358593 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 2643676 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 371458257 # Type of FU issued
+system.cpu3.iq.rate 0.855644 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 7473910 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.020120 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 1169596628 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 426913403 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 357682131 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 627338 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 312499 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 278370 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 378596824 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 335324 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 2893628 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 9059982 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 11985 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 386621 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 4959688 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 9605329 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 12315 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 430621 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 5363996 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 2122346 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 4168343 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 2422339 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 5589935 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2953176 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 9025973 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 4011376 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 370041408 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 1020577 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 65059563 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 47956782 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 6665282 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 121223 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 3842845 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 386621 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 1507009 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1322517 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 2829526 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 357707316 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 67134694 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 3315560 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 3062237 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 10687906 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 7763233 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 379342357 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 1032736 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 62384560 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 53396526 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 8880600 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 160790 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 7539596 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 430621 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 1536012 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1351234 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 2887246 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 367483062 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 65729081 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 3395466 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 74876 # number of nop insts executed
-system.cpu3.iew.exec_refs 112730172 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 73596465 # Number of branches executed
-system.cpu3.iew.exec_stores 45595478 # Number of stores executed
-system.cpu3.iew.exec_rate 0.923672 # Inst execution rate
-system.cpu3.iew.wb_sent 350496089 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 349815748 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 170914672 # num instructions producing a value
-system.cpu3.iew.wb_consumers 300090920 # num instructions consuming a value
+system.cpu3.iew.exec_nop 81915 # number of nop insts executed
+system.cpu3.iew.exec_refs 116559779 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 68181123 # Number of branches executed
+system.cpu3.iew.exec_stores 50830698 # Number of stores executed
+system.cpu3.iew.exec_rate 0.846488 # Inst execution rate
+system.cpu3.iew.wb_sent 358682036 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 357960501 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 176824720 # num instructions producing a value
+system.cpu3.iew.wb_consumers 308531947 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 0.903294 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.569543 # average fanout of values written-back
+system.cpu3.iew.wb_rate 0.824553 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.573116 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 45110535 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7714333 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 2522004 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 365126198 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.889780 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.821639 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 47576745 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 10066214 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 2576993 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 411229636 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.806649 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.806100 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 241067877 66.02% 66.02% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 60177968 16.48% 82.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 23030537 6.31% 88.81% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 12678452 3.47% 92.28% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 6124253 1.68% 93.96% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 3724103 1.02% 94.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 3468414 0.95% 95.93% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 2157144 0.59% 96.52% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 12697450 3.48% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 288483917 70.15% 70.15% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 61981955 15.07% 85.22% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 20267968 4.93% 90.15% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 9217498 2.24% 92.39% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 6652848 1.62% 94.01% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 4003479 0.97% 94.99% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 3757671 0.91% 95.90% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 2541712 0.62% 96.52% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 14322588 3.48% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 365126198 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 280963321 # Number of instructions committed
-system.cpu3.commit.committedOps 324882017 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 411229636 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 282128500 # Number of instructions committed
+system.cpu3.commit.committedOps 331717886 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 98996674 # Number of memory references committed
-system.cpu3.commit.loads 55999580 # Number of loads committed
-system.cpu3.commit.membars 1980658 # Number of memory barriers committed
-system.cpu3.commit.branches 68831058 # Number of branches committed
-system.cpu3.commit.fp_insts 288600 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 294637419 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 7471816 # Number of function calls committed.
+system.cpu3.commit.refs 100811760 # Number of memory references committed
+system.cpu3.commit.loads 52779230 # Number of loads committed
+system.cpu3.commit.membars 2341382 # Number of memory barriers committed
+system.cpu3.commit.branches 63187183 # Number of branches committed
+system.cpu3.commit.fp_insts 266447 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 304028105 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 8134067 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 225203928 69.32% 69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 613924 0.19% 69.51% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 30363 0.01% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 37128 0.01% 69.53% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 55999580 17.24% 86.77% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 42997094 13.23% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 230158153 69.38% 69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 685246 0.21% 69.59% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 30654 0.01% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.60% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 32073 0.01% 69.61% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.61% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.61% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.61% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 52779230 15.91% 85.52% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 48032530 14.48% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 324882017 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 12697450 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 720404728 # The number of ROB reads
-system.cpu3.rob.rob_writes 747667993 # The number of ROB writes
-system.cpu3.timesIdled 2347863 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 14470128 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 98704132703 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 280963321 # Number of Instructions Simulated
-system.cpu3.committedOps 324882017 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.378353 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.378353 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.725503 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.725503 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 414317420 # number of integer regfile reads
-system.cpu3.int_regfile_writes 245959017 # number of integer regfile writes
-system.cpu3.fp_regfile_reads 580593 # number of floating regfile reads
-system.cpu3.fp_regfile_writes 365724 # number of floating regfile writes
-system.cpu3.cc_regfile_reads 82484676 # number of cc regfile reads
-system.cpu3.cc_regfile_writes 83140356 # number of cc regfile writes
-system.cpu3.misc_regfile_reads 708702435 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 7780128 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40264 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40264 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
+system.cpu3.commit.op_class_0::total 331717886 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 14322588 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 773873016 # The number of ROB reads
+system.cpu3.rob.rob_writes 766677768 # The number of ROB writes
+system.cpu3.timesIdled 2386400 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 14820766 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 98598665590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 282128500 # Number of Instructions Simulated
+system.cpu3.committedOps 331717886 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.538756 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.538756 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.649876 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.649876 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 433777374 # number of integer regfile reads
+system.cpu3.int_regfile_writes 254753352 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 550692 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 344140 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 80727735 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 81413298 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 763399482 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 10252205 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 40277 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40277 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136543 # Transaction distribution
+system.iobus.trans_dist::WriteResp 136543 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47710 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122592 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178025.447849 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 173370.576099 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 177081.501976 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 177063.691290 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 175322.757112 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 171383.232370 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 174644.779897 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 76740 # Transaction distribution
-system.membus.trans_dist::ReadResp 434267 # Transaction distribution
-system.membus.trans_dist::WriteReq 33649 # Transaction distribution
-system.membus.trans_dist::WriteResp 33649 # Transaction distribution
-system.membus.trans_dist::Writeback 1051076 # Transaction distribution
-system.membus.trans_dist::CleanEvict 194214 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 34391 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 34393 # Transaction distribution
-system.membus.trans_dist::ReadExReq 878752 # Transaction distribution
-system.membus.trans_dist::ReadExResp 878752 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 357527 # Transaction distribution
+system.membus.trans_dist::ReadReq 76751 # Transaction distribution
+system.membus.trans_dist::ReadResp 550767 # Transaction distribution
+system.membus.trans_dist::WriteReq 33656 # Transaction distribution
+system.membus.trans_dist::WriteResp 33656 # Transaction distribution
+system.membus.trans_dist::Writeback 1590295 # Transaction distribution
+system.membus.trans_dist::CleanEvict 250132 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 40589 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 40592 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1356297 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1356297 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 474016 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122592 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 61 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6766 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3747318 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 3876721 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 342328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4219049 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6786 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5542839 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5672278 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342541 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 342541 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6014819 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155722 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13532 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139182816 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 139352250 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7292736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7292736 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 146644986 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 1691 # Total snoops (count)
-system.membus.snoop_fanout::samples 2735655 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 211708448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 211877938 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7303680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7303680 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 219181618 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1560 # Total snoops (count)
+system.membus.snoop_fanout::samples 3931023 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2735655 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3931023 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2735655 # Request fanout histogram
-system.membus.reqLayer0.occupancy 67480499 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3931023 # Request fanout histogram
+system.membus.reqLayer0.occupancy 67063498 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1687500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 3012404078 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 4875978841 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2789968901 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4492458378 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 111926505 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 103510165 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 51428395 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 26044342 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 3013 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 2333 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 2333 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 57525316 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 29151092 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 3060 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 2399 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 2399 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 1485574 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 23674636 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33649 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33649 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 7959451 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 17972959 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 43013 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 43018 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1971030 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1971030 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 15726300 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 6468003 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1272625 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1224417 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47261977 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29193320 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 817918 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1719148 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 78992363 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1006650324 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1020855654 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2953520 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6072336 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2036531834 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1644943 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 53692689 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.011673 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.107408 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 1748199 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 26397420 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33656 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33656 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 9662082 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 19582233 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 51062 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 51066 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2478951 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2478951 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 16735129 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 7917622 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1294933 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1246469 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 50288517 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 35153401 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 878892 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2158697 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 88479507 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1071219732 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1236530654 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3178896 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 7750232 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2318679514 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2264699 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 60538896 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.012147 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.109543 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 53065946 98.83% 98.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 626743 1.17% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 59803521 98.79% 98.79% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 735375 1.21% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 53692689 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 20600677992 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 60538896 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 23067770487 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 830192 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 767706 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 15256484341 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 16065319902 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 7870736599 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 9498707196 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 292647751 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 310622695 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 703926527 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 847575032 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000027] Console: colour dummy device 80x25\r
-[ 0.000030] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000032] pid_max: default: 32768 minimum: 301\r
-[ 0.000047] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000048] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000169] hw perfevents: no hardware support available\r
-[ 1.060045] CPU1: failed to come online\r
-[ 2.080096] CPU2: failed to come online\r
-[ 3.100147] CPU3: failed to come online\r
-[ 3.100148] Brought up 1 CPUs\r
-[ 3.100149] SMP: Total of 1 processors activated.\r
-[ 3.100176] devtmpfs: initialized\r
-[ 3.100788] atomic64_test: passed\r
-[ 3.100845] regulator-dummy: no parameters\r
-[ 3.101102] NET: Registered protocol family 16\r
-[ 3.101191] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.101195] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101234] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101235] Serial: AMBA PL011 UART driver\r
-[ 3.101357] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101379] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101541] console [ttyAMA0] enabled\r
-[ 3.101668] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.101706] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.101743] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.101777] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130355] 3V3: 3300 mV \r
-[ 3.130376] vgaarb: loaded\r
-[ 3.130417] SCSI subsystem initialized\r
-[ 3.130486] libata version 3.00 loaded.\r
-[ 3.130569] usbcore: registered new interface driver usbfs\r
-[ 3.130596] usbcore: registered new interface driver hub\r
-[ 3.130650] usbcore: registered new device driver usb\r
-[ 3.130683] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130692] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130711] PTP clock support registered\r
-[ 3.130862] Switched to clocksource arch_sys_counter\r
-[ 3.131801] NET: Registered protocol family 2\r
-[ 3.131900] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131914] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131929] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131942] TCP: reno registered\r
-[ 3.131948] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131960] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131987] NET: Registered protocol family 1\r
-[ 3.132018] RPC: Registered named UNIX socket transport module.\r
-[ 3.132028] RPC: Registered udp transport module.\r
-[ 3.132035] RPC: Registered tcp transport module.\r
-[ 3.132043] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.132054] PCI: CLS 0 bytes, default 64\r
-[ 3.132151] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.132209] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.133926] fuse init (API version 7.23)\r
-[ 3.133982] msgmni has been set to 469\r
-[ 3.135967] io scheduler noop registered\r
-[ 3.136002] io scheduler cfq registered (default)\r
-[ 3.136280] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.136281] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.136283] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.136284] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.136285] pci_bus 0000:00: scanning bus\r
-[ 3.136288] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.136290] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136293] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136309] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.136311] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.136313] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.136315] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.136316] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.136318] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.136320] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.136337] pci_bus 0000:00: fixups for bus\r
-[ 3.136338] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.136340] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.136345] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.136346] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.136349] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.136350] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.136352] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.136354] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.136356] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136358] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.136359] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.136361] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.136363] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.136364] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.136956] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.137115] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.137124] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.137143] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.137321] scsi0 : ata_piix\r
-[ 3.137376] scsi1 : ata_piix\r
-[ 3.137393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137474] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137487] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137508] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137521] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290865] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290866] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290873] ata1.00: configured for UDMA/33\r
-[ 3.290889] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290951] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290958] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290972] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290974] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290981] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.291034] sda: sda1\r
-[ 3.291096] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.411154] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.411169] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.411198] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.411208] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.411238] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.411251] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411374] usbcore: registered new interface driver usb-storage\r
-[ 3.411444] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411624] usbcore: registered new interface driver usbhid\r
-[ 3.411633] usbhid: USB HID core driver\r
-[ 3.411655] TCP: cubic registered\r
-[ 3.411662] NET: Registered protocol family 17\r
-\0[ 3.411877] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411887] devtmpfs: mounted\r
-[ 3.411895] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000014] Console: colour dummy device 80x25\r
+[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000017] pid_max: default: 32768 minimum: 301\r
+[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000026] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000089] hw perfevents: no hardware support available\r
+[ 1.060049] CPU1: failed to come online\r
+[ 2.080100] CPU2: failed to come online\r
+[ 3.100151] CPU3: failed to come online\r
+[ 3.100153] Brought up 1 CPUs\r
+[ 3.100153] SMP: Total of 1 processors activated.\r
+[ 3.100180] devtmpfs: initialized\r
+[ 3.100809] atomic64_test: passed\r
+[ 3.100875] regulator-dummy: no parameters\r
+[ 3.101140] NET: Registered protocol family 16\r
+[ 3.101229] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.101232] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101271] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101273] Serial: AMBA PL011 UART driver\r
+[ 3.101394] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101445] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.101992] console [ttyAMA0] enabled\r
+[ 3.102057] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102083] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102108] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102132] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130359] 3V3: 3300 mV \r
+[ 3.130380] vgaarb: loaded\r
+[ 3.130422] SCSI subsystem initialized\r
+[ 3.130493] libata version 3.00 loaded.\r
+[ 3.130582] usbcore: registered new interface driver usbfs\r
+[ 3.130610] usbcore: registered new interface driver hub\r
+[ 3.130662] usbcore: registered new device driver usb\r
+[ 3.130697] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130706] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130725] PTP clock support registered\r
+[ 3.130894] Switched to clocksource arch_sys_counter\r
+[ 3.131871] NET: Registered protocol family 2\r
+[ 3.131947] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131962] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131979] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131993] TCP: reno registered\r
+[ 3.131999] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132011] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.132042] NET: Registered protocol family 1\r
+[ 3.132076] RPC: Registered named UNIX socket transport module.\r
+[ 3.132086] RPC: Registered udp transport module.\r
+[ 3.132093] RPC: Registered tcp transport module.\r
+[ 3.132101] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.132112] PCI: CLS 0 bytes, default 64\r
+[ 3.132214] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.132264] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.133999] fuse init (API version 7.23)\r
+[ 3.134056] msgmni has been set to 469\r
+[ 3.136080] io scheduler noop registered\r
+[ 3.136117] io scheduler cfq registered (default)\r
+[ 3.136408] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136409] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.136411] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.136412] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.136413] pci_bus 0000:00: scanning bus\r
+[ 3.136416] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.136418] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.136421] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136437] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.136439] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.136441] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.136443] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.136445] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.136458] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.136471] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136530] pci_bus 0000:00: fixups for bus\r
+[ 3.136540] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.136554] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.136581] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.136590] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.136604] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.136613] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.136628] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.136642] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.136656] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.136670] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136683] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.136696] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.136709] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.136721] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.137154] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.137322] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.137323] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.137329] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.137678] scsi0 : ata_piix\r
+[ 3.137822] scsi1 : ata_piix\r
+[ 3.137861] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.137873] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.137983] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.137994] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.138007] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.138017] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290897] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290898] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290904] ata1.00: configured for UDMA/33\r
+[ 3.290921] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290982] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290990] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.291004] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.291005] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.291012] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291065] sda: sda1\r
+[ 3.291127] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.411190] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.411205] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.411235] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.411245] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411276] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411288] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411412] usbcore: registered new interface driver usb-storage\r
+[ 3.411483] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411662] usbcore: registered new interface driver usbhid\r
+[ 3.411671] usbhid: USB HID core driver\r
+[ 3.411696] TCP: cubic registered\r
+[ 3.411703] NET: Registered protocol family 17\r
+\0[ 3.411927] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411937] devtmpfs: mounted\r
+[ 3.411945] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450119] udevd[607]: starting version 182\r
+[ 3.450201] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.543151] random: dd urandom read with 19 bits of entropy available\r
+[ 3.573344] random: dd urandom read with 20 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.681081] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.711112] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
-interrupts=Null
+interrupts=
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:45:15
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 06:29:33
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3 -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-o3
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
---------- Begin Simulation Statistics ----------
-sim_seconds 51.329008 # Number of seconds simulated
-sim_ticks 51329007806000 # Number of ticks simulated
-final_tick 51329007806000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.289289 # Number of seconds simulated
+sim_ticks 51289289109000 # Number of ticks simulated
+final_tick 51289289109000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 122530 # Simulator instruction rate (inst/s)
-host_op_rate 143983 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7088851393 # Simulator tick rate (ticks/s)
-host_mem_usage 738964 # Number of bytes of host memory used
-host_seconds 7240.81 # Real time elapsed on the host
-sim_insts 887219290 # Number of instructions simulated
-sim_ops 1042552088 # Number of ops (including micro ops) simulated
+host_inst_rate 116964 # Simulator instruction rate (inst/s)
+host_op_rate 137448 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6754182467 # Simulator tick rate (ticks/s)
+host_mem_usage 688124 # Number of bytes of host memory used
+host_seconds 7593.71 # Real time elapsed on the host
+sim_insts 888194021 # Number of instructions simulated
+sim_ops 1043742869 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 156608 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 147648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 4011328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 41948256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 137216 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 124672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3256192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 42225192 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 430144 # Number of bytes read from this memory
-system.physmem.bytes_read::total 92437256 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4011328 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory
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system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 401 # Write bandwidth from this memory (bytes/s)
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system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 51329006651000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 13 # Read request sizes (log2)
system.physmem.readPktSize::4 2 # Read request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::384-511 26482 4.70% 77.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 23365 4.15% 81.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12858 2.28% 83.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 13591 2.41% 86.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 8972 1.59% 87.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 68848 12.22% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 563229 # Bytes accessed per row activation
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-system.physmem.rdPerTurnAround::mean 20.570010 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 2 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-6143 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::59392-61439 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 17.444297 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::20-23 1492 2.13% 96.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 215 0.31% 96.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 476 0.68% 97.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 85 0.12% 97.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 378 0.54% 98.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 194 0.28% 98.56% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 70176 # Writes before turning the bus around for reads
-system.physmem.totQLat 41972985964 # Total ticks spent queuing
-system.physmem.totMemAccLat 69039398464 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 7217710000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29076.39 # Average queueing delay per DRAM burst
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+system.physmem.totQLat 42013541205 # Total ticks spent queuing
+system.physmem.totMemAccLat 69035553705 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 7205870000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29152.30 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 47826.39 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 47902.30 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.80 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.53 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.80 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.20 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 9.49 # Average write queue length when enqueuing
-system.physmem.readRowHits 1185538 # Number of row buffer hits during reads
-system.physmem.writeRowHits 918946 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.13 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.07 # Row buffer hit rate for writes
-system.physmem.avgGap 19218811.75 # Average gap between requests
-system.physmem.pageHitRate 78.89 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 2148975360 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1172556000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 5585346000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 3972265920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1240688413800 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29709081656250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34315210484610 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.534456 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 49423456234980 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1713988120000 # Time in different power states
+system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 9.35 # Average write queue length when enqueuing
+system.physmem.readRowHits 1183295 # Number of row buffer hits during reads
+system.physmem.writeRowHits 918857 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.11 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.08 # Row buffer hit rate for writes
+system.physmem.avgGap 19225096.03 # Average gap between requests
+system.physmem.pageHitRate 78.88 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 2114615160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1153807875 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 5490264000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 3925247040 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3349966598160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1237156507125 # Energy for active background per rank (pJ)
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+system.physmem_0.totalEnergy 34288151582610 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.524687 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 49388977684769 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1712661860000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 191563442520 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 187649331731 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2109035880 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1150763625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 5674281600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 3960362160 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3352561271280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1239780982635 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29709877648500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34315114345680 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.532583 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 49424762025236 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1713988120000 # Time in different power states
+system.physmem_1.actEnergy 2140047000 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1167684375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 5750846400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4004756640 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3349966598160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1240738244055 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 29685202677000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 34288970853630 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.540660 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 49383704909692 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1712661860000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 190257652264 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 192921720308 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 1088 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1669 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 131402033 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 89056413 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 5742935 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 89027832 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 64073858 # Number of BTB hits
+system.cpu0.branchPred.lookups 131510280 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 89076411 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 5754624 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 89205696 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 64088886 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 71.970592 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 17186238 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 188408 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 71.843939 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 17216191 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 189076 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 880195 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 880195 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16466 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 89406 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 539518 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 340677 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 2766.077546 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 16593.074042 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 337825 99.16% 99.16% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 1415 0.42% 99.58% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 964 0.28% 99.86% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 183 0.05% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 175 0.05% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 39 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751 38 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::458752-524287 35 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walks 879879 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 879879 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16451 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88924 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 539694 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 340185 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 2660.496495 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 15843.329302 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535 337511 99.21% 99.21% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071 1400 0.41% 99.63% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607 868 0.26% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143 160 0.05% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679 148 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215 35 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287 32 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 340677 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 406676 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 23311.011714 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 18634.861317 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 20757.119040 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 397195 97.67% 97.67% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6941 1.71% 99.38% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1728 0.42% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 125 0.03% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 435 0.11% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 140 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 69 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 34 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 406676 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 373167653756 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.157772 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.693071 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-3 372147551256 99.73% 99.73% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-7 557799500 0.15% 99.88% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-11 204631000 0.05% 99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-15 121085000 0.03% 99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-19 47750000 0.01% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::20-23 25413500 0.01% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::24-27 26015000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::28-31 31058000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::32-35 5928000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::36-39 324500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::40-43 31000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::44-47 25000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::48-51 28000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::52-55 7000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::56-59 7000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 373167653756 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 89406 84.45% 84.45% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 16466 15.55% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 105872 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 880195 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 340185 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 407005 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 23314.236926 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 18617.801732 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 20825.488249 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 397459 97.65% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 7042 1.73% 99.38% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1712 0.42% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 113 0.03% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 415 0.10% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 146 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 68 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::458752-524287 24 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::524288-589823 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 11 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 407005 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 376382023716 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.109107 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.663618 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-3 375374134216 99.73% 99.73% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-7 555470000 0.15% 99.88% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-11 199772500 0.05% 99.93% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-15 117350500 0.03% 99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-19 45444000 0.01% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::20-23 24549500 0.01% 99.98% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::24-27 26272500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::28-31 32439000 0.01% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::32-35 6175500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::36-39 322000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::44-47 35000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::48-51 18000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 376382023716 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 88924 84.39% 84.39% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 16451 15.61% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 105375 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 879879 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 880195 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105872 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 879879 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 105375 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105872 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 986067 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 105375 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 985254 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 104380254 # DTB read hits
-system.cpu0.dtb.read_misses 607183 # DTB read misses
-system.cpu0.dtb.write_hits 80883417 # DTB write hits
-system.cpu0.dtb.write_misses 273012 # DTB write misses
-system.cpu0.dtb.flush_tlb 1104 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 104450342 # DTB read hits
+system.cpu0.dtb.read_misses 607388 # DTB read misses
+system.cpu0.dtb.write_hits 80999803 # DTB write hits
+system.cpu0.dtb.write_misses 272491 # DTB write misses
+system.cpu0.dtb.flush_tlb 1103 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 55971 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 172 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 8743 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 21264 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 532 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 54933 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 199 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9612 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 56844 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 104987437 # DTB read accesses
-system.cpu0.dtb.write_accesses 81156429 # DTB write accesses
+system.cpu0.dtb.perms_faults 55908 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 105057730 # DTB read accesses
+system.cpu0.dtb.write_accesses 81272294 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 185263671 # DTB hits
-system.cpu0.dtb.misses 880195 # DTB misses
-system.cpu0.dtb.accesses 186143866 # DTB accesses
+system.cpu0.dtb.hits 185450145 # DTB hits
+system.cpu0.dtb.misses 879879 # DTB misses
+system.cpu0.dtb.accesses 186330024 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 105005 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 105005 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3046 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71369 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 14507 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 90498 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 1949.556896 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 12931.664385 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767 89434 98.82% 98.82% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535 551 0.61% 99.43% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303 86 0.10% 99.53% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071 107 0.12% 99.65% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839 211 0.23% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607 47 0.05% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911 14 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::327680-360447 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::360448-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 105425 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 105425 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3033 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 71538 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 14522 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 90903 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1916.366897 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 12628.127488 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767 89834 98.82% 98.82% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535 539 0.59% 99.42% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303 99 0.11% 99.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071 130 0.14% 99.67% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839 200 0.22% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607 51 0.06% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375 18 0.02% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 90498 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 88922 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 29750.028115 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 24620.054553 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 24536.459942 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 86625 97.42% 97.42% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 636 0.72% 98.13% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 1404 1.58% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 86 0.10% 99.81% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 126 0.14% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 13 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 88922 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 300108383224 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.830431 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -249135515800 -83.02% -83.02% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 549170051524 182.99% 99.98% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 65847000 0.02% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 6561000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 1119000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::5 120500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::6 200000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 300108383224 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 71369 95.91% 95.91% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 3046 4.09% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 74415 # Table walker page sizes translated
+system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 90903 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 89093 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 29737.628096 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 24673.282560 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 24049.122605 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 86936 97.58% 97.58% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 600 0.67% 98.25% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 1294 1.45% 99.70% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 93 0.10% 99.81% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 133 0.15% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 25 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 89093 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 303340156184 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.819271 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -248434536268 -81.90% -81.90% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 551700406452 181.88% 99.98% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 66884500 0.02% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 6271500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 916000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::5 53500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::6 160500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 303340156184 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 71538 95.93% 95.93% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 3033 4.07% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 74571 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105005 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105005 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 105425 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 105425 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74415 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74415 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 179420 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 94426208 # ITB inst hits
-system.cpu0.itb.inst_misses 105005 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 74571 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 74571 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 179996 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 94464352 # ITB inst hits
+system.cpu0.itb.inst_misses 105425 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1104 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1103 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 21323 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 546 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 41718 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 21264 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 532 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 41067 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 203794 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 204534 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 94531213 # ITB inst accesses
-system.cpu0.itb.hits 94426208 # DTB hits
-system.cpu0.itb.misses 105005 # DTB misses
-system.cpu0.itb.accesses 94531213 # DTB accesses
-system.cpu0.numCycles 693924076 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 94569777 # ITB inst accesses
+system.cpu0.itb.hits 94464352 # DTB hits
+system.cpu0.itb.misses 105425 # DTB misses
+system.cpu0.itb.accesses 94569777 # DTB accesses
+system.cpu0.numCycles 693727147 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 245365223 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 583481750 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 131402033 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 81260096 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 404572474 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 13127390 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 2693259 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 25075 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 5895 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 5426941 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 179188 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 4152 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 94205115 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 3543246 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 41874 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 664835628 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.027383 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.280090 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 245689923 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 583659918 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 131510280 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 81305077 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 403973689 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 13146062 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 2696063 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 24792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 6132 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 5442737 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 182065 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 4382 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 94242396 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 3550844 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 42244 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 664592540 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.028282 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.281038 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 520667894 78.32% 78.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 18098994 2.72% 81.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 18311074 2.75% 83.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 13311384 2.00% 85.79% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 28016067 4.21% 90.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 9084552 1.37% 91.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 9729872 1.46% 92.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 8406845 1.26% 94.10% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 39208946 5.90% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 520383096 78.30% 78.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 18093254 2.72% 81.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 18296207 2.75% 83.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 13332643 2.01% 85.78% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 28010014 4.21% 90.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 9092439 1.37% 91.37% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 9727305 1.46% 92.83% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 8422108 1.27% 94.10% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 39235474 5.90% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 664835628 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.189361 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.840844 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 199358459 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 341820249 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 105168047 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 13323606 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5162847 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 19689498 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 1420951 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 636719093 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 4377127 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5162847 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 206863652 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 31387432 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 259611771 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 110843507 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 50963626 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 621821272 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 119952 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 2228381 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 1945503 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 31637065 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 3952 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 595122984 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 956623907 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 735190096 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 738559 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 501301772 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 93821212 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 14866038 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 12879620 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 74385297 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 100195270 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 85014336 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 13702275 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 14674859 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 590272104 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 14944858 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 591104249 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 830680 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 78609056 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 50293897 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 361003 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 664835628 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.889098 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.627888 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 664592540 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.189571 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.841339 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 199631749 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 341256701 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 105213142 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 13320667 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5167977 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 19724467 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 1425325 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 637042209 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 4387868 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5167977 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 207139071 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 31235122 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 259336821 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 110889608 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 50821415 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 622130396 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 110301 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 2210574 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 1917918 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 31535075 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 3960 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 595274899 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 956990256 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 735490255 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 762145 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 501553477 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 93721422 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 14866567 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 12875390 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 74435077 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 100241817 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 85151630 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 13697674 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 14727627 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 590625310 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 14935431 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 591459977 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 828967 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 78563814 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 50313782 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 364460 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 664592540 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.889959 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.628761 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 433426304 65.19% 65.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 96952426 14.58% 79.78% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 43294447 6.51% 86.29% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 30849550 4.64% 90.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 22862967 3.44% 94.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 15973478 2.40% 96.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 10856280 1.63% 98.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 6404067 0.96% 99.37% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 4216109 0.63% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 433116455 65.17% 65.17% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 96939801 14.59% 79.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 43307418 6.52% 86.27% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 30869552 4.64% 90.92% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 22882943 3.44% 94.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 15965693 2.40% 96.76% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 10866497 1.64% 98.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 6415983 0.97% 99.36% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 4228198 0.64% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 664835628 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 664592540 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 3013815 25.84% 25.84% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 22977 0.20% 26.04% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 2673 0.02% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 4796217 41.12% 67.19% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 3826853 32.81% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 3016734 25.85% 25.85% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 25376 0.22% 26.06% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 2604 0.02% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.08% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 4797053 41.10% 67.18% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 3830581 32.82% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 58 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 401137490 67.86% 67.86% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1467252 0.25% 68.11% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 65623 0.01% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 154 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.12% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 57449 0.01% 68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.13% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 106450027 18.01% 86.14% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 81926148 13.86% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 401312314 67.85% 67.85% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 1456904 0.25% 68.10% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 65858 0.01% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 165 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 4 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 60568 0.01% 68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 106521284 18.01% 86.13% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 82042825 13.87% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 591104249 # Type of FU issued
-system.cpu0.iq.rate 0.851828 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 11662537 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.019730 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1858540164 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 684045272 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 569697611 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 997179 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 495349 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 443319 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 602234444 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 532284 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 4680430 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 591459977 # Type of FU issued
+system.cpu0.iq.rate 0.852583 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 11672350 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.019735 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1858987169 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 684321714 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 570020326 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 1026642 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 511393 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 456189 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 602584344 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 547979 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 4688231 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 15887962 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 20586 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 725982 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 8698150 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 15870823 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 20812 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 719682 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 8709865 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 3921331 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 7846897 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 3916695 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 7873559 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5162847 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 16668961 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 12768791 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 605350499 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 1734594 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 100195270 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 85014336 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 12589274 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 229167 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 12454098 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 725982 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2593635 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 2277415 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 4871050 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 584543415 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 104370380 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 5693430 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 5167977 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 16609605 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 12703167 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 605694561 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 1733726 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 100241817 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 85151630 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 12585145 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 227737 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 12390007 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 719682 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 2598504 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 2279450 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 4877954 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 584896168 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 104440997 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 5696378 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 133537 # number of nop insts executed
-system.cpu0.iew.exec_refs 185253232 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 108623271 # Number of branches executed
-system.cpu0.iew.exec_stores 80882852 # Number of stores executed
-system.cpu0.iew.exec_rate 0.842374 # Inst execution rate
-system.cpu0.iew.wb_sent 571363680 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 570140930 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 281574536 # num instructions producing a value
-system.cpu0.iew.wb_consumers 488934383 # num instructions consuming a value
+system.cpu0.iew.exec_nop 133820 # number of nop insts executed
+system.cpu0.iew.exec_refs 185440040 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 108756194 # Number of branches executed
+system.cpu0.iew.exec_stores 80999043 # Number of stores executed
+system.cpu0.iew.exec_rate 0.843121 # Inst execution rate
+system.cpu0.iew.wb_sent 571697028 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 570476515 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 281622326 # num instructions producing a value
+system.cpu0.iew.wb_consumers 489116164 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.821619 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.575894 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.822336 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.575778 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 78652927 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 14583855 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4341813 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 651404193 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.808420 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.807572 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 78604829 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 14570971 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 4349296 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 651171717 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.809306 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.808418 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 458550730 70.39% 70.39% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 94732366 14.54% 84.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 33042086 5.07% 90.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 15126484 2.32% 92.33% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 10907840 1.67% 94.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 6532170 1.00% 95.01% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 6050361 0.93% 95.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3879708 0.60% 96.53% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 22582448 3.47% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 458185820 70.36% 70.36% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 94765025 14.55% 84.92% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 33137681 5.09% 90.01% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 15077927 2.32% 92.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 10931676 1.68% 94.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 6537456 1.00% 95.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 6054601 0.93% 95.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3871079 0.59% 96.53% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 22610452 3.47% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 651404193 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 448281871 # Number of instructions committed
-system.cpu0.commit.committedOps 526607906 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 651171717 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 448537783 # Number of instructions committed
+system.cpu0.commit.committedOps 526996927 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 160623494 # Number of memory references committed
-system.cpu0.commit.loads 84307308 # Number of loads committed
-system.cpu0.commit.membars 3712250 # Number of memory barriers committed
-system.cpu0.commit.branches 100326253 # Number of branches committed
-system.cpu0.commit.fp_insts 425629 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 483420006 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 13315515 # Number of function calls committed.
+system.cpu0.commit.refs 160812759 # Number of memory references committed
+system.cpu0.commit.loads 84370994 # Number of loads committed
+system.cpu0.commit.membars 3712862 # Number of memory barriers committed
+system.cpu0.commit.branches 100457713 # Number of branches committed
+system.cpu0.commit.fp_insts 437537 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 483805259 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 13348009 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 364753410 69.26% 69.26% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 1133090 0.22% 69.48% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 49128 0.01% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 48742 0.01% 69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.50% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 84307308 16.01% 85.51% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 76316186 14.49% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 364956602 69.25% 69.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 1127311 0.21% 69.47% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 49300 0.01% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.48% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 50913 0.01% 69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 84370994 16.01% 85.49% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 76441765 14.51% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 526607906 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 22582448 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 1230128311 # The number of ROB reads
-system.cpu0.rob.rob_writes 1223973004 # The number of ROB writes
-system.cpu0.timesIdled 4124129 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 29088448 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 48650709972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 448281871 # Number of Instructions Simulated
-system.cpu0.committedOps 526607906 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.547964 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.547964 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.646010 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.646010 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 689327095 # number of integer regfile reads
-system.cpu0.int_regfile_writes 407367655 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 801695 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 483656 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 125240184 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 126404355 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 1208337968 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 14686021 # number of misc regfile writes
-system.cpu0.dcache.tags.replacements 10424389 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.972987 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 299585117 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 10424901 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.737454 # Average number of references to valid blocks.
+system.cpu0.commit.op_class_0::total 526996927 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 22610452 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 1230217301 # The number of ROB reads
+system.cpu0.rob.rob_writes 1224645571 # The number of ROB writes
+system.cpu0.timesIdled 4130146 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 29134607 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 48521219733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 448537783 # Number of Instructions Simulated
+system.cpu0.committedOps 526996927 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.546641 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.546641 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.646562 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.646562 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 689663562 # number of integer regfile reads
+system.cpu0.int_regfile_writes 407539482 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 822896 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 494260 # number of floating regfile writes
+system.cpu0.cc_regfile_reads 125263725 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 126423537 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 1208432146 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 14685746 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 10442064 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.972968 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 299912904 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 10442576 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.720203 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 2716190500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 307.327232 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 204.645755 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.600249 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.399699 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 306.410459 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 205.562509 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.598458 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.401489 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 1321394222 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 1321394222 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 79981443 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 78050702 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 158032145 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 67196950 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 66097721 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 133294671 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 207918 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193439 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 401357 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 180362 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data 144303 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 324665 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1756226 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1719412 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 3475638 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2032769 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1975290 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 4008059 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 147178393 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 144148423 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 291326816 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 147386311 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 144341862 # number of overall hits
-system.cpu0.dcache.overall_hits::total 291728173 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 6301112 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 6119243 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 12420355 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 6289754 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 6328811 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 12618565 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 639748 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 640862 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 1280610 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 612213 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data 625423 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 1237636 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 334540 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 314072 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 648612 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 6 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu1.data 8 # number of StoreCondReq misses
+system.cpu0.dcache.tags.tag_accesses 1323031608 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 1323031608 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 80041652 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 78145564 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 158187216 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 67282411 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 66174015 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 133456426 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208357 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193759 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 402116 # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data 179575 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data 144785 # number of WriteLineReq hits
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17403.449748 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17515.483510 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46382.921472 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46497.701019 # average WriteReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19912.437194 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19745.865824 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 73935.265622 # average WriteLineReq mshr miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14299.638264 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14427.896287 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21437.500000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22714.285714 # average StoreCondReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25439.297287 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24659.336366 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24686.772616 # average overall mshr miss latency
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-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173465.007868 # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169077.320889 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172786.880078 # average WriteReq mshr uncacheable latency
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-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172397.346530 # average overall mshr uncacheable latency
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system.cpu0.icache.tags.warmup_cycle 23717372500 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.overall_mshr_hits::cpu1.inst 601195 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 1224627 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8109390 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7863266 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 15972656 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 8109390 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 7863266 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 15972656 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 8109390 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 7863266 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 15972656 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 625847 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 603161 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 1229008 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 625847 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu1.inst 603161 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 1229008 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 625847 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu1.inst 603161 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 1229008 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8129351 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 7865191 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 15994542 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 8129351 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 7865191 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 15994542 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 8129351 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 7865191 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 15994542 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 13120 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 7526 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 20646 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 13120 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 7526 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 20646 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103682474880 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 99950191908 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 203632666788 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103682474880 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 99950191908 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 203632666788 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103682474880 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 99950191908 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 203632666788 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 103957984374 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 99931045411 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 203889029785 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 103957984374 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 99931045411 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 203889029785 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 103957984374 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 99931045411 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 203889029785 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 960778000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2636240000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1675462000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 960778000 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 2636240000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086012 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.086012 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086094 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085927 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.086012 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12748.829424 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12785.483850 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12711.027696 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12748.829424 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.086272 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085749 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.086014 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.086272 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085749 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.086014 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.086272 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085749 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.086014 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12787.980784 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12705.482348 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12747.412823 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12787.980784 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12705.482348 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12747.412823 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12787.980784 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12705.482348 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12747.412823 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 127702.896341 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 127687.687688 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 127661.174595 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 127687.687688 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 127789270 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 86858303 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 5584682 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 87369575 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 62601289 # Number of BTB hits
+system.cpu1.branchPred.lookups 128002334 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 87000769 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5591841 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 87469952 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 62728816 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 71.651131 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16643705 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 184713 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 71.714703 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 16690428 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 184044 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 886728 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 886728 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16477 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 90200 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 549590 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 337138 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2560.840071 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 15205.071993 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535 334698 99.28% 99.28% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071 1295 0.38% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607 786 0.23% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143 134 0.04% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679 132 0.04% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215 32 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::393216-458751 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::458752-524287 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 888625 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 888625 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 16515 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89516 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 551182 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 337443 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 2618.907490 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 15834.815336 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535 334927 99.25% 99.25% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071 1259 0.37% 99.63% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607 844 0.25% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143 153 0.05% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679 151 0.04% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 337138 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 413502 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23222.124681 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 18719.794007 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 19687.471539 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 404370 97.79% 97.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6829 1.65% 99.44% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1627 0.39% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 122 0.03% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 359 0.09% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 93 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 61 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 23 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 16 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 413502 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 343450342184 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.162233 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.725616 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-3 342433135184 99.70% 99.70% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-7 558046000 0.16% 99.87% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-11 195137000 0.06% 99.92% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-15 122093500 0.04% 99.96% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-19 46703500 0.01% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::20-23 26952500 0.01% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::24-27 27089500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::28-31 34276500 0.01% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::32-35 6435000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::36-39 311500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::40-43 102500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::44-47 19500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::48-51 38500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::52-55 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 343450342184 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 90201 84.55% 84.55% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 16477 15.45% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 106678 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 886728 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 337443 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 414261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 23202.362762 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 18749.985984 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 19280.784036 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 405371 97.85% 97.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 6574 1.59% 99.44% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1705 0.41% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 91 0.02% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 347 0.08% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 109 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::589824-655359 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 414261 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 346681338644 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.164180 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.727467 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-3 345667955144 99.71% 99.71% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-7 547148000 0.16% 99.87% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-11 197378500 0.06% 99.92% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-15 124829500 0.04% 99.96% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-19 46718000 0.01% 99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::20-23 26902000 0.01% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::24-27 29536000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::28-31 34566500 0.01% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::32-35 5689000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::36-39 518500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::40-43 43000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::44-47 27500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::48-51 26500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::52-55 500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 346681338644 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 89517 84.42% 84.42% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 16515 15.58% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 106032 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 888625 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 886728 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106678 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 888625 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106032 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106678 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 993406 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106032 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 994657 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 101925383 # DTB read hits
-system.cpu1.dtb.read_misses 607794 # DTB read misses
-system.cpu1.dtb.write_hits 79659263 # DTB write hits
-system.cpu1.dtb.write_misses 278934 # DTB write misses
-system.cpu1.dtb.flush_tlb 1096 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 102078491 # DTB read hits
+system.cpu1.dtb.read_misses 609526 # DTB read misses
+system.cpu1.dtb.write_hits 79752942 # DTB write hits
+system.cpu1.dtb.write_misses 279099 # DTB write misses
+system.cpu1.dtb.flush_tlb 1097 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 54027 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 180 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 8646 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 21138 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 525 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 54374 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 189 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 9195 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 55500 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 102533177 # DTB read accesses
-system.cpu1.dtb.write_accesses 79938197 # DTB write accesses
+system.cpu1.dtb.perms_faults 57003 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 102688017 # DTB read accesses
+system.cpu1.dtb.write_accesses 80032041 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 181584646 # DTB hits
-system.cpu1.dtb.misses 886728 # DTB misses
-system.cpu1.dtb.accesses 182471374 # DTB accesses
+system.cpu1.dtb.hits 181831433 # DTB hits
+system.cpu1.dtb.misses 888625 # DTB misses
+system.cpu1.dtb.accesses 182720058 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 104027 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 104027 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2965 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70858 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 14434 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 89593 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1868.019823 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 12006.495125 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767 88555 98.84% 98.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535 538 0.60% 99.44% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303 104 0.12% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071 108 0.12% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839 209 0.23% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607 38 0.04% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::229376-262143 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 89593 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 88257 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 29154.191735 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24307.950547 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 23207.189467 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 86230 97.70% 97.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 592 0.67% 98.37% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 1228 1.39% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 107 0.12% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 29 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 88257 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 296203153428 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 1.803727 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 -237987293372 -80.35% -80.35% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 534122343800 180.32% 99.98% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 59128000 0.02% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 7492500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 1022500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 250000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::6 210000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 296203153428 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 70858 95.98% 95.98% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 2965 4.02% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 73823 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 103286 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 103286 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2985 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 70650 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 14185 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 89101 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1880.887981 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 12259.575091 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-65535 88607 99.45% 99.45% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-131071 208 0.23% 99.68% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-196607 245 0.27% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-262143 23 0.03% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-327679 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 89101 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 87820 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 29448.206559 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24574.367788 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 23374.084602 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 85760 97.65% 97.65% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 575 0.65% 98.31% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 1268 1.44% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 74 0.08% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 108 0.12% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 87820 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 303729046684 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 1.808269 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 -245416179168 -80.80% -80.80% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 549075630852 180.78% 99.98% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 61607500 0.02% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 7072500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 899500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::5 15500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 303729046684 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 70650 95.95% 95.95% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 2985 4.05% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 73635 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104027 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104027 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 103286 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 103286 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73823 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73823 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 177850 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 91745725 # ITB inst hits
-system.cpu1.itb.inst_misses 104027 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 73635 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 73635 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 176921 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 91956391 # ITB inst hits
+system.cpu1.itb.inst_misses 103286 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1096 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1097 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 21110 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 40011 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 21138 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 525 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 40049 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 204194 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 202974 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 91849752 # ITB inst accesses
-system.cpu1.itb.hits 91745725 # DTB hits
-system.cpu1.itb.misses 104027 # DTB misses
-system.cpu1.itb.accesses 91849752 # DTB accesses
-system.cpu1.numCycles 682447871 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 92059677 # ITB inst accesses
+system.cpu1.itb.hits 91956391 # DTB hits
+system.cpu1.itb.misses 103286 # DTB misses
+system.cpu1.itb.accesses 92059677 # DTB accesses
+system.cpu1.numCycles 683589124 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 237751767 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 569981698 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 127789270 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 79244994 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 403874148 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 12747214 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 2621326 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 22891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 5452 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 5355964 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 162889 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 2912 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 91518882 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 3441613 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 41515 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 656170682 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.017476 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.271778 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 238009169 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 571176057 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 128002334 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 79419244 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 404719127 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 12774600 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 2616585 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 24222 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 5589 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 5368087 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 160870 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 2610 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 91730802 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 3443412 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 41301 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 657293286 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.017856 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.272002 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 515442690 78.55% 78.55% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 17560626 2.68% 81.23% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 17609646 2.68% 83.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 13074345 1.99% 85.91% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 27836031 4.24% 90.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 8626345 1.31% 91.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 9437454 1.44% 92.90% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 8134103 1.24% 94.14% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 38449442 5.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 516237120 78.54% 78.54% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 17632958 2.68% 81.22% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 17654036 2.69% 83.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 13091323 1.99% 85.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 27900711 4.24% 90.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 8639588 1.31% 91.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 9467175 1.44% 92.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 8151646 1.24% 94.14% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 38518729 5.86% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 656170682 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.187251 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.835202 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 193456459 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 342166734 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 102287783 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 13239744 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 5017523 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 18910299 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 1375576 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 622643781 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 4236982 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 5017523 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 200842686 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 30883178 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 258887608 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 108004065 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 52532870 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 608141114 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 110721 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 2023681 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 1854971 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 33287436 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 3642 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 582179449 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 939040277 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 719307421 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 813140 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 491677026 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 90502418 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 15019602 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 13109435 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 74431382 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 97738010 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 83701683 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 13087583 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 14003001 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 577050532 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 15100250 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 578680532 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 823139 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 76206595 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 48603059 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 352691 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 656170682 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.881905 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.622817 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 657293286 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.187250 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.835555 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 193664291 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 342800105 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 102542010 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 13254966 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 5029491 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 18937376 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 1377136 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 623890493 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 4237673 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 5029491 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 201058836 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 31048942 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 259190035 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 108261392 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 52701935 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 609359225 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 108791 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 2049420 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 1849812 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 33430397 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 3628 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 583294874 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 940667365 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 720819975 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 791427 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 492359028 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 90935841 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 15032233 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 13124059 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 74465076 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 97949385 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 83816258 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 13144575 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 14065563 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 578164482 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 15125943 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 579632592 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 823862 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 76544478 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 48922532 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu1.iq.issued_per_cycle::1 96527772 14.71% 80.05% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 41990375 6.40% 86.45% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 29917551 4.56% 91.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 22305055 3.40% 94.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 15606448 2.38% 96.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 10670315 1.63% 98.41% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 6241457 0.95% 99.36% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 4181851 0.64% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 429426254 65.33% 65.33% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 96715112 14.71% 80.05% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 42097823 6.40% 86.45% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 29977053 4.56% 91.01% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 22357761 3.40% 94.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 15606240 2.37% 96.79% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 10657458 1.62% 98.41% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 6260997 0.95% 99.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 4194588 0.64% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 656170682 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 657293286 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2907149 25.23% 25.23% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 25340 0.22% 25.45% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 2712 0.02% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 2 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.47% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 4700245 40.79% 66.27% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 3886684 33.73% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 2920465 25.31% 25.31% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 23164 0.20% 25.51% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 2858 0.02% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 1 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 4710924 40.83% 66.37% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 3880904 33.63% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 392511580 67.83% 67.83% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1384098 0.24% 68.07% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 66455 0.01% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 76 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 5 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 71678 0.01% 68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 103950145 17.96% 86.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 80696483 13.94% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 393199833 67.84% 67.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1396367 0.24% 68.08% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 66291 0.01% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 69 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 68890 0.01% 68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.10% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 104108183 17.96% 86.06% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 80792947 13.94% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 578680532 # Type of FU issued
-system.cpu1.iq.rate 0.847948 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 11522132 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.019911 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1824781458 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 668482518 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 557668794 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1095559 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 542505 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 489305 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 589617138 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 585515 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 4580122 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 579632592 # Type of FU issued
+system.cpu1.iq.rate 0.847925 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 11538316 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.019906 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 1827853747 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 669983955 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 558625373 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1066901 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 527037 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 476493 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 590600685 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 570212 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 4591636 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 15421998 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 21561 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 678629 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 8522052 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 15509069 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 19434 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 687053 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 8553480 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 3766919 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 7862357 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 3778771 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 7833875 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 5017523 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 16098124 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 12731672 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 592283961 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 1683866 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 97738010 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 83701683 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 12822867 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 226624 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 12419238 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 678629 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 2534874 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2203490 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 4738364 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 572262856 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 101914202 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 5543088 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 5029491 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 16246993 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 12738129 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 593422501 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 1696916 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 97949385 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 83816258 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 12835084 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 232041 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 12419302 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 687053 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 2537334 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2208748 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 4746082 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 573207937 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 102068127 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 5548487 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 133179 # number of nop insts executed
-system.cpu1.iew.exec_refs 181576481 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 105801109 # Number of branches executed
-system.cpu1.iew.exec_stores 79662279 # Number of stores executed
-system.cpu1.iew.exec_rate 0.838544 # Inst execution rate
-system.cpu1.iew.wb_sent 559345130 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 558158099 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 275625677 # num instructions producing a value
-system.cpu1.iew.wb_consumers 478553206 # num instructions consuming a value
+system.cpu1.iew.exec_nop 132076 # number of nop insts executed
+system.cpu1.iew.exec_refs 181824390 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 105934255 # Number of branches executed
+system.cpu1.iew.exec_stores 79756263 # Number of stores executed
+system.cpu1.iew.exec_rate 0.838527 # Inst execution rate
+system.cpu1.iew.wb_sent 560287134 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 559101866 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 276158020 # num instructions producing a value
+system.cpu1.iew.wb_consumers 479351020 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.817877 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.575956 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.817892 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.576108 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 76251521 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 14747559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4228324 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 643144454 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.802221 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.802123 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 76588811 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 14772366 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4233759 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 644213743 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.802134 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.802116 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 453619473 70.53% 70.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 93903191 14.60% 85.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 31983690 4.97% 90.11% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 14866669 2.31% 92.42% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 10513323 1.63% 94.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 6352313 0.99% 95.04% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5895751 0.92% 95.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3796111 0.59% 96.55% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 22213933 3.45% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 454416895 70.54% 70.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 94019038 14.59% 85.13% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 32034419 4.97% 90.11% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 14900535 2.31% 92.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 10532700 1.63% 94.05% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 6339894 0.98% 95.04% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5911008 0.92% 95.95% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3813889 0.59% 96.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 22245365 3.45% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 643144454 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 438937419 # Number of instructions committed
-system.cpu1.commit.committedOps 515944182 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 644213743 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 439656238 # Number of instructions committed
+system.cpu1.commit.committedOps 516745942 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 157495642 # Number of memory references committed
-system.cpu1.commit.loads 82316011 # Number of loads committed
-system.cpu1.commit.membars 3580111 # Number of memory barriers committed
-system.cpu1.commit.branches 97766699 # Number of branches committed
-system.cpu1.commit.fp_insts 469643 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 473710297 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 12866382 # Number of function calls committed.
+system.cpu1.commit.refs 157703093 # Number of memory references committed
+system.cpu1.commit.loads 82440315 # Number of loads committed
+system.cpu1.commit.membars 3590265 # Number of memory barriers committed
+system.cpu1.commit.branches 97880986 # Number of branches committed
+system.cpu1.commit.fp_insts 458119 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 474489741 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 12901444 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 357259636 69.24% 69.24% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 1077544 0.21% 69.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 49642 0.01% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.46% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 61718 0.01% 69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.47% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 82316011 15.95% 85.43% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 75179631 14.57% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 357849627 69.25% 69.25% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 1084383 0.21% 69.46% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 49292 0.01% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.47% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 59547 0.01% 69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.48% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 82440315 15.95% 85.44% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 75262778 14.56% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 515944182 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 22213933 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1209227164 # The number of ROB reads
-system.cpu1.rob.rob_writes 1197436777 # The number of ROB writes
-system.cpu1.timesIdled 3994160 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 26277189 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 52630560458 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 438937419 # Number of Instructions Simulated
-system.cpu1.committedOps 515944182 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.554773 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.554773 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.643181 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.643181 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 675192691 # number of integer regfile reads
-system.cpu1.int_regfile_writes 398302134 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 877858 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 519852 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 122926890 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 124034847 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 1190535376 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 14866281 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40297 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40297 # Transaction distribution
+system.cpu1.commit.op_class_0::total 516745942 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 22245365 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 1211389031 # The number of ROB reads
+system.cpu1.rob.rob_writes 1199768965 # The number of ROB writes
+system.cpu1.timesIdled 3993228 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 26295838 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 52679663676 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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+system.cpu1.committedOps 516745942 # Number of Ops (including micro ops) Simulated
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128598.896608 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 129274.382315 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125312.986646 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135756.274804 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 127425.839552 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 127054.158111 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125237.379558 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136498.049472 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 134938.760227 # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 139645.561265 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139628.885690 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 139637.238009 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 125322.326553 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 130392.772127 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 130944.173004 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 130663.179511 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 145654.928974 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 145047.531143 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 145340.143907 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 136172.442949 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 136439.783200 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 135102.313801 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128620.733249 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 128660.919540 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 125491.363034 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136172.442949 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 128043.437646 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 126941.147379 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125126.981732 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 136439.783200 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 135102.313801 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158412.829145 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158756.104227 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163455.588149 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142425.163332 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165677.684879 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157491.460477 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161239.724605 # average WriteReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163072.300006 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 142422.758279 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165967.041590 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157314.632689 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 161241.289767 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112202.896341 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 161908.742164 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 162228.507998 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 112145.296040 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160370.246085 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 149627.843017 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160097.200775 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 149626.989605 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 54325 # Transaction distribution
-system.membus.trans_dist::ReadResp 466014 # Transaction distribution
-system.membus.trans_dist::WriteReq 33697 # Transaction distribution
-system.membus.trans_dist::WriteResp 33697 # Transaction distribution
-system.membus.trans_dist::Writeback 1223851 # Transaction distribution
-system.membus.trans_dist::CleanEvict 214858 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36602 # Transaction distribution
+system.membus.trans_dist::ReadReq 54323 # Transaction distribution
+system.membus.trans_dist::ReadResp 463989 # Transaction distribution
+system.membus.trans_dist::WriteReq 33696 # Transaction distribution
+system.membus.trans_dist::WriteResp 33696 # Transaction distribution
+system.membus.trans_dist::Writeback 1223443 # Transaction distribution
+system.membus.trans_dist::CleanEvict 213592 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 36616 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 36604 # Transaction distribution
-system.membus.trans_dist::ReadExReq 1014814 # Transaction distribution
-system.membus.trans_dist::ReadExResp 1014814 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 411689 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 36618 # Transaction distribution
+system.membus.trans_dist::ReadExReq 1014298 # Transaction distribution
+system.membus.trans_dist::ReadExResp 1014298 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 409666 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6862 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4279818 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4409460 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342041 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 342041 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4751501 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6856 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4273089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4402725 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342054 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 342054 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4744779 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2148 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13724 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163529836 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 163701542 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7254464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7254464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 170956006 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 2794 # Total snoops (count)
-system.membus.snoop_fanout::samples 3098842 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13712 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 163341292 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 163512986 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7254912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7254912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 170767898 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 2786 # Total snoops (count)
+system.membus.snoop_fanout::samples 3094626 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3098842 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3094626 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3098842 # Request fanout histogram
-system.membus.reqLayer0.occupancy 114250999 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3094626 # Request fanout histogram
+system.membus.reqLayer0.occupancy 113794499 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 50156 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 5591500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 5590500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 8287460048 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 8281023093 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 7742269755 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 7728395442 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 228310464 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 228381503 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks
system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks
system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks
-system.toL2Bus.snoop_filter.tot_requests 53652655 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 27255089 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 4361 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 2133 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 2133 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.tot_requests 53734904 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 27297777 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 4493 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 2110 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 2110 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 2023578 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 25097341 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 9215084 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 18618130 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 45706 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2021207 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 25124422 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 9226509 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 18644458 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 45658 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 14 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 45720 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 2093953 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 2093953 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 15972656 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 7109207 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1337267 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1230603 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47955066 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31500258 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 906342 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2489762 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 82851428 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1023557760 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1100111846 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3042744 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8372064 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2135084414 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 2099930 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 56453563 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 0.014593 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.119915 # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp 45672 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 2103809 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 2103809 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 15994542 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 7116774 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1337512 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1230848 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 48020569 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 31553133 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 908522 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2486966 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 82969190 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1024954048 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1101984346 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3065144 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8363688 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2138367226 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 2094185 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 56528569 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 0.014634 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.120081 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 55629759 98.54% 98.54% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 823804 1.46% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 55701347 98.54% 98.54% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 827222 1.46% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 56453563 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 35456582958 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 56528569 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 35506762964 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1421406 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 1418902 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 24004091061 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 24036893583 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 14485026242 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 14511308139 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 526450560 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 525798129 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 1445956414 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 1444244841 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 19211 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 16329 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000000] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000011] Console: colour dummy device 80x25\r
-[ 0.000013] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000014] pid_max: default: 32768 minimum: 301\r
-[ 0.000021] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000022] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000100] hw perfevents: no hardware support available\r
-[ 1.060050] CPU1: failed to come online\r
+[ 0.000014] Console: colour dummy device 80x25\r
+[ 0.000016] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000017] pid_max: default: 32768 minimum: 301\r
+[ 0.000025] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000025] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000128] hw perfevents: no hardware support available\r
+[ 1.060051] CPU1: failed to come online\r
[ 2.080097] CPU2: failed to come online\r
-[ 3.100143] CPU3: failed to come online\r
-[ 3.100145] Brought up 1 CPUs\r
+[ 3.100144] CPU3: failed to come online\r
+[ 3.100146] Brought up 1 CPUs\r
[ 3.100146] SMP: Total of 1 processors activated.\r
-[ 3.100182] devtmpfs: initialized\r
-[ 3.100453] atomic64_test: passed\r
-[ 3.100481] regulator-dummy: no parameters\r
-[ 3.100703] NET: Registered protocol family 16\r
-[ 3.100783] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.100790] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.101275] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.101279] Serial: AMBA PL011 UART driver\r
-[ 3.101402] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.101425] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.101952] console [ttyAMA0] enabled\r
-[ 3.102005] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.102030] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.102055] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.102079] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130361] 3V3: 3300 mV \r
-[ 3.130390] vgaarb: loaded\r
-[ 3.130421] SCSI subsystem initialized\r
-[ 3.130450] libata version 3.00 loaded.\r
-[ 3.130481] usbcore: registered new interface driver usbfs\r
-[ 3.130495] usbcore: registered new interface driver hub\r
-[ 3.130519] usbcore: registered new device driver usb\r
-[ 3.130538] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.130547] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.130563] PTP clock support registered\r
-[ 3.130638] Switched to clocksource arch_sys_counter\r
-[ 3.131336] NET: Registered protocol family 2\r
-[ 3.131382] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.131395] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.131411] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.131424] TCP: reno registered\r
-[ 3.131430] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131441] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.131468] NET: Registered protocol family 1\r
-[ 3.131511] RPC: Registered named UNIX socket transport module.\r
-[ 3.131521] RPC: Registered udp transport module.\r
-[ 3.131528] RPC: Registered tcp transport module.\r
-[ 3.131536] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.131547] PCI: CLS 0 bytes, default 64\r
-[ 3.131644] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.131705] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.132732] fuse init (API version 7.23)\r
-[ 3.132787] msgmni has been set to 469\r
-[ 3.134276] io scheduler noop registered\r
-[ 3.134311] io scheduler cfq registered (default)\r
-[ 3.134587] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.134599] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.134609] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.134620] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.134629] pci_bus 0000:00: scanning bus\r
-[ 3.134638] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.134649] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.134662] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134688] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.134699] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.134709] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.134718] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.134728] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.134737] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.134747] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.134773] pci_bus 0000:00: fixups for bus\r
-[ 3.134781] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.134791] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.134806] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.134814] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.134822] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.134830] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.134839] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.134851] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.134863] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.134874] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.134885] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.134895] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.134905] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.134915] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.135224] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.135384] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.135393] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.135411] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.135582] scsi0 : ata_piix\r
-[ 3.135646] scsi1 : ata_piix\r
-[ 3.135666] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.135677] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.135746] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.135757] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.135770] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.135780] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.290658] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.290667] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.290689] ata1.00: configured for UDMA/33\r
-[ 3.290723] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.290797] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.290816] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.290846] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.290855] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.290871] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.290955] sda: sda1\r
-[ 3.291031] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.410909] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.410921] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.410937] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.410947] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.410962] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.410973] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411018] usbcore: registered new interface driver usb-storage\r
-[ 3.411056] mousedev: PS/2 mouse device common for all mice\r
-[ 3.411152] usbcore: registered new interface driver usbhid\r
-[ 3.411161] usbhid: USB HID core driver\r
-[ 3.411184] TCP: cubic registered\r
-[ 3.411190] NET: Registered protocol family 17\r
-\0[ 3.411417] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.411445] devtmpfs: mounted\r
-[ 3.411480] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 3.100191] devtmpfs: initialized\r
+[ 3.100478] atomic64_test: passed\r
+[ 3.100511] regulator-dummy: no parameters\r
+[ 3.100758] NET: Registered protocol family 16\r
+[ 3.100846] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.100854] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.101552] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.101557] Serial: AMBA PL011 UART driver\r
+[ 3.101698] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.101724] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.102252] console [ttyAMA0] enabled\r
+[ 3.102316] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.102342] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.102367] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.102391] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130379] 3V3: 3300 mV \r
+[ 3.130413] vgaarb: loaded\r
+[ 3.130447] SCSI subsystem initialized\r
+[ 3.130476] libata version 3.00 loaded.\r
+[ 3.130509] usbcore: registered new interface driver usbfs\r
+[ 3.130523] usbcore: registered new interface driver hub\r
+[ 3.130548] usbcore: registered new device driver usb\r
+[ 3.130568] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.130576] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.130593] PTP clock support registered\r
+[ 3.130677] Switched to clocksource arch_sys_counter\r
+[ 3.131395] NET: Registered protocol family 2\r
+[ 3.131448] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.131463] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.131480] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.131494] TCP: reno registered\r
+[ 3.131500] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131512] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.131543] NET: Registered protocol family 1\r
+[ 3.131589] RPC: Registered named UNIX socket transport module.\r
+[ 3.131599] RPC: Registered udp transport module.\r
+[ 3.131606] RPC: Registered tcp transport module.\r
+[ 3.131614] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.131625] PCI: CLS 0 bytes, default 64\r
+[ 3.131729] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.131798] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.132866] fuse init (API version 7.23)\r
+[ 3.132923] msgmni has been set to 469\r
+[ 3.134469] io scheduler noop registered\r
+[ 3.134506] io scheduler cfq registered (default)\r
+[ 3.134833] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.134845] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.134855] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.134866] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.134875] pci_bus 0000:00: scanning bus\r
+[ 3.134885] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.134897] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.134909] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.134938] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.134948] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.134958] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.134968] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.134977] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.134987] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.134997] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.135023] pci_bus 0000:00: fixups for bus\r
+[ 3.135030] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.135041] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.135057] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.135065] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.135074] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.135082] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.135092] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.135103] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.135115] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.135127] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.135137] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.135147] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.135157] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.135168] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.135488] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.135665] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.135674] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.135695] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.135880] scsi0 : ata_piix\r
+[ 3.135948] scsi1 : ata_piix\r
+[ 3.135969] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.135980] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.136053] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.136064] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.136077] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.136087] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.290700] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.290708] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.290732] ata1.00: configured for UDMA/33\r
+[ 3.290772] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.290849] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.290869] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.290899] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.290908] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.290924] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.291014] sda: sda1\r
+[ 3.291093] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.410952] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.410964] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.410981] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.410990] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.411006] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.411017] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.411062] usbcore: registered new interface driver usb-storage\r
+[ 3.411102] mousedev: PS/2 mouse device common for all mice\r
+[ 3.411201] usbcore: registered new interface driver usbhid\r
+[ 3.411210] usbhid: USB HID core driver\r
+[ 3.411235] TCP: cubic registered\r
+[ 3.411242] NET: Registered protocol family 17\r
+\0[ 3.411492] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.411521] devtmpfs: mounted\r
+[ 3.411566] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.447850] udevd[607]: starting version 182\r
+[ 3.448001] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.542546] random: dd urandom read with 19 bits of entropy available\r
+[ 3.532640] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.660867] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.650908] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
type=LinuxArmSystem
children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
atags_addr=134217728
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm64
+boot_loader=/home/joel/research/gem5/full_system_files/binaries/boot_emm.arm64
boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1
cache_line_size=64
clk_domain=system.clk_domain
-dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch64.20140821.dtb
+dtb_filename=/home/joel/research/gem5/full_system_files/binaries/vexpress.aarch64.20140821.dtb
early_kernel_symbols=false
enable_context_switch_stats_dump=false
eventq_index=0
have_virtualization=false
highest_el_is_64=false
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch64.20140821
+kernel=/home/joel/research/gem5/full_system_files/binaries/vmlinux.aarch64.20140821
kernel_addr_check=true
load_addr_mask=268435455
load_offset=2147483648
memories=system.physmem system.realview.nvmem system.realview.vram
mmap_using_noreserve=false
multi_proc=true
+multi_thread=false
num_work_ids=16
panic_on_oops=true
panic_on_panic=true
phys_addr_range_64=40
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
reset_addr_64=0
symbolfile=
work_begin_ckpt_count=0
[system.cf0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linaro-minimal-aarch64.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linaro-minimal-aarch64.img
read_only=true
[system.clk_domain]
eventq_index=0
function_trace=false
function_trace_start=0
-interrupts=Null
+interrupts=
isa=system.cpu1.isa
istage2_mmu=system.cpu1.istage2_mmu
itb=system.cpu1.itb
[system.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.vncserver]
type=VncServer
eventq_index=0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Aug 7 2015 10:13:08
-gem5 started Aug 7 2015 11:47:53
-gem5 executing on e104799-lin
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
+gem5 compiled Oct 1 2015 05:39:21
+gem5 started Oct 2 2015 06:37:21
+gem5 executing on artery
+command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing -re /home/joel/research/gem5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-timing
Selected 64-bit ARM architecture, updating default disk image...
Global frequency set at 1000000000000 ticks per second
sim_ticks 51811486345500 # Number of ticks simulated
final_tick 51811486345500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 646354 # Simulator instruction rate (inst/s)
-host_op_rate 759580 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 40519578786 # Simulator tick rate (ticks/s)
-host_mem_usage 722184 # Number of bytes of host memory used
-host_seconds 1278.68 # Real time elapsed on the host
+host_inst_rate 353733 # Simulator instruction rate (inst/s)
+host_op_rate 415699 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 22175355428 # Simulator tick rate (ticks/s)
+host_mem_usage 671232 # Number of bytes of host memory used
+host_seconds 2336.44 # Real time elapsed on the host
sim_insts 826478524 # Number of instructions simulated
sim_ops 971257944 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.numCycles 51812404725 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu0.kern.inst.arm 0 # number of arm instructions executed
+system.cpu0.kern.inst.quiesce 15960 # number of quiesce instructions executed
system.cpu0.committedInsts 413973920 # Number of instructions committed
system.cpu0.committedOps 486522682 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 447282441 # Number of integer alu accesses
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 486797091 # Class of executed instruction
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 18838 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 9220536 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.942797 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 287472122 # Total number of references to valid blocks.
system.cpu1.numCycles 51810567966 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
+system.cpu1.kern.inst.arm 0 # number of arm instructions executed
+system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu1.committedInsts 412504604 # Number of instructions committed
system.cpu1.committedOps 484735262 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 445679810 # Number of integer alu accesses
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 485014384 # Class of executed instruction
-system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.iobus.trans_dist::ReadReq 40322 # Transaction distribution
system.iobus.trans_dist::ReadResp 40322 # Transaction distribution
system.iobus.trans_dist::WriteReq 136571 # Transaction distribution
[ 0.000000] NR_IRQS:64 nr_irqs:64 0\r
[ 0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).\r
[ 0.000001] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns\r
-[ 0.000040] Console: colour dummy device 80x25\r
-[ 0.000043] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
-[ 0.000046] pid_max: default: 32768 minimum: 301\r
-[ 0.000067] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000069] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
-[ 0.000281] hw perfevents: no hardware support available\r
-[ 1.060140] CPU1: failed to come online\r
-[ 2.080277] CPU2: failed to come online\r
-[ 3.100414] CPU3: failed to come online\r
-[ 3.100419] Brought up 1 CPUs\r
-[ 3.100421] SMP: Total of 1 processors activated.\r
-[ 3.100521] devtmpfs: initialized\r
-[ 3.101599] atomic64_test: passed\r
-[ 3.101677] regulator-dummy: no parameters\r
-[ 3.102436] NET: Registered protocol family 16\r
-[ 3.102707] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
-[ 3.102718] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
-[ 3.104187] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
-[ 3.104194] Serial: AMBA PL011 UART driver\r
-[ 3.104560] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
-[ 3.104628] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
-[ 3.105186] console [ttyAMA0] enabled\r
-[ 3.105314] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
-[ 3.105363] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
-[ 3.105412] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
-[ 3.105457] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
-[ 3.130945] 3V3: 3300 mV \r
-[ 3.131024] vgaarb: loaded\r
-[ 3.131114] SCSI subsystem initialized\r
-[ 3.131184] libata version 3.00 loaded.\r
-[ 3.131268] usbcore: registered new interface driver usbfs\r
-[ 3.131295] usbcore: registered new interface driver hub\r
-[ 3.131349] usbcore: registered new device driver usb\r
-[ 3.131393] pps_core: LinuxPPS API ver. 1 registered\r
-[ 3.131403] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
-[ 3.131425] PTP clock support registered\r
-[ 3.131650] Switched to clocksource arch_sys_counter\r
-[ 3.133712] NET: Registered protocol family 2\r
-[ 3.133864] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
-[ 3.133892] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
-[ 3.133924] TCP: Hash tables configured (established 2048 bind 2048)\r
-[ 3.133963] TCP: reno registered\r
-[ 3.133970] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.133988] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
-[ 3.134052] NET: Registered protocol family 1\r
-[ 3.134122] RPC: Registered named UNIX socket transport module.\r
-[ 3.134132] RPC: Registered udp transport module.\r
-[ 3.134141] RPC: Registered tcp transport module.\r
-[ 3.134149] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
-[ 3.134162] PCI: CLS 0 bytes, default 64\r
-[ 3.134478] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
-[ 3.134677] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
-[ 3.138144] fuse init (API version 7.23)\r
-[ 3.138307] msgmni has been set to 469\r
-[ 3.142786] io scheduler noop registered\r
-[ 3.142881] io scheduler cfq registered (default)\r
-[ 3.143804] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
-[ 3.143818] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
-[ 3.143831] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
-[ 3.143844] pci_bus 0000:00: root bus resource [bus 00-ff]\r
-[ 3.143855] pci_bus 0000:00: scanning bus\r
-[ 3.143868] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
-[ 3.143883] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.143900] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.143960] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
-[ 3.143973] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
-[ 3.143986] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
-[ 3.143998] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
-[ 3.144010] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
-[ 3.144022] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
-[ 3.144035] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
-[ 3.144093] pci_bus 0000:00: fixups for bus\r
-[ 3.144103] pci_bus 0000:00: bus scan returning with max=00\r
-[ 3.144116] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
-[ 3.144141] pci 0000:00:00.0: fixup irq: got 33\r
-[ 3.144150] pci 0000:00:00.0: assigning IRQ 33\r
-[ 3.144163] pci 0000:00:01.0: fixup irq: got 34\r
-[ 3.144173] pci 0000:00:01.0: assigning IRQ 34\r
-[ 3.144188] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
-[ 3.144202] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
-[ 3.144216] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.144230] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
-[ 3.144243] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
-[ 3.144256] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
-[ 3.144269] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
-[ 3.144282] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.145170] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
-[ 3.145672] ata_piix 0000:00:01.0: version 2.13\r
-[ 3.145683] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
-[ 3.145719] ata_piix 0000:00:01.0: enabling bus mastering\r
-[ 3.146290] scsi0 : ata_piix\r
-[ 3.146464] scsi1 : ata_piix\r
-[ 3.146516] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.146529] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.146721] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.146734] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.146755] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.146767] e1000 0000:00:00.0: enabling bus mastering\r
-[ 3.301682] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
-[ 3.301693] ata1.00: 2096640 sectors, multi 0: LBA \r
-[ 3.301726] ata1.00: configured for UDMA/33\r
-[ 3.301800] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
-[ 3.301991] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
-[ 3.302026] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
-[ 3.302082] sd 0:0:0:0: [sda] Write Protect is off\r
-[ 3.302093] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
-[ 3.302121] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
-[ 3.302324] sda: sda1\r
-[ 3.302524] sd 0:0:0:0: [sda] Attached SCSI disk\r
-[ 3.422002] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
-[ 3.422017] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
-[ 3.422045] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
-[ 3.422056] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
-[ 3.422086] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
-[ 3.422098] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.422227] usbcore: registered new interface driver usb-storage\r
-[ 3.422318] mousedev: PS/2 mouse device common for all mice\r
-[ 3.422603] usbcore: registered new interface driver usbhid\r
-[ 3.422613] usbhid: USB HID core driver\r
-[ 3.422663] TCP: cubic registered\r
-[ 3.422672] NET: Registered protocol family 17\r
-\0[ 3.423259] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
-[ 3.423303] devtmpfs: mounted\r
-[ 3.423393] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
+[ 0.000045] Console: colour dummy device 80x25\r
+[ 0.000049] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)\r
+[ 0.000051] pid_max: default: 32768 minimum: 301\r
+[ 0.000075] Mount-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000077] Mountpoint-cache hash table entries: 512 (order: 0, 4096 bytes)\r
+[ 0.000352] hw perfevents: no hardware support available\r
+[ 1.060141] CPU1: failed to come online\r
+[ 2.080278] CPU2: failed to come online\r
+[ 3.100415] CPU3: failed to come online\r
+[ 3.100420] Brought up 1 CPUs\r
+[ 3.100422] SMP: Total of 1 processors activated.\r
+[ 3.100538] devtmpfs: initialized\r
+[ 3.101654] atomic64_test: passed\r
+[ 3.101742] regulator-dummy: no parameters\r
+[ 3.102585] NET: Registered protocol family 16\r
+[ 3.102876] vdso: 2 pages (1 code, 1 data) at base ffffffc0006cd000\r
+[ 3.102888] hw-breakpoint: found 2 breakpoint and 2 watchpoint registers.\r
+[ 3.105208] software IO TLB [mem 0x8d400000-0x8d800000] (4MB) mapped at [ffffffc00d400000-ffffffc00d7fffff]\r
+[ 3.105217] Serial: AMBA PL011 UART driver\r
+[ 3.105618] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/sysctl@020000\r
+[ 3.105693] 1c090000.uart: ttyAMA0 at MMIO 0x1c090000 (irq = 37, base_baud = 0) is a PL011 rev3\r
+[ 3.106253] console [ttyAMA0] enabled\r
+[ 3.106402] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0a0000\r
+[ 3.106451] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0b0000\r
+[ 3.106501] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/uart@0c0000\r
+[ 3.106546] of_amba_device_create(): amba_device_add() failed (-19) for /smb/motherboard/iofpga@3,00000000/wdt@0f0000\r
+[ 3.130866] 3V3: 3300 mV \r
+[ 3.130954] vgaarb: loaded\r
+[ 3.131051] SCSI subsystem initialized\r
+[ 3.131124] libata version 3.00 loaded.\r
+[ 3.131215] usbcore: registered new interface driver usbfs\r
+[ 3.131243] usbcore: registered new interface driver hub\r
+[ 3.131300] usbcore: registered new device driver usb\r
+[ 3.131347] pps_core: LinuxPPS API ver. 1 registered\r
+[ 3.131356] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>\r
+[ 3.131380] PTP clock support registered\r
+[ 3.131621] Switched to clocksource arch_sys_counter\r
+[ 3.133832] NET: Registered protocol family 2\r
+[ 3.133998] TCP established hash table entries: 2048 (order: 2, 16384 bytes)\r
+[ 3.134030] TCP bind hash table entries: 2048 (order: 3, 32768 bytes)\r
+[ 3.134070] TCP: Hash tables configured (established 2048 bind 2048)\r
+[ 3.134123] TCP: reno registered\r
+[ 3.134131] UDP hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134150] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)\r
+[ 3.134226] NET: Registered protocol family 1\r
+[ 3.134305] RPC: Registered named UNIX socket transport module.\r
+[ 3.134315] RPC: Registered udp transport module.\r
+[ 3.134324] RPC: Registered tcp transport module.\r
+[ 3.134332] RPC: Registered tcp NFSv4.1 backchannel transport module.\r
+[ 3.134346] PCI: CLS 0 bytes, default 64\r
+[ 3.134689] futex hash table entries: 1024 (order: 4, 65536 bytes)\r
+[ 3.134927] HugeTLB registered 2 MB page size, pre-allocated 0 pages\r
+[ 3.138697] fuse init (API version 7.23)\r
+[ 3.138869] msgmni has been set to 469\r
+[ 3.143638] io scheduler noop registered\r
+[ 3.143735] io scheduler cfq registered (default)\r
+[ 3.144790] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.144804] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
+[ 3.144817] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
+[ 3.144830] pci_bus 0000:00: root bus resource [bus 00-ff]\r
+[ 3.144841] pci_bus 0000:00: scanning bus\r
+[ 3.144856] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
+[ 3.144871] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
+[ 3.144888] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.144952] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
+[ 3.144966] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
+[ 3.144978] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
+[ 3.144990] pci 0000:00:01.0: reg 0x18: [io 0x0000-0x0007]\r
+[ 3.145002] pci 0000:00:01.0: reg 0x1c: [io 0x0000-0x0003]\r
+[ 3.145014] pci 0000:00:01.0: reg 0x20: [io 0x0000-0x000f]\r
+[ 3.145028] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.145087] pci_bus 0000:00: fixups for bus\r
+[ 3.145097] pci_bus 0000:00: bus scan returning with max=00\r
+[ 3.145111] pci 0000:00:00.0: calling quirk_e100_interrupt+0x0/0x1cc\r
+[ 3.145140] pci 0000:00:00.0: fixup irq: got 33\r
+[ 3.145149] pci 0000:00:00.0: assigning IRQ 33\r
+[ 3.145163] pci 0000:00:01.0: fixup irq: got 34\r
+[ 3.145172] pci 0000:00:01.0: assigning IRQ 34\r
+[ 3.145186] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
+[ 3.145201] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
+[ 3.145215] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
+[ 3.145229] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.145242] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
+[ 3.145255] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
+[ 3.145268] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
+[ 3.145280] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
+[ 3.146196] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.146728] ata_piix 0000:00:01.0: version 2.13\r
+[ 3.146741] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
+[ 3.146785] ata_piix 0000:00:01.0: enabling bus mastering\r
+[ 3.147395] scsi0 : ata_piix\r
+[ 3.147583] scsi1 : ata_piix\r
+[ 3.147636] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
+[ 3.147649] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.147855] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.147867] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.147890] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.147903] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.301657] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
+[ 3.301668] ata1.00: 2096640 sectors, multi 0: LBA \r
+[ 3.301702] ata1.00: configured for UDMA/33\r
+[ 3.301790] scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5\r
+[ 3.301986] sd 0:0:0:0: Attached scsi generic sg0 type 0\r
+[ 3.302022] sd 0:0:0:0: [sda] 2096640 512-byte logical blocks: (1.07 GB/1023 MiB)\r
+[ 3.302079] sd 0:0:0:0: [sda] Write Protect is off\r
+[ 3.302090] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00\r
+[ 3.302118] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA\r
+[ 3.302321] sda: sda1\r
+[ 3.302527] sd 0:0:0:0: [sda] Attached SCSI disk\r
+[ 3.421982] e1000 0000:00:00.0 eth0: (PCI:33MHz:32-bit) 00:90:00:00:00:01\r
+[ 3.421997] e1000 0000:00:00.0 eth0: Intel(R) PRO/1000 Network Connection\r
+[ 3.422026] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k\r
+[ 3.422036] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
+[ 3.422067] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
+[ 3.422079] igb: Copyright (c) 2007-2014 Intel Corporation.\r
+[ 3.422210] usbcore: registered new interface driver usb-storage\r
+[ 3.422303] mousedev: PS/2 mouse device common for all mice\r
+[ 3.422596] usbcore: registered new interface driver usbhid\r
+[ 3.422606] usbhid: USB HID core driver\r
+[ 3.422662] TCP: cubic registered\r
+[ 3.422671] NET: Registered protocol family 17\r
+\0[ 3.423301] VFS: Mounted root (ext2 filesystem) on device 8:1.\r
+[ 3.423347] devtmpfs: mounted\r
+[ 3.423474] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.470213] udevd[607]: starting version 182\r
+[ 3.470471] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.606506] random: dd urandom read with 20 bits of entropy available\r
+[ 3.586574] random: dd urandom read with 21 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.801885] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.791856] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/home/joel/research/gem5/full_system_files/binaries/x86_64-vmlinux-2.6.22.9
kernel_addr_check=true
load_addr_mask=18446744073709551615
load_offset=0
mem_ranges=0:134217727
memories=system.physmem
mmap_using_noreserve=false
+multi_thread=false
num_work_ids=16
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+readfile=/home/joel/research/gem5/gem5/tests/halt.sh
smbios_table=system.smbios_table
symbolfile=
work_begin_ckpt_count=0
[system.cpu.toL2Bus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_latency=0
frontend_latency=1
response_latency=1
-snoop_filter=Null
+snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
system=system
use_default_range=false
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
+[system.cpu.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=0
+max_capacity=8388608
+system=system
+
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/home/joel/research/gem5/full_system_files/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 6 2015 22:19:56
-gem5 started Jan 6 2015 22:27:08
-gem5 executing on gabeblackz620.mtv.corp.google.com
-command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+gem5 compiled Oct 1 2015 04:53:13
+gem5 started Oct 1 2015 04:53:52
+gem5 executing on artery
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re /home/joel/research/gem5/gem5/tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
+
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /home/joel/research/gem5/full_system_files/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5188454477000 because m5_exit instruction encountered
+Exiting @ tick 5194921252500 because m5_exit instruction encountered
sim_ticks 5194921252500 # Number of ticks simulated
final_tick 5194921252500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 862150 # Simulator instruction rate (inst/s)
-host_op_rate 1661827 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34815163679 # Simulator tick rate (ticks/s)
-host_mem_usage 660376 # Number of bytes of host memory used
-host_seconds 149.21 # Real time elapsed on the host
-sim_insts 128645146 # Number of instructions simulated
-sim_ops 247968367 # Number of ops (including micro ops) simulated
+host_inst_rate 334832 # Simulator instruction rate (inst/s)
+host_op_rate 645401 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 13521111808 # Simulator tick rate (ticks/s)
+host_mem_usage 605972 # Number of bytes of host memory used
+host_seconds 384.21 # Real time elapsed on the host
+sim_insts 128645145 # Number of instructions simulated
+sim_ops 247968363 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
system.physmem_0.readEnergy 590093400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 401209200 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 136710410535 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2997028289250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3474354711360 # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy 136710415665 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2997028284750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3474354711990 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.798995 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4985717898976 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 4985717890976 # Time in different power states
system.physmem_0.memoryStateTime::REF 173469660000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 35728624774 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 35728632774 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 217334880 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 118585500 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 606504600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 416203920 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 339306654960 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 137303657415 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 2996507897250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 3474476838525 # Total energy per rank (pJ)
+system.physmem_1.actBackEnergy 137303660835 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 2996507894250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 3474476838945 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.822504 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 4984854152228 # Time in different power states
+system.physmem_1.memoryStateTime::IDLE 4984854148228 # Time in different power states
system.physmem_1.memoryStateTime::REF 173469660000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 36597268272 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 36597272272 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.numCycles 10389842505 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 128645146 # Number of instructions committed
-system.cpu.committedOps 247968367 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 232546073 # Number of integer alu accesses
+system.cpu.kern.inst.arm 0 # number of arm instructions executed
+system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu.committedInsts 128645145 # Number of instructions committed
+system.cpu.committedOps 247968363 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 232546069 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 2315361 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 23194066 # number of instructions that are conditional controls
-system.cpu.num_int_insts 232546073 # number of integer instructions
+system.cpu.num_int_insts 232546069 # number of integer instructions
system.cpu.num_fp_insts 48 # number of float instructions
-system.cpu.num_int_register_reads 435625867 # number of times the integer registers were read
-system.cpu.num_int_register_writes 198317571 # number of times the integer registers were written
+system.cpu.num_int_register_reads 435625855 # number of times the integer registers were read
+system.cpu.num_int_register_writes 198317568 # number of times the integer registers were written
system.cpu.num_fp_register_reads 48 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 133116487 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 95666128 # number of times the CC registers were written
-system.cpu.num_mem_refs 22339099 # number of memory refs
-system.cpu.num_load_insts 13935933 # Number of load instructions
-system.cpu.num_store_insts 8403166 # Number of store instructions
-system.cpu.num_idle_cycles 9774871363.998119 # Number of idle cycles
-system.cpu.num_busy_cycles 614971141.001882 # Number of busy cycles
+system.cpu.num_cc_register_reads 133116486 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 95666126 # number of times the CC registers were written
+system.cpu.num_mem_refs 22339097 # number of memory refs
+system.cpu.num_load_insts 13935932 # Number of load instructions
+system.cpu.num_store_insts 8403165 # Number of store instructions
+system.cpu.num_idle_cycles 9774871371.998117 # Number of idle cycles
+system.cpu.num_busy_cycles 614971133.001882 # Number of busy cycles
system.cpu.not_idle_fraction 0.059190 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.940810 # Percentage of idle cycles
system.cpu.Branches 26367781 # Number of branches fetched
system.cpu.op_class::No_OpClass 172241 0.07% 0.07% # Class of executed instruction
-system.cpu.op_class::IntAlu 225200251 90.82% 90.89% # Class of executed instruction
+system.cpu.op_class::IntAlu 225200249 90.82% 90.89% # Class of executed instruction
system.cpu.op_class::IntMult 140056 0.06% 90.94% # Class of executed instruction
system.cpu.op_class::IntDiv 123237 0.05% 90.99% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction
-system.cpu.op_class::MemRead 13930961 5.62% 96.61% # Class of executed instruction
-system.cpu.op_class::MemWrite 8403166 3.39% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 13930960 5.62% 96.61% # Class of executed instruction
+system.cpu.op_class::MemWrite 8403165 3.39% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 247969928 # Class of executed instruction
-system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.cpu.op_class::total 247969924 # Class of executed instruction
system.cpu.dcache.tags.replacements 1623328 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.995361 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 20131143 # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 20131141 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 1623840 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 12.397245 # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 12.397244 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.995361 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::2 123 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 88683234 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 88683234 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 12000893 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 12000893 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 8069415 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 8069415 # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses 88683226 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 88683226 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 12000892 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 12000892 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8069414 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 8069414 # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data 58662 # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total 58662 # number of SoftPFReq hits
-system.cpu.dcache.demand_hits::cpu.data 20070308 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 20070308 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 20128970 # number of overall hits
-system.cpu.dcache.overall_hits::total 20128970 # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data 20070306 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 20070306 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 20128968 # number of overall hits
+system.cpu.dcache.overall_hits::total 20128968 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 906883 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 906883 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 325772 # number of WriteReq misses
system.cpu.dcache.demand_miss_latency::total 31845914977 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 31845914977 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 31845914977 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 12907776 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 12907776 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 8395187 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 8395187 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 12907775 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 12907775 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8395186 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 8395186 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data 461872 # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total 461872 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 21302963 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 21302963 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 21764835 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 21764835 # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 21302961 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 21302961 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21764833 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 21764833 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070259 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.070259 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038805 # miss rate for WriteReq accesses
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 789867 # number of replacements
system.cpu.icache.tags.tagsinuse 510.214824 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 144930127 # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs 144930125 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 790379 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 183.367887 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 183.367884 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 164495636500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 510.214824 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.996513 # Average percentage of cache occupancy
system.cpu.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 146510899 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 146510899 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 144930127 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 144930127 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 144930127 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 144930127 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 144930127 # number of overall hits
-system.cpu.icache.overall_hits::total 144930127 # number of overall hits
+system.cpu.icache.tags.tag_accesses 146510897 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 146510897 # Number of data accesses
+system.cpu.icache.ReadReq_hits::cpu.inst 144930125 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 144930125 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 144930125 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 144930125 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 144930125 # number of overall hits
+system.cpu.icache.overall_hits::total 144930125 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 790386 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 790386 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 790386 # number of demand (read+write) misses
system.cpu.icache.demand_miss_latency::total 11833714500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11833714500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11833714500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 145720513 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 145720513 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 145720513 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 145720513 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 145720513 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 145720513 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 145720511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 145720511 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 145720511 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 145720511 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 145720511 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 145720511 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005424 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.005424 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.005424 # miss rate for demand accesses
projects / gem5.git / commitdiff