warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:59:50
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:34:24
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 216988313500 because target called exit()
+Exiting @ tick 216988269500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 115233 # Simulator instruction rate (inst/s)
-host_mem_usage 238284 # Number of bytes of host memory used
-host_seconds 5211.87 # Real time elapsed on the host
-host_tick_rate 41633525 # Simulator tick rate (ticks/s)
+host_inst_rate 84615 # Simulator instruction rate (inst/s)
+host_mem_usage 256696 # Number of bytes of host memory used
+host_seconds 7097.77 # Real time elapsed on the host
+host_tick_rate 30571310 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 600581394 # Number of instructions simulated
+sim_insts 600581343 # Number of instructions simulated
sim_seconds 0.216988 # Number of seconds simulated
-sim_ticks 216988313500 # Number of ticks simulated
+sim_ticks 216988269500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 80605282 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 86770000 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 80605280 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 86769998 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 3926724 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 92457745 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 92457745 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 92457743 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 92457743 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 70067581 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 7237695 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 7237688 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 415629341 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.444993 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.803103 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 415627277 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.445000 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.803105 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 151329728 36.41% 36.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 131463070 31.63% 68.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 59591076 14.34% 82.38% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 151327612 36.41% 36.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 131463127 31.63% 68.04% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 59591085 14.34% 82.38% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 19300079 4.64% 87.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 16801344 4.04% 91.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 14774924 3.55% 94.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 12865596 3.10% 97.71% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 2265829 0.55% 98.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 7237695 1.74% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 16801337 4.04% 91.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 14774918 3.55% 94.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 12865599 3.10% 97.71% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 2265832 0.55% 98.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 7237688 1.74% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 415629341 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 415627277 # Number of insts commited each cycle
system.cpu.commit.COM:count 600581394 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 219174038 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4754911 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 4754311 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 600581394 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3642 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 121350527 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 600581394 # Number of Instructions Simulated
-system.cpu.committedInsts_total 600581394 # Number of Instructions Simulated
+system.cpu.commit.commitSquashedInsts 121349980 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 600581343 # Number of Instructions Simulated
+system.cpu.committedInsts_total 600581343 # Number of Instructions Simulated
system.cpu.cpi 0.722594 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.722594 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 140357692 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13127.051417 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.439109 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 140121331 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3102723000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 13126.895414 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7797.393105 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 140121332 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3102673000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001684 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 236361 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 40726 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1525452000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 236360 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 40725 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1525443000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001394 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 195635 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 17787.356145 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.258061 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 17787.364223 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10360.276216 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 67933393 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 26422494996 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 26422506996 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.021399 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 1485465 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 1237601 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2567935004 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 2567939504 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003571 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 247864 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs 4386.427788 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 469.123189 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 469.123191 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 2188 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 9597504 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 209776550 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 17147.620024 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 208054724 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29525217996 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 17147.607914 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 208054725 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29525179996 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.008208 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1721826 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1278327 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4093387004 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 1721825 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1278326 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4093382504 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.002114 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 443499 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999739 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.932542 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4094.932523 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 209776550 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 17147.620024 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 9229.754755 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 17147.607914 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 9229.744608 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 208054724 # number of overall hits
-system.cpu.dcache.overall_miss_latency 29525217996 # number of overall miss cycles
+system.cpu.dcache.overall_hits 208054725 # number of overall hits
+system.cpu.dcache.overall_miss_latency 29525179996 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.008208 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1721826 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 1278327 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4093387004 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 1721825 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1278326 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4093382504 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.002114 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 443499 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 439401 # number of replacements
system.cpu.dcache.sampled_refs 443497 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.932542 # Cycle average of tags in use
-system.cpu.dcache.total_refs 208054727 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 90722000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4094.932523 # Cycle average of tags in use
+system.cpu.dcache.total_refs 208054728 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 90723000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 394050 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 84141891 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 763382279 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 172756991 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 145179524 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 17468389 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 13550935 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles 84141897 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 763381678 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 172755507 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 145178933 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 17467706 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 13550939 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 92457745 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 75163464 # Number of cache lines fetched
-system.cpu.fetch.Cycles 161721844 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 803289 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 727645117 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 5447650 # Number of cycles fetch has spent squashing
+system.cpu.fetch.Branches 92457743 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 75163466 # Number of cache lines fetched
+system.cpu.fetch.Cycles 161721841 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 803288 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 727645114 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 5447051 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.213048 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 75163464 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 80605282 # Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 75163466 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 80605280 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.676692 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 433097730 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.793885 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.871524 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 433094982 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.793896 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.871529 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 271377208 62.66% 62.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 26620227 6.15% 68.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 271374463 62.66% 62.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 26620223 6.15% 68.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18536414 4.28% 73.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 23464508 5.42% 78.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11465886 2.65% 81.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 12676535 2.93% 84.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5122175 1.18% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5122176 1.18% 85.26% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 7816549 1.80% 87.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 56018228 12.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 433097730 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 433094982 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 75163464 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35391.803279 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34026.104418 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 75162549 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 32383500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 75163466 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35392.896175 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34027.443106 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 75162551 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32384500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000012 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 915 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 168 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25417500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 25418500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 747 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 100889.327517 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 100889.330201 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 75163464 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35391.803279 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
-system.cpu.icache.demand_hits 75162549 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 32383500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 75163466 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35392.896175 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency
+system.cpu.icache.demand_hits 75162551 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32384500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000012 # miss rate for demand accesses
system.cpu.icache.demand_misses 915 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 168 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25417500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 25418500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000010 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 747 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.323287 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 662.091545 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 75163464 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35391.803279 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34026.104418 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 662.091546 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 75163466 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35392.896175 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34027.443106 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 75162549 # number of overall hits
-system.cpu.icache.overall_miss_latency 32383500 # number of overall miss cycles
+system.cpu.icache.overall_hits 75162551 # number of overall hits
+system.cpu.icache.overall_miss_latency 32384500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000012 # miss rate for overall accesses
system.cpu.icache.overall_misses 915 # number of overall misses
system.cpu.icache.overall_mshr_hits 168 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25417500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 25418500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000010 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 747 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 23 # number of replacements
system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 662.091545 # Cycle average of tags in use
-system.cpu.icache.total_refs 75162549 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 662.091546 # Cycle average of tags in use
+system.cpu.icache.total_refs 75162551 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 878898 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 74261584 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.487821 # Inst execution rate
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+system.cpu.iew.EXEC:branches 74261585 # Number of branches executed
+system.cpu.iew.EXEC:nop 62913 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.487680 # Inst execution rate
system.cpu.iew.EXEC:refs 240772759 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 74373435 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 747728848 # num instructions consuming a value
-system.cpu.iew.WB:count 638555092 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.593985 # average fanout of values written-back
+system.cpu.iew.WB:consumers 747728792 # num instructions consuming a value
+system.cpu.iew.WB:count 638494059 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.593986 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 444140092 # num instructions producing a value
-system.cpu.iew.WB:rate 1.471404 # insts written-back per cycle
-system.cpu.iew.WB:sent 640268738 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 5263099 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 938806 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 184696678 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 444140095 # num instructions producing a value
+system.cpu.iew.WB:rate 1.471264 # insts written-back per cycle
+system.cpu.iew.WB:sent 640207091 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 5262481 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 938808 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 184696679 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3886 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3056895 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 88578802 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 721929575 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 3056896 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 88578804 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 721929028 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 166399324 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7744433 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 645679694 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 15541 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewExecSquashedInsts 7744349 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 645618045 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 15544 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 10568 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 17468389 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 17467706 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 68840 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 8986 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 927620 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 15164 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 35743652 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 18357789 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 35743653 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 18357791 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 927620 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1456086 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1455468 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 3807013 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 1741733302 # number of integer regfile reads
-system.cpu.int_regfile_writes 500762065 # number of integer regfile writes
+system.cpu.int_regfile_reads 1741672216 # number of integer regfile reads
+system.cpu.int_regfile_writes 500762058 # number of integer regfile writes
system.cpu.ipc 1.383903 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.383903 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 408584049 62.53% 62.53% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 408522313 62.53% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 6689 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 168909832 25.85% 88.38% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 168909835 25.85% 88.38% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 75923554 11.62% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 653424127 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 7689778 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.011768 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 653362394 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 7689776 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.011770 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 110226 1.43% 1.43% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 110224 1.43% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.43% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 216637 2.82% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 433097730 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.508722 # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 131709381 30.41% 30.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 125173843 28.90% 59.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 78416744 18.11% 77.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 46404818 10.71% 88.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 32896297 7.60% 95.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 12946022 2.99% 98.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 3892650 0.90% 99.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 732656 0.17% 99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 925319 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 131707315 30.41% 30.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 125173244 28.90% 59.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 78416793 18.11% 77.42% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 46415103 10.72% 88.14% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 32898080 7.60% 95.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 12956560 2.99% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 3885385 0.90% 99.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 717191 0.17% 99.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 925311 0.21% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 433097730 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.505667 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 433094982 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.505525 # Inst issue rate
system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 661113885 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 1748261718 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 638555076 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 843800706 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 721925689 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 653424127 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 661052150 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 1748135502 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 638494043 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 843674084 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 721862229 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 653362394 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3886 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 120964345 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 120901183 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 625992 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 244 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 239956902 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 239953447 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 247865 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.327689 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.618950 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34472.344792 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31273.636053 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 189395 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 2015597000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2015598000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.235895 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 58470 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828568500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828569500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235895 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 58470 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 196377 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34258.171034 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34258.354481 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31117.674945 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 163670 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1120482000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 1120488000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.166552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 32707 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 444242 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34395.505445 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34395.582219 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 353065 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 3136079000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 3136086000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.205242 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 91177 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 2845992000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 2845993000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.205217 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 91166 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.056947 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.488639 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1866.034390 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16011.711399 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 1866.034580 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16011.711774 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 444242 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34395.505445 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.690806 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34395.582219 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.701775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 353065 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 3136079000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 3136086000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.205242 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 91177 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 2845992000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 2845993000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.205217 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 91166 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements 72987 # number of replacements
system.cpu.l2cache.sampled_refs 88484 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17877.745789 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 17877.746353 # Cycle average of tags in use
system.cpu.l2cache.total_refs 418684 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 58152 # number of writebacks
system.cpu.memDep0.conflictingLoads 56143840 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 33466008 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 184696678 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 88578802 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 960863166 # number of misc regfile reads
+system.cpu.memDep0.conflictingStores 33466009 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 184696679 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 88578804 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 960863165 # number of misc regfile reads
system.cpu.misc_regfile_writes 9367 # number of misc regfile writes
-system.cpu.numCycles 433976628 # number of cpu cycles simulated
+system.cpu.numCycles 433976540 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 12394432 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 12394449 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 469246940 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 63310884 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 190432951 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IQFullEvents 63310870 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 190431449 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 3181742 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 2146132338 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 749362118 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 579635257 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 140765492 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 17468389 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 71980169 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 110388314 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 2146129409 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 749361548 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 579635255 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 140764920 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 17467706 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 71980154 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 110388312 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 96 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 2146132242 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 56297 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:int_rename_lookups 2146129313 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 56304 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 3959 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 128598467 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 128598458 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3953 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 1130322956 # The number of ROB reads
-system.cpu.rob.rob_writes 1461347493 # The number of ROB writes
-system.cpu.timesIdled 36486 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 1130320351 # The number of ROB reads
+system.cpu.rob.rob_writes 1461345715 # The number of ROB writes
+system.cpu.timesIdled 36569 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:58:27
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 15:32:42
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 56054650500 because target called exit()
+Exiting @ tick 56054651500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 65288 # Simulator instruction rate (inst/s)
-host_mem_usage 370872 # Number of bytes of host memory used
-host_seconds 1396.92 # Real time elapsed on the host
-host_tick_rate 40127232 # Simulator tick rate (ticks/s)
+host_inst_rate 61070 # Simulator instruction rate (inst/s)
+host_mem_usage 389424 # Number of bytes of host memory used
+host_seconds 1493.21 # Real time elapsed on the host
+host_tick_rate 37539692 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 91202735 # Number of instructions simulated
+sim_insts 91190126 # Number of instructions simulated
sim_seconds 0.056055 # Number of seconds simulated
-sim_ticks 56054650500 # Number of ticks simulated
+sim_ticks 56054651500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 20717891 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 22133087 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 20717897 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 22133091 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 1885128 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 22369136 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 22369136 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 1885129 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 22369140 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 22369140 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 18672384 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 365812 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 365813 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:committed_per_cycle::samples 109380669 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.833810 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.220278 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.220279 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 55493598 50.73% 50.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 34988156 31.99% 82.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 8951301 8.18% 90.91% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 55493600 50.73% 50.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 34988153 31.99% 82.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 8951302 8.18% 90.91% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 6346851 5.80% 96.71% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::4 1763725 1.61% 98.32% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::5 198423 0.18% 98.50% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 611708 0.56% 99.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 661095 0.60% 99.67% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 365812 0.33% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 661094 0.60% 99.67% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 365813 0.33% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 27330336 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1941616 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1941617 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91202735 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 544722 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 11836568 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 91202735 # Number of Instructions Simulated
-system.cpu.committedInsts_total 91202735 # Number of Instructions Simulated
-system.cpu.cpi 1.229232 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.229232 # CPI: Total CPI of All Threads
+system.cpu.commit.commitSquashedInsts 11836562 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 91190126 # Number of Instructions Simulated
+system.cpu.committedInsts_total 91190126 # Number of Instructions Simulated
+system.cpu.cpi 1.229402 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.229402 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 23356359 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 5257.244166 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2204.745551 # average ReadReq mshr miss latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.851200 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3486.513521 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 3486.513459 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 28095227 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 7297.350069 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3081.864877 # average overall mshr miss latency
system.cpu.dcache.replacements 946019 # number of replacements
system.cpu.dcache.sampled_refs 950115 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3486.513521 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3486.513459 # Cycle average of tags in use
system.cpu.dcache.total_refs 27008178 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 23888323000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.warmup_cycle 23888324000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 943195 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 6646244 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 108354442 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 27877026 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 74250528 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 2697133 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 606871 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles 6646243 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 108354440 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 27877036 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 74250519 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2697135 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 606870 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 22369136 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 12683523 # Number of cache lines fetched
-system.cpu.fetch.Cycles 76804790 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 214313 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 109645009 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 22369140 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 12683528 # Number of cache lines fetched
+system.cpu.fetch.Cycles 76804780 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 214312 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 109645002 # Number of instructions fetch has processed
system.cpu.fetch.MiscStallCycles 18268 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 1945737 # Number of cycles fetch has spent squashing
+system.cpu.fetch.SquashCycles 1945739 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.199530 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 12683523 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 20717891 # Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 12683528 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 20717897 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.978019 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 112077802 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 112077803 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 0.986563 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.108840 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.108841 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 35656336 31.81% 31.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 60887091 54.33% 86.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 35656347 31.81% 31.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 60887079 54.33% 86.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 7618220 6.80% 92.94% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 828250 0.74% 93.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4141724 3.70% 97.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4141725 3.70% 97.37% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2560072 2.28% 99.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 241811 0.22% 99.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 241812 0.22% 99.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 9014 0.01% 99.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 135284 0.12% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 112077802 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 112077803 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 75 # number of floating regfile reads
system.cpu.fp_regfile_writes 47 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 12683523 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36326.451613 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34504.457652 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 12682748 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 28153000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 12683528 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36327.096774 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34505.200594 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12682753 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 28153500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000061 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 775 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 102 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 23221500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 23222000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000053 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 673 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18845.093611 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18845.101040 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 12683523 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36326.451613 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
-system.cpu.icache.demand_hits 12682748 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 28153000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 12683528 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36327.096774 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency
+system.cpu.icache.demand_hits 12682753 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 28153500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000061 # miss rate for demand accesses
system.cpu.icache.demand_misses 775 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 102 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 23221500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 23222000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000053 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 673 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.278329 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 570.018362 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 12683523 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36326.451613 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34504.457652 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 570.018353 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 12683528 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36327.096774 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34505.200594 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 12682748 # number of overall hits
-system.cpu.icache.overall_miss_latency 28153000 # number of overall miss cycles
+system.cpu.icache.overall_hits 12682753 # number of overall hits
+system.cpu.icache.overall_miss_latency 28153500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000061 # miss rate for overall accesses
system.cpu.icache.overall_misses 775 # number of overall misses
system.cpu.icache.overall_mshr_hits 102 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 23221500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 23222000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000053 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 673 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 3 # number of replacements
system.cpu.icache.sampled_refs 673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 570.018362 # Cycle average of tags in use
-system.cpu.icache.total_refs 12682748 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 570.018353 # Cycle average of tags in use
+system.cpu.icache.total_refs 12682753 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 31500 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 31501 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 19532471 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.868515 # Inst execution rate
-system.cpu.iew.EXEC:refs 28649530 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 5007242 # Number of stores executed
+system.cpu.iew.EXEC:nop 62748 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.868101 # Inst execution rate
+system.cpu.iew.EXEC:refs 28649527 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 5007239 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 90073384 # num instructions consuming a value
-system.cpu.iew.WB:count 96607772 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.596776 # average fanout of values written-back
+system.cpu.iew.WB:consumers 90073370 # num instructions consuming a value
+system.cpu.iew.WB:count 96561407 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.596775 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 53753594 # num instructions producing a value
-system.cpu.iew.WB:rate 0.861728 # insts written-back per cycle
-system.cpu.iew.WB:sent 96877677 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2055865 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 53753580 # num instructions producing a value
+system.cpu.iew.WB:rate 0.861315 # insts written-back per cycle
+system.cpu.iew.WB:sent 96831306 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2055858 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 89156 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 24681131 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 24681129 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 553822 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1090188 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 5533285 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 103041048 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 1090186 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 5533282 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 103041042 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 23642288 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2271319 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 97368620 # Number of executed instructions
+system.cpu.iew.iewExecSquashedInsts 2270342 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 97322249 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 1607 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 2697133 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 2697135 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 23177 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 17440 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 1330 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 2095638 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 788441 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 2095636 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 788438 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 1330 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 76117 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 76110 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 1979748 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 246289928 # number of integer regfile reads
-system.cpu.int_regfile_writes 76222702 # number of integer regfile writes
-system.cpu.ipc 0.813516 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.813516 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 246243554 # number of integer regfile reads
+system.cpu.int_regfile_writes 76222698 # number of integer regfile writes
+system.cpu.ipc 0.813404 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.813404 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 70327801 70.58% 70.58% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 3 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.59% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 24261779 24.35% 94.94% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039837 5.06% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 70280458 70.57% 70.57% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 10479 0.01% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 70.58% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 70.58% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 2 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 11 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 27 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 70.58% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 70.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 24261777 24.36% 94.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 5039834 5.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 99639939 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 99592591 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 491330 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.004931 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate 0.004933 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 430175 87.55% 87.55% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 27 0.01% 87.56% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 34720 7.07% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 112077802 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.889025 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.090069 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 112077803 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.888602 # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 47848976 42.69% 42.69% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 42741533 38.14% 80.83% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 14042267 12.53% 93.36% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 4560980 4.07% 97.43% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 789415 0.70% 98.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 737896 0.66% 98.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 1220893 1.09% 99.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 128302 0.11% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 47855391 42.70% 42.70% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 42755359 38.15% 80.85% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 14035968 12.52% 93.37% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 4551717 4.06% 97.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 786660 0.70% 98.13% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 736099 0.66% 98.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 1220793 1.09% 99.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 128276 0.11% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 7540 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 112077802 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.888775 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 112077803 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.888353 # Inst issue rate
system.cpu.iq.fp_alu_accesses 74 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 144 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 100131195 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 311849254 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 96607706 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 112840034 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 102487226 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 99639939 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 100083847 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 311754559 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 96561341 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 112732108 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 102424472 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 99592591 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 553822 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9797863 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 9752691 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 388 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9100 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 13596507 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 13565681 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.312342 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 14547 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 904214 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34294.794795 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34295.295295 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.850051 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 903215 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 34260500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 34261000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.001105 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 999 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 950788 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34285.282388 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34285.314550 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 935242 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 532999000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 532999500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.016351 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 15546 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.012324 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.246682 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 403.843593 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8083.268341 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 403.843587 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 8083.268197 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 950788 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34285.282388 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34285.314550 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31031.382773 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 935242 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 532999000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 532999500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.016351 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 15546 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 12 # number of overall MSHR hits
system.cpu.l2cache.replacements 709 # number of replacements
system.cpu.l2cache.sampled_refs 15518 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 8487.111934 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 8487.111783 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1598481 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 32 # number of writebacks
system.cpu.memDep0.conflictingLoads 436025 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 249497 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 24681131 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5533285 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 157552604 # number of misc regfile reads
+system.cpu.memDep0.insertedLoads 24681129 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 5533282 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 157552597 # number of misc regfile reads
system.cpu.misc_regfile_writes 1603309 # number of misc regfile writes
-system.cpu.numCycles 112109302 # number of cpu cycles simulated
+system.cpu.numCycles 112109304 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 294826 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 72061910 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4906 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 29931124 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 29931132 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 31548 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 277459118 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 106593773 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 83924761 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 72730212 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 2697133 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 723330 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 11862848 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 277443671 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 106593764 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 83924752 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 72730204 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2697135 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 723329 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 11862839 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 474 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 277458644 # Number of integer rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 277443197 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 5701177 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 592742 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 1065555 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 576556 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 212048427 # The number of ROB reads
-system.cpu.rob.rob_writes 208775903 # The number of ROB writes
+system.cpu.rob.rob_reads 212048419 # The number of ROB reads
+system.cpu.rob.rob_writes 208775892 # The number of ROB writes
system.cpu.timesIdled 1292 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x402807b6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xbeffffee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x403387de.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:56:25
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 15:43:32
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 365535797000 because target called exit()
+Exiting @ tick 365986074500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 89247 # Simulator instruction rate (inst/s)
-host_mem_usage 242220 # Number of bytes of host memory used
-host_seconds 6290.45 # Real time elapsed on the host
-host_tick_rate 58109668 # Simulator tick rate (ticks/s)
+host_inst_rate 77433 # Simulator instruction rate (inst/s)
+host_mem_usage 260740 # Number of bytes of host memory used
+host_seconds 7232.86 # Real time elapsed on the host
+host_tick_rate 50600448 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 561403855 # Number of instructions simulated
-sim_seconds 0.365536 # Number of seconds simulated
-sim_ticks 365535797000 # Number of ticks simulated
+sim_insts 560059971 # Number of instructions simulated
+sim_seconds 0.365986 # Number of seconds simulated
+sim_ticks 365986074500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 140412857 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 174405829 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 140387936 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 174401300 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 15516134 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 191856696 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 191856696 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 15511612 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 191766015 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 191766015 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 110089780 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3543910 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3558142 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 660408748 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.850085 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.259950 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 662070266 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.847952 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.257926 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 341979114 51.78% 51.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 195474584 29.60% 81.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 65236254 9.88% 91.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 25100650 3.80% 95.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 18282819 2.77% 97.83% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 7231568 1.10% 98.92% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 2404526 0.36% 99.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 1155323 0.17% 99.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 3543910 0.54% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 343782937 51.93% 51.93% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 194895590 29.44% 81.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 65587700 9.91% 91.27% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 25120372 3.79% 95.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 18782135 2.84% 97.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 6815428 1.03% 98.93% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 2394801 0.36% 99.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1133161 0.17% 99.46% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 3558142 0.54% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 660408748 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 662070266 # Number of insts commited each cycle
system.cpu.commit.COM:count 561403855 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 184987501 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 27361456 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 26429304 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 561403855 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 157189 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 399600068 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 561403855 # Number of Instructions Simulated
-system.cpu.committedInsts_total 561403855 # Number of Instructions Simulated
-system.cpu.cpi 1.302220 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.302220 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 149781892 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 10115.689557 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6757.918127 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 148783591 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 10098503000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.006665 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 998301 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 174053 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 5570200500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.005503 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 824248 # number of ReadReq MSHR misses
+system.cpu.commit.commitSquashedInsts 399418051 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 560059971 # Number of Instructions Simulated
+system.cpu.committedInsts_total 560059971 # Number of Instructions Simulated
+system.cpu.cpi 1.306953 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.306953 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 149905369 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 10172.883940 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 6761.781933 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 148899998 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 10227522500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.006707 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 1005371 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 179403 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 5585015500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.005510 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 825968 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 55727847 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14769.740800 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13602.051977 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 54444667 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 18952236000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.023026 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1283180 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 935759 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 4725638500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.006234 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 347421 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 14757.173065 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13626.207417 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 54433003 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 19108237000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.023235 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1294844 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 947408 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 4734235000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.006235 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 347436 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 173.452238 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 173.284886 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 205509739 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 12733.281145 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 203228258 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 29050739000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.011102 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2281481 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1109812 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10295839000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.005701 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1171669 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 205633216 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 12753.485870 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 8794.286111 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 203333001 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 29335759500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.011186 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2300215 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1126811 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 10319250500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005706 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1173404 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.992538 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4065.435193 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 205509739 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 12733.281145 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 8787.327308 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.992547 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4065.472807 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 205633216 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 12753.485870 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 8794.286111 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 203228258 # number of overall hits
-system.cpu.dcache.overall_miss_latency 29050739000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.011102 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2281481 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 1109812 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10295839000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005701 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1171669 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 203333001 # number of overall hits
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+system.cpu.dcache.overall_miss_rate 0.011186 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2300215 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1126811 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 10319250500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005706 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1173404 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1167571 # number of replacements
-system.cpu.dcache.sampled_refs 1171667 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1169307 # number of replacements
+system.cpu.dcache.sampled_refs 1173403 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4065.435193 # Cycle average of tags in use
-system.cpu.dcache.total_refs 203228263 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 6053773000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 1048319 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 23914899 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 1082691365 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 293791436 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 339619753 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 66259738 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 3082660 # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse 4065.472807 # Cycle average of tags in use
+system.cpu.dcache.total_refs 203333005 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 6053772000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 1049504 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 23915687 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 1082602718 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 296214320 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 338871926 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 65446321 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 3068332 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 191856696 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 122785155 # Number of cache lines fetched
-system.cpu.fetch.Cycles 351913139 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 3732953 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 938955668 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 5443516 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 27647770 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.262432 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 122785155 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 140412857 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.284355 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 726668486 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.538402 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.455586 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 191766015 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 122748340 # Number of cache lines fetched
+system.cpu.fetch.Cycles 351971872 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 3710699 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 938893733 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 4527385 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 26711690 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.261985 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 122748340 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 140387936 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.282691 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 727516586 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.537241 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.455426 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 375480392 51.67% 51.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 167711007 23.08% 74.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 28511073 3.92% 78.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 34539499 4.75% 83.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 26732700 3.68% 87.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 10963415 1.51% 88.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 11441350 1.57% 90.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 11151746 1.53% 91.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 60137304 8.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 376259318 51.72% 51.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 167730540 23.06% 74.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 28515235 3.92% 78.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 34553707 4.75% 83.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 26720758 3.67% 87.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 10947410 1.50% 88.62% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 11409505 1.57% 90.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 11171933 1.54% 91.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 60208180 8.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 726668486 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 727516586 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 122785155 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 13335.070892 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 9658.160050 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 122768369 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 223842500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 122748340 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 13369.913613 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 9679.346455 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 122731555 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 224414000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000137 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 16786 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 916 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 153275000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 16785 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 933 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 153437000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000129 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 15870 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 15852 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 7736.852092 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 7742.827266 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 122785155 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 13335.070892 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency
-system.cpu.icache.demand_hits 122768369 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 223842500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 122748340 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 13369.913613 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency
+system.cpu.icache.demand_hits 122731555 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 224414000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000137 # miss rate for demand accesses
-system.cpu.icache.demand_misses 16786 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 916 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 153275000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 16785 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 933 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 153437000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000129 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 15870 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 15852 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.542928 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1111.916228 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 122785155 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 13335.070892 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 9658.160050 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.543111 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1112.290548 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 122748340 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 13369.913613 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 9679.346455 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 122768369 # number of overall hits
-system.cpu.icache.overall_miss_latency 223842500 # number of overall miss cycles
+system.cpu.icache.overall_hits 122731555 # number of overall hits
+system.cpu.icache.overall_miss_latency 224414000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000137 # miss rate for overall accesses
-system.cpu.icache.overall_misses 16786 # number of overall misses
-system.cpu.icache.overall_mshr_hits 916 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 153275000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 16785 # number of overall misses
+system.cpu.icache.overall_mshr_hits 933 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 153437000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000129 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 15870 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 15852 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 14020 # number of replacements
-system.cpu.icache.sampled_refs 15868 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 14002 # number of replacements
+system.cpu.icache.sampled_refs 15851 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1111.916228 # Cycle average of tags in use
-system.cpu.icache.total_refs 122768369 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1112.290548 # Cycle average of tags in use
+system.cpu.icache.total_refs 122731555 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 4403109 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 125406817 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.996154 # Inst execution rate
-system.cpu.iew.EXEC:refs 229537979 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 71989836 # Number of stores executed
+system.cpu.idleCycles 4455564 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 125457274 # Number of branches executed
+system.cpu.iew.EXEC:nop 13838185 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.981178 # Inst execution rate
+system.cpu.iew.EXEC:refs 229700627 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 72018658 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 715317405 # num instructions consuming a value
-system.cpu.iew.WB:count 674936623 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.509545 # average fanout of values written-back
+system.cpu.iew.WB:consumers 714382081 # num instructions consuming a value
+system.cpu.iew.WB:count 665966048 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.510315 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 364486134 # num instructions producing a value
-system.cpu.iew.WB:rate 0.923215 # insts written-back per cycle
-system.cpu.iew.WB:sent 715720315 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 30103584 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2644883 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 200154824 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 162257 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 12097440 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 140083731 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 960991852 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 157548143 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 31983856 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 728259959 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 123835 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 364559924 # num instructions producing a value
+system.cpu.iew.WB:rate 0.909824 # insts written-back per cycle
+system.cpu.iew.WB:sent 705629563 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 29041716 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2636135 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 199993331 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 162274 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 12088796 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 140409395 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 960810723 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 157681969 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 32008551 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 718194992 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 117672 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 3633 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 66259738 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 187555 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 3801 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 65446321 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 180324 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 4454393 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 9891 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.forwLoads 4458450 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 9743 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 352056 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 12768 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 72027799 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 83223254 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 352056 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 15636111 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 14467473 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 1624866525 # number of integer regfile reads
-system.cpu.int_regfile_writes 504061562 # number of integer regfile writes
-system.cpu.ipc 0.767919 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.767919 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 347516 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 11819 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 71866306 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 83548918 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 347516 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 14571260 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 14470456 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 1616277270 # number of integer regfile reads
+system.cpu.int_regfile_writes 504274200 # number of integer regfile writes
+system.cpu.ipc 0.765138 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.765138 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.79% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.79% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 67.79% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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-system.cpu.iq.ISSUE:fu_busy_rate 0.015076 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 750203543 # Type of FU issued
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system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 133776 1.17% 1.17% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.17% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdAdd 0 0.00% 1.17% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::SimdFloatAdd 0 0.00% 1.17% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::SimdFloatAlu 0 0.00% 1.17% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.384447 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::1 195069580 26.84% 73.58% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::3 40650184 5.59% 93.20% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 24674774 3.40% 96.60% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 15399691 2.12% 98.72% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 3388059 0.47% 99.18% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 4145144 0.57% 99.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 1791987 0.25% 100.00% # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::7 4087676 0.56% 99.76% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 726668486 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.039903 # Inst issue rate
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+system.cpu.iq.ISSUE:rate 1.024907 # Inst issue rate
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system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 652 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 771704903 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 2266614625 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 674936607 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 1350317509 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 960829595 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 760243815 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 162257 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 389023744 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 7997557 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 5068 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 710003502 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.fp_inst_queue_writes 598 # Number of floating instruction queue writes
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+system.cpu.iq.int_inst_queue_writes 1323699335 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 946810264 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 750203543 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 162274 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 376428693 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 8018474 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 5085 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 702572396 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 347847 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34254.310886 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.170745 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 228324 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 4094178000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.343608 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 119523 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705711500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343608 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 119523 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 839688 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34183.859863 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.526653 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 724943 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 3922427000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.136652 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 114745 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_accesses 347863 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34247.596496 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31004.740070 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 228350 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 4093033000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.343563 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 119513 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 3705469500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.343563 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 119513 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 841391 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34185.632593 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.780138 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 726325 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 3933604000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.136757 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 115066 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 30 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency 3558405000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.136616 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 114715 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 2 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_hits 2 # number of UpgradeReq hits
-system.cpu.l2cache.Writeback_accesses 1048319 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 1048319 # number of Writeback hits
+system.cpu.l2cache.ReadReq_mshr_miss_latency 3568621500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.136721 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 115036 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_hits 1 # number of UpgradeReq hits
+system.cpu.l2cache.Writeback_accesses 1049504 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 1049504 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 6.336020 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 6.339320 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1187535 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34219.803814 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 953267 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 8016605000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.197273 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 234268 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 1189254 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34217.201881 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 954675 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 8026637000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.197249 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 234579 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 30 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7264116500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.197247 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 234238 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 7274091000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.197224 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 234549 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.185686 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.450094 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 6084.559967 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14748.682079 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 1187535 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34219.803814 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.691101 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.185910 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.449873 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 6091.890422 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14741.450627 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 1189254 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34217.201881 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.097476 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 953267 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 8016605000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.197273 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 234268 # number of overall misses
+system.cpu.l2cache.overall_hits 954675 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 8026637000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.197249 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 234579 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 30 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7264116500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.197247 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 234238 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 7274091000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.197224 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 234549 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 215168 # number of replacements
-system.cpu.l2cache.sampled_refs 235364 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 215449 # number of replacements
+system.cpu.l2cache.sampled_refs 235636 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 20833.242046 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 1491271 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 262458362000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 171581 # number of writebacks
-system.cpu.memDep0.conflictingLoads 60170710 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 74734099 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 200154824 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 140083731 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 1169165868 # number of misc regfile reads
+system.cpu.l2cache.tagsinuse 20833.341048 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 1493772 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 262779341000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 171632 # number of writebacks
+system.cpu.memDep0.conflictingLoads 58798533 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 76400324 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 199993331 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 140409395 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 1169227072 # number of misc regfile reads
system.cpu.misc_regfile_writes 344748 # number of misc regfile writes
-system.cpu.numCycles 731071595 # number of cpu cycles simulated
+system.cpu.numCycles 731972150 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 7125233 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 7146790 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 435368498 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 5221350 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 309286671 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 9288405 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 16 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 2644676144 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 1043986494 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 713690265 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 326862324 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 66259738 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 15428382 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 278321764 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 2110 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 2644674034 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 1706138 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 233255 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 48704887 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 185624 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 1617861624 # The number of ROB reads
-system.cpu.rob.rob_writes 1988299741 # The number of ROB writes
-system.cpu.timesIdled 93433 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 5207540 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 311739226 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 9258079 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 2640447492 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 1043812056 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 713532745 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 325976886 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 65446321 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15480980 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 278164244 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 1939 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 2640445553 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 1726383 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 233275 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 49072391 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 185712 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 1619326892 # The number of ROB reads
+system.cpu.rob.rob_writes 1987147936 # The number of ROB writes
+system.cpu.timesIdled 95874 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
---------- End Simulation Statistics ----------
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
12 8 14
13 8 14
14 8 14
-warn: Bad interworking branch address 0x7ceeeeee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7dfefefe.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7cb6b6b6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e929292.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e9a9a9a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e9a9a9a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ea2a2a2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e868686.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7da6a6a6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7eaeaeae.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7deaeaea.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7dc2c2c2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7d828282.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ea6a6a6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e9e9e9e.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7de2e2e2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7cfefefe.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7d9e9e9e.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7dfefefe.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e9a9a9a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e9a9a9a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ddadada.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e828282.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7e8a8a8a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ea2a2a2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7eb6b6b6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7edadada.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ebababa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ef6f6f6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x80868686.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7faeaeae.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7faaaaaa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7f8e8e8e.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ee2e2e2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7f868686.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fa6a6a6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7f969696.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fd2d2d2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fcecece.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ff6f6f6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7feaeaea.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fdadada.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fe6e6e6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7f8a8a8a.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7feaeaea.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fdedede.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7feeeeee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ff2f2f2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7ff2f2f2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7feeeeee.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fd6d6d6.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7fd2d2d2.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0x7faeaeae.
-For more information see: http://www.m5sim.org/warn/55f199fd
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:56:35
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:41:06
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.210000
-Exiting @ tick 215422929500 because target called exit()
+Exiting @ tick 215422930500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 72451 # Simulator instruction rate (inst/s)
-host_mem_usage 252856 # Number of bytes of host memory used
-host_seconds 4758.76 # Real time elapsed on the host
-host_tick_rate 45268689 # Simulator tick rate (ticks/s)
+host_inst_rate 59988 # Simulator instruction rate (inst/s)
+host_mem_usage 271504 # Number of bytes of host memory used
+host_seconds 5747.46 # Real time elapsed on the host
+host_tick_rate 37481445 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 344777955 # Number of instructions simulated
+sim_insts 344777343 # Number of instructions simulated
sim_seconds 0.215423 # Number of seconds simulated
-sim_ticks 215422929500 # Number of ticks simulated
+sim_ticks 215422930500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 29670463 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 36719834 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 29670488 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 36719835 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 7622670 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 36869176 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 36869176 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 7622671 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 36869177 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 36869177 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 28188953 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 5177395 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 5177396 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 417225954 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 417225904 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.826358 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.412065 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 233100827 55.87% 55.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 116424181 27.90% 83.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 32132758 7.70% 91.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 233100746 55.87% 55.87% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 116424213 27.90% 83.77% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 32132757 7.70% 91.48% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 14133629 3.39% 94.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 7357054 1.76% 96.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 4244458 1.02% 97.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 2971859 0.71% 98.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 1683793 0.40% 98.76% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 5177395 1.24% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 7357055 1.76% 96.63% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 4244457 1.02% 97.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 2971889 0.71% 98.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 1683762 0.40% 98.76% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 5177396 1.24% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 417225954 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 417225904 # Number of insts commited each cycle
system.cpu.commit.COM:count 344777955 # Number of instructions committed
system.cpu.commit.COM:fp_insts 114216705 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 177028572 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 9986423 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 9986408 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 344777955 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 3533298 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 48561535 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 344777955 # Number of Instructions Simulated
-system.cpu.committedInsts_total 344777955 # Number of Instructions Simulated
-system.cpu.cpi 1.249633 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.249633 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 98212602 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32812.217924 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30418.895349 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 98209500 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 101783500 # number of ReadReq miss cycles
+system.cpu.commit.commitSquashedInsts 48561453 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 344777343 # Number of Instructions Simulated
+system.cpu.committedInsts_total 344777343 # Number of Instructions Simulated
+system.cpu.cpi 1.249635 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.249635 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 98212603 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 32812.379110 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30419.186047 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 98209501 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 101784000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000032 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 3102 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 1382 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 52320500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 52321000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000018 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1720 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_mshr_misses 2850 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 11781.250000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 39442.992779 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 39442.992998 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 188500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 180276174 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30186.293036 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33582.275711 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 180254477 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 654952000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 180276175 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30186.316081 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33582.385120 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 180254478 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 654952500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000120 # miss rate for demand accesses
system.cpu.dcache.demand_misses 21697 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 17127 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 153471000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 153471500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 4570 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.755653 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3095.155920 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 180276174 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30186.293036 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33582.275711 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 3095.155896 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 180276175 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30186.316081 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33582.385120 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 180254477 # number of overall hits
-system.cpu.dcache.overall_miss_latency 654952000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 180254478 # number of overall hits
+system.cpu.dcache.overall_miss_latency 654952500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000120 # miss rate for overall accesses
system.cpu.dcache.overall_misses 21697 # number of overall misses
system.cpu.dcache.overall_mshr_hits 17127 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 153471000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 153471500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 4570 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 1402 # number of replacements
system.cpu.dcache.sampled_refs 4570 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3095.155920 # Cycle average of tags in use
-system.cpu.dcache.total_refs 180254477 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3095.155896 # Cycle average of tags in use
+system.cpu.dcache.total_refs 180254478 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 1028 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 135683877 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 445047974 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 110691347 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 165193341 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 13510660 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BlockedCycles 135683876 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 445047864 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 110691412 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 165193226 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 13510644 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 5657389 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 36869176 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 45676058 # Number of cache lines fetched
-system.cpu.fetch.Cycles 181360432 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 631539 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 363476722 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 18599 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 9990891 # Number of cycles fetch has spent squashing
+system.cpu.fetch.Branches 36869177 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 45676128 # Number of cache lines fetched
+system.cpu.fetch.Cycles 181360333 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 631577 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 363476608 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 18583 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 9990877 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.085574 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 45676058 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 29670463 # Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 45676128 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 29670488 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.843635 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 430736614 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 430736547 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.090672 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.994313 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 252892328 58.71% 58.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 95422194 22.15% 80.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 252892375 58.71% 58.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 95422079 22.15% 80.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 21830959 5.07% 85.93% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 14061343 3.26% 89.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 11029779 2.56% 91.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 8719423 2.02% 93.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 4691834 1.09% 94.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 4691835 1.09% 94.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4052981 0.94% 95.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 18035773 4.19% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 430736614 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 430736547 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 185889152 # number of floating regfile reads
system.cpu.fp_regfile_writes 130863264 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 45676058 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 11498.094859 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.634691 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 45658474 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 202182500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 45676128 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 11498.066424 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 7998.605010 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 45658544 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 202182000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000385 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 17584 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 738 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 134745000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 134744500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000369 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 16846 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 2710.666944 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 2710.671100 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 45676058 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 11498.094859 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 7998.634691 # average overall mshr miss latency
-system.cpu.icache.demand_hits 45658474 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 202182500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 45676128 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 11498.066424 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 7998.605010 # average overall mshr miss latency
+system.cpu.icache.demand_hits 45658544 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 202182000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000385 # miss rate for demand accesses
system.cpu.icache.demand_misses 17584 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 738 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 134745000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 134744500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000369 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 16846 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.897245 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1837.557212 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 45676058 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 11498.094859 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 7998.634691 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 1837.557197 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 45676128 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 11498.066424 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 7998.605010 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 45658474 # number of overall hits
-system.cpu.icache.overall_miss_latency 202182500 # number of overall miss cycles
+system.cpu.icache.overall_hits 45658544 # number of overall hits
+system.cpu.icache.overall_miss_latency 202182000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000385 # miss rate for overall accesses
system.cpu.icache.overall_misses 17584 # number of overall misses
system.cpu.icache.overall_mshr_hits 738 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 134745000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 134744500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000369 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 16846 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 14975 # number of replacements
system.cpu.icache.sampled_refs 16844 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1837.557212 # Cycle average of tags in use
-system.cpu.icache.total_refs 45658474 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1837.557197 # Cycle average of tags in use
+system.cpu.icache.total_refs 45658544 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 109246 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 29572211 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.858504 # Inst execution rate
-system.cpu.iew.EXEC:refs 185717004 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 85614435 # Number of stores executed
+system.cpu.idleCycles 109315 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 29572151 # Number of branches executed
+system.cpu.iew.EXEC:nop 511948 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.857328 # Inst execution rate
+system.cpu.iew.EXEC:refs 185716991 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 85614422 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 264958674 # num instructions consuming a value
-system.cpu.iew.WB:count 365790604 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.549025 # average fanout of values written-back
+system.cpu.iew.WB:consumers 264871547 # num instructions consuming a value
+system.cpu.iew.WB:count 365283823 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.549146 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 145468948 # num instructions producing a value
-system.cpu.iew.WB:rate 0.849006 # insts written-back per cycle
-system.cpu.iew.WB:sent 367353689 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 10421858 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 145453119 # num instructions producing a value
+system.cpu.iew.WB:rate 0.847829 # insts written-back per cycle
+system.cpu.iew.WB:sent 366846883 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 10421797 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4450 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 108215524 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 108215518 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 3540937 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 11257749 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 93620853 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 393342022 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 11257763 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 93620838 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 393341940 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 100102569 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7571412 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 369883065 # Number of executed instructions
+system.cpu.iew.iewExecSquashedInsts 7587099 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 369376260 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 69 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 9 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 13510660 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 13510644 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 176 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 37 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 6487 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 33 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 13562546 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 11245258 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 13562540 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 11245243 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 6487 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 2859204 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 2859143 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 7562654 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 857434842 # number of integer regfile reads
-system.cpu.int_regfile_writes 187420899 # number of integer regfile writes
-system.cpu.ipc 0.800235 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.800235 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 856895426 # number of integer regfile reads
+system.cpu.int_regfile_writes 187404557 # number of integer regfile writes
+system.cpu.ipc 0.800234 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.800234 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 130407630 34.55% 34.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 2146058 0.57% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 679 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 2 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6735975 1.78% 36.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.90% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8317099 2.20% 39.11% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3313873 0.88% 39.98% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1566398 0.41% 40.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20555034 5.45% 45.84% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7151488 1.89% 47.74% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7075439 1.87% 49.61% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.66% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 102612479 27.19% 76.85% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 87397034 23.15% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 129916529 34.46% 34.46% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 2146058 0.57% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 3 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 679 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 2 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 35.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 6735975 1.79% 36.82% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 36.82% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 8317099 2.21% 39.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 3313873 0.88% 39.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 1566398 0.42% 40.32% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 20555034 5.45% 45.77% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 7151488 1.90% 47.67% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 7075439 1.88% 49.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 175286 0.05% 49.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 102612475 27.22% 76.82% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 87397021 23.18% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 377454477 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 6999236 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018543 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 376963359 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 6999234 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018567 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 204 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 202 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 5040 0.07% 0.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.07% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 588 0.01% 2.17% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 183278 2.62% 4.79% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 4.79% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 4924134 70.35% 75.14% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 1739681 24.86% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 4924135 70.35% 75.14% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 1739680 24.86% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 430736614 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.876300 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.213056 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 430736547 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.875160 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.210569 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 218913895 50.82% 50.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 123057011 28.57% 79.39% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 46006225 10.68% 90.07% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 20712551 4.81% 94.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 13744591 3.19% 98.07% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 5457639 1.27% 99.34% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 2167994 0.50% 99.84% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 440824 0.10% 99.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 235884 0.05% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 218916849 50.82% 50.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 123149552 28.59% 79.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 45929825 10.66% 90.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 20859984 4.84% 94.92% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 13764585 3.20% 98.12% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 5289881 1.23% 99.34% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 2150519 0.50% 99.84% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 439470 0.10% 99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 235882 0.05% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 430736614 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.876078 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 122762429 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 242026964 # Number of floating instruction queue reads
+system.cpu.iq.ISSUE:issued_per_cycle::total 430736547 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.874938 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 122762431 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 242026966 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 116081453 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 130324765 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 261691284 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 951420966 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 249709151 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 308466887 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 389801085 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 377454477 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 261200162 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 950433097 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 249202370 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 307537991 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 389289055 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 376963359 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 3540937 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 45444738 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 803126 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 45027872 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 797564 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 7639 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 100178963 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 100142647 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.104167 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.011647 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3413.355602 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 381.656203 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 3413.355578 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 381.656201 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 21416 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 34344.019471 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.535184 # average overall mshr miss latency
system.cpu.l2cache.replacements 55 # number of replacements
system.cpu.l2cache.sampled_refs 5231 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3795.011805 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 3795.011778 # Cycle average of tags in use
system.cpu.l2cache.total_refs 14289 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 34606299 # Number of conflicting loads.
+system.cpu.memDep0.conflictingLoads 34606296 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 43565672 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 108215524 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 93620853 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 1021297951 # number of misc regfile reads
+system.cpu.memDep0.insertedLoads 108215518 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 93620838 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 1021297842 # number of misc regfile reads
system.cpu.misc_regfile_writes 43097547 # number of misc regfile writes
-system.cpu.numCycles 430845860 # number of cpu cycles simulated
+system.cpu.numCycles 430845862 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 2009946 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 340171955 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2410 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 122720704 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 4353276 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 1678823809 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 427512242 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 413848674 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 159405057 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 13510660 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 15892138 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 73676716 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:IdleCycles 122720761 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 4353275 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 1678808180 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 427512132 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 413848551 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 159404950 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 13510644 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15892137 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 73676593 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 836456573 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 842367236 # Number of integer rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 842351607 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 117198109 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 12788197 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 37692287 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 37692284 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 3543781 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 805385527 # The number of ROB reads
-system.cpu.rob.rob_writes 800205983 # The number of ROB writes
-system.cpu.timesIdled 2211 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 805385393 # The number of ROB reads
+system.cpu.rob.rob_writes 800205802 # The number of ROB writes
+system.cpu.timesIdled 2213 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
---------- End Simulation Statistics ----------
For more information see: http://www.m5sim.org/warn/d946bea6
warn: fcntl64(3, 2) passed through to host
For more information see: http://www.m5sim.org/warn/a55e2c46
-warn: Bad interworking branch address 0x66.
-For more information see: http://www.m5sim.org/warn/55f199fd
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 02:00:50
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 15:06:31
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 1106986290500 because target called exit()
+Exiting @ tick 1106986295500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 139604 # Simulator instruction rate (inst/s)
-host_mem_usage 244852 # Number of bytes of host memory used
-host_seconds 13207.13 # Real time elapsed on the host
-host_tick_rate 83817309 # Simulator tick rate (ticks/s)
+host_inst_rate 80651 # Simulator instruction rate (inst/s)
+host_mem_usage 263088 # Number of bytes of host memory used
+host_seconds 22860.92 # Real time elapsed on the host
+host_tick_rate 48422649 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1843766922 # Number of instructions simulated
+sim_insts 1843755906 # Number of instructions simulated
sim_seconds 1.106986 # Number of seconds simulated
-sim_ticks 1106986290500 # Number of ticks simulated
+sim_ticks 1106986295500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 334577288 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 553224056 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 334577290 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 553224059 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 46883845 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 562377077 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 562377077 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 46883846 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 562377080 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 562377080 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 258172659 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 41405242 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 41405243 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 2026425019 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 2026424997 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.909862 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 1.566343 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 1126460049 55.59% 55.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 1126460027 55.59% 55.59% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::1 528416767 26.08% 81.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::2 168171926 8.30% 89.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::3 70727286 3.49% 93.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 47338472 2.34% 95.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 23657957 1.17% 96.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 47338473 2.34% 95.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 23657956 1.17% 96.96% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 13792404 0.68% 97.64% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 6454916 0.32% 97.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 41405242 2.04% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 6454915 0.32% 97.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 41405243 2.04% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 2026425019 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 2026424997 # Number of insts commited each cycle
system.cpu.commit.COM:count 1843766922 # Number of instructions committed
system.cpu.commit.COM:fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 908401145 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 84212939 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 84212929 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1843766922 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 188261 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1168824216 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1843766922 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1843766922 # Number of Instructions Simulated
-system.cpu.cpi 1.200788 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.200788 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 714254562 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34305.778645 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836125 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 712322725 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 66273172500 # number of ReadReq miss cycles
+system.cpu.commit.commitSquashedInsts 1168824477 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1843755906 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1843755906 # Number of Instructions Simulated
+system.cpu.cpi 1.200795 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.200795 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 714254563 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34305.782527 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34068.836467 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 712322726 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 66273180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002705 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1931837 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 467831 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 49876980500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 49876981000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002050 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1464006 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 276945664 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_mshr_misses 72472 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 10666.666667 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 643.332594 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 643.332595 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 32000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 991200226 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34560.484046 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618594 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 988465075 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 94528142500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 991200227 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 34560.486788 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 988465076 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 94528150000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.002759 # miss rate for demand accesses
system.cpu.dcache.demand_misses 2735151 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 1198673 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 52238129500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 52238130000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.001550 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 1536478 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999786 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.125013 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 991200226 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34560.484046 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618594 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4095.125005 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 991200227 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 34560.486788 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 33998.618919 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 988465075 # number of overall hits
-system.cpu.dcache.overall_miss_latency 94528142500 # number of overall miss cycles
+system.cpu.dcache.overall_hits 988465076 # number of overall hits
+system.cpu.dcache.overall_miss_latency 94528150000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.002759 # miss rate for overall accesses
system.cpu.dcache.overall_misses 2735151 # number of overall misses
system.cpu.dcache.overall_mshr_hits 1198673 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 52238129500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 52238130000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.001550 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 1536478 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 1532380 # number of replacements
system.cpu.dcache.sampled_refs 1536476 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.125013 # Cycle average of tags in use
-system.cpu.dcache.total_refs 988465091 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 341946000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tagsinuse 4095.125005 # Cycle average of tags in use
+system.cpu.dcache.total_refs 988465092 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 341948000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106863 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 223702821 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3748475932 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 853302528 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 949015552 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 187283417 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BlockedCycles 223702819 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3748475941 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 853302516 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 949015542 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 187283447 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 404118 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 562377077 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 400588369 # Number of cache lines fetched
+system.cpu.fetch.Branches 562377080 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 400588374 # Number of cache lines fetched
system.cpu.fetch.Cycles 1002800662 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 11586078 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2972268186 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 34327 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 86966878 # Number of cycles fetch has spent squashing
+system.cpu.fetch.IcacheSquashes 11586077 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2972268197 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 34317 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 86966870 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.254013 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 400588369 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 334577288 # Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 400588374 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 334577290 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 1.342505 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 2213708436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 2213708442 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.777306 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 2.798612 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1213776786 54.83% 54.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 388415263 17.55% 72.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1213776792 54.83% 54.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 388415260 17.55% 72.38% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 93122307 4.21% 76.58% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 48895921 2.21% 78.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 60943546 2.75% 81.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 76981670 3.48% 85.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 16173404 0.73% 85.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 35829918 1.62% 87.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 279569621 12.63% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 16173405 0.73% 85.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 35829919 1.62% 87.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 279569622 12.63% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 2213708436 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 2213708442 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 66048246 # number of floating regfile reads
system.cpu.fp_regfile_writes 52282096 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 400588369 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 8967.410787 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.276669 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 400557684 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 275165000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 400588374 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 8967.427082 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 5871.293987 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 400557689 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 275165500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000077 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 30685 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1813 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 169515500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 169516000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000072 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 28872 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 13875.010704 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 13875.010877 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 400588369 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 8967.410787 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 5871.276669 # average overall mshr miss latency
-system.cpu.icache.demand_hits 400557684 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 275165000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 400588374 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 8967.427082 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency
+system.cpu.icache.demand_hits 400557689 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 275165500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000077 # miss rate for demand accesses
system.cpu.icache.demand_misses 30685 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1813 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 169515500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 169516000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000072 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 28872 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.814790 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1668.688983 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 400588369 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 8967.410787 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 5871.276669 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 1668.688980 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 400588374 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 8967.427082 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 5871.293987 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 400557684 # number of overall hits
-system.cpu.icache.overall_miss_latency 275165000 # number of overall miss cycles
+system.cpu.icache.overall_hits 400557689 # number of overall hits
+system.cpu.icache.overall_miss_latency 275165500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000077 # miss rate for overall accesses
system.cpu.icache.overall_misses 30685 # number of overall misses
system.cpu.icache.overall_mshr_hits 1813 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 169515500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 169516000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000072 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 28872 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 27162 # number of replacements
system.cpu.icache.sampled_refs 28869 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1668.688983 # Cycle average of tags in use
-system.cpu.icache.total_refs 400557684 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1668.688980 # Cycle average of tags in use
+system.cpu.icache.total_refs 400557689 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 264146 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 328211890 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.050140 # Inst execution rate
-system.cpu.iew.EXEC:refs 1122138305 # number of memory reference insts executed
+system.cpu.idleCycles 264150 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 328211891 # Number of branches executed
+system.cpu.iew.EXEC:nop 104784 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.050105 # Inst execution rate
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system.cpu.iew.EXEC:stores 367853547 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 2149738091 # num instructions consuming a value
-system.cpu.iew.WB:count 2244813187 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 2149736970 # num instructions consuming a value
+system.cpu.iew.WB:count 2244737126 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.548413 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1178945029 # num instructions producing a value
-system.cpu.iew.WB:rate 1.013930 # insts written-back per cycle
-system.cpu.iew.WB:sent 2267021093 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 93878046 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 1178943946 # num instructions producing a value
+system.cpu.iew.WB:rate 1.013896 # insts written-back per cycle
+system.cpu.iew.WB:sent 2266943895 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 93876953 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 4821399 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 976823890 # Number of dispatched load instructions
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system.cpu.iew.iewDispNonSpecInsts 9835077 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 65011205 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 487069954 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 3012606054 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 754284758 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 120224792 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2324980968 # Number of executed instructions
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+system.cpu.iew.iewDispStoreInsts 487070109 # Number of dispatched store instructions
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+system.cpu.iew.iewExecLoadInsts 754284759 # Number of load instructions executed
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system.cpu.iew.iewIQFullEvents 971459 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 242 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 187283417 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 1560904 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 187283447 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1560865 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 12454380 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread.0.memOrderViolation 2755264 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1382 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 345418041 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 210074657 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedLoads 345418040 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 210074812 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 2755264 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 45730558 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 45729465 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 48147488 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 5403725947 # number of integer regfile reads
-system.cpu.int_regfile_writes 1668305359 # number of integer regfile writes
-system.cpu.ipc 0.832787 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.832787 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 5403649891 # number of integer regfile reads
+system.cpu.int_regfile_writes 1668305360 # number of integer regfile writes
+system.cpu.ipc 0.832782 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.832782 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 49.37% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 49.37% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 49.37% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 49.37% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1195859034 48.91% 48.91% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::SimdAdd 16846 0.00% 49.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 49.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 49.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 6876473 0.28% 49.70% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 5501179 0.22% 49.93% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 49.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23390230 0.96% 50.89% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 50.89% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.89% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.89% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 793077281 32.43% 83.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 407863833 16.68% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 23390230 0.96% 50.88% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 50.88% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 50.88% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 793077280 32.43% 83.32% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 407863832 16.68% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 2445205760 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 60724254 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.024834 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 2445128542 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 60724253 # FU busy when requested
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system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 337 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IntMult 24113 0.04% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.04% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 16532363 27.23% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 1044197875 47.17% 47.17% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 536098097 24.22% 71.39% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 282654634 12.77% 84.16% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 162977150 7.36% 91.52% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 122131975 5.52% 97.03% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 40303840 1.82% 98.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 15378768 0.69% 99.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 7181539 0.32% 99.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 2784558 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 1044209874 47.17% 47.17% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 536089548 24.22% 71.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 282659967 12.77% 84.16% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 162995448 7.36% 91.52% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 122130271 5.52% 97.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 40278652 1.82% 98.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 15378668 0.69% 99.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 7181748 0.32% 99.87% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 2784266 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 2213708436 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.104443 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 2213708442 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.104408 # Inst issue rate
system.cpu.iq.fp_alu_accesses 64689412 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 126628637 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 56420382 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 101846831 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 2441240602 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 7046560079 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 2188392805 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 4055397012 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 3002770977 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2445205760 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 2441163383 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 7046405646 # Number of integer instruction queue reads
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+system.cpu.iq.iqInstsAdded 3002666337 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2445128542 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 9835077 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1141885172 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 8344506 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1141792420 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 8344504 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 9646816 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2082899377 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 2082844826 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.911922 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 66087 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1492876 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383234 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34237.383587 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.264277 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 77656 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 48453429500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 48453430000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.947982 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 1415220 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 1565346 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34249.025354 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34249.025692 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 84039 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 50733321000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 50733321500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.946313 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 1481307 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 39 # number of demand (read+write) MSHR hits
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.884785 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.091201 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 28992.645165 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 2988.461118 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 28992.645122 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 2988.461105 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1565346 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34249.025354 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34249.025692 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31000.307169 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 84039 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 50733321000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 50733321500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.946313 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 1481307 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 39 # number of overall MSHR hits
system.cpu.l2cache.replacements 1479999 # number of replacements
system.cpu.l2cache.sampled_refs 1512721 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31981.106283 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 31981.106227 # Cycle average of tags in use
system.cpu.l2cache.total_refs 85987 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66099 # number of writebacks
system.cpu.memDep0.conflictingLoads 48375882 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 167873780 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 976823890 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 487069954 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 4207984120 # number of misc regfile reads
+system.cpu.memDep0.insertedLoads 976823889 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 487070109 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 4207984132 # number of misc regfile reads
system.cpu.misc_regfile_writes 14227476 # number of misc regfile writes
-system.cpu.numCycles 2213972582 # number of cpu cycles simulated
+system.cpu.numCycles 2213972592 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 17658494 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1482327508 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4825678 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 919120381 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 919120367 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 8406320 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 1 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 9255875063 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3353421712 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2685986508 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 880460602 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 187283417 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 23975327 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1203658997 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 9255846830 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3353421825 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2685986513 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 880460594 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 187283447 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 23975324 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1203659002 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 485863672 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 8770011391 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 185210215 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:int_rename_lookups 8769983158 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 185210216 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 19466962 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 226114375 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 226114383 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 13965391 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 4997592572 # The number of ROB reads
-system.cpu.rob.rob_writes 6212467818 # The number of ROB writes
-system.cpu.timesIdled 87015 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 4997592808 # The number of ROB reads
+system.cpu.rob.rob_writes 6212468368 # The number of ROB writes
+system.cpu.timesIdled 87017 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
---------- End Simulation Statistics ----------
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: Bad interworking branch address 0x7002.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
-warn: Bad interworking branch address 0xa.
-For more information see: http://www.m5sim.org/warn/55f199fd
hack: be nice to actually delete the event here
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:56:24
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:37:23
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 59259979500 because target called exit()
+Exiting @ tick 59259968500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 60156 # Simulator instruction rate (inst/s)
-host_mem_usage 246816 # Number of bytes of host memory used
-host_seconds 1643.03 # Real time elapsed on the host
-host_tick_rate 36067570 # Simulator tick rate (ticks/s)
+host_inst_rate 56888 # Simulator instruction rate (inst/s)
+host_mem_usage 265416 # Number of bytes of host memory used
+host_seconds 1737.33 # Real time elapsed on the host
+host_tick_rate 34109858 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 98838077 # Number of instructions simulated
+sim_insts 98832525 # Number of instructions simulated
sim_seconds 0.059260 # Number of seconds simulated
-sim_ticks 59259979500 # Number of ticks simulated
+sim_ticks 59259968500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 10631376 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 17355232 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 10631378 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 17355234 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 914560 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 17451382 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 17451382 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 17451384 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 17451384 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 12133384 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 1268932 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 114018884 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.866857 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.400756 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 114018356 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.866861 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.400758 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 59418042 52.11% 52.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 36575306 32.08% 84.19% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 7815756 6.85% 91.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 3335762 2.93% 93.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 3218602 2.82% 96.79% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 1142108 1.00% 97.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 823063 0.72% 98.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 421313 0.37% 98.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 59417509 52.11% 52.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 36575314 32.08% 84.19% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 7815755 6.85% 91.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3335760 2.93% 93.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 3218603 2.82% 96.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1142107 1.00% 97.80% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 823062 0.72% 98.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 421314 0.37% 98.89% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 1268932 1.11% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 114018884 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 114018356 # Number of insts commited each cycle
system.cpu.commit.COM:count 98838077 # Number of instructions committed
system.cpu.commit.COM:fp_insts 56 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 47871033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 2496869 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 2496729 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 98838077 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 667791 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 18231626 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 98838077 # Number of Instructions Simulated
-system.cpu.committedInsts_total 98838077 # Number of Instructions Simulated
-system.cpu.cpi 1.199133 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.199133 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 28495397 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 22617.028157 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18828.183694 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 28388709 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2412965500 # number of ReadReq miss cycles
+system.cpu.commit.commitSquashedInsts 18231502 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 98832525 # Number of Instructions Simulated
+system.cpu.committedInsts_total 98832525 # Number of Instructions Simulated
+system.cpu.cpi 1.199200 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.199200 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 28495395 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 22616.985978 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18828.121969 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 28388707 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2412961000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.003744 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 106688 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 49985 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1067614500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1067611000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001990 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 56703 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 19865820 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32612.870291 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34110.136388 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 18320719 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 50390178500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 32612.833902 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34110.141072 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 18320717 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 50390187500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.077777 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1545101 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1438347 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3641393500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_misses 1545103 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1438349 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 3641394000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.005374 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 106754 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 285.786157 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 285.786132 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 21500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 48361217 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 31967.245211 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 46709428 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 52803144000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_accesses 48361215 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31967.209229 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 28808.830457 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 46709424 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 52803148500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.034155 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1651789 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 1488332 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4709008000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_misses 1651791 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 1488334 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4709005000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.003380 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 163457 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.995663 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4078.236319 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 48361217 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 31967.245211 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 28808.848810 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4078.236312 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 48361215 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31967.209229 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 28808.830457 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 46709428 # number of overall hits
-system.cpu.dcache.overall_miss_latency 52803144000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 46709424 # number of overall hits
+system.cpu.dcache.overall_miss_latency 52803148500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.034155 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1651789 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 1488332 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4709008000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_misses 1651791 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 1488334 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4709005000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.003380 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 163457 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 159346 # number of replacements
system.cpu.dcache.sampled_refs 163442 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4078.236319 # Cycle average of tags in use
-system.cpu.dcache.total_refs 46709461 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 4078.236312 # Cycle average of tags in use
+system.cpu.dcache.total_refs 46709457 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 393981000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 124385 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 14942645 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 127014948 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 27511704 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 70998513 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 3514572 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 566022 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles 14942635 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 127014816 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 27511316 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 70998383 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 3514410 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 566021 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 17451382 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 12122688 # Number of cache lines fetched
-system.cpu.fetch.Cycles 73872074 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Branches 17451384 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 12122691 # Number of cache lines fetched
+system.cpu.fetch.Cycles 73872078 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 96174 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 95885012 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 34128 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 2507897 # Number of cycles fetch has spent squashing
+system.cpu.fetch.Insts 95885018 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 33989 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 2507758 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.147244 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 12122688 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 10631376 # Number of branches that fetch has predicted taken
+system.cpu.fetch.icacheStallCycles 12122691 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 10631378 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.809020 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 117533456 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.108172 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.634523 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 117532765 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.108179 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 1.634526 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 43866274 37.32% 37.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 53998301 45.94% 83.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9118937 7.76% 91.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 43865579 37.32% 37.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 53998302 45.94% 83.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 9118939 7.76% 91.02% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 3358983 2.86% 93.88% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1352835 1.15% 95.03% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 476061 0.41% 95.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1116299 0.95% 96.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1116300 0.95% 96.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 521407 0.44% 96.83% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 3724359 3.17% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 117533456 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 117532765 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 58 # number of floating regfile reads
system.cpu.fp_regfile_writes 40 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 12122688 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12759.423411 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 9476.994450 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 12098546 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 308038000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 12122691 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12759.444122 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 9477.015634 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 12098549 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 308038500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.001991 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 24142 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 539 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 223685500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 223686000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001947 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 23603 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 512.911056 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 512.911184 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 12122688 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12759.423411 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency
-system.cpu.icache.demand_hits 12098546 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 308038000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 12122691 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12759.444122 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 9477.015634 # average overall mshr miss latency
+system.cpu.icache.demand_hits 12098549 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 308038500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.001991 # miss rate for demand accesses
system.cpu.icache.demand_misses 24142 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 539 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 223685500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 223686000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.001947 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 23603 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.878284 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1798.726213 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 12122688 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12759.423411 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 9476.994450 # average overall mshr miss latency
+system.cpu.icache.occ_blocks::0 1798.726219 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 12122691 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12759.444122 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 9477.015634 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 12098546 # number of overall hits
-system.cpu.icache.overall_miss_latency 308038000 # number of overall miss cycles
+system.cpu.icache.overall_hits 12098549 # number of overall hits
+system.cpu.icache.overall_miss_latency 308038500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.001991 # miss rate for overall accesses
system.cpu.icache.overall_misses 24142 # number of overall misses
system.cpu.icache.overall_mshr_hits 539 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 223685500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 223686000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.001947 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 23603 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 21558 # number of replacements
system.cpu.icache.sampled_refs 23588 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1798.726213 # Cycle average of tags in use
-system.cpu.icache.total_refs 12098546 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1798.726219 # Cycle average of tags in use
+system.cpu.icache.total_refs 12098549 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 986504 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 987173 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 13347127 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.903568 # Inst execution rate
-system.cpu.iew.EXEC:refs 50902903 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 21266898 # Number of stores executed
+system.cpu.iew.EXEC:nop 107693 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.902867 # Inst execution rate
+system.cpu.iew.EXEC:refs 50902907 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 21266903 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 83917531 # num instructions consuming a value
-system.cpu.iew.WB:count 104978436 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.516830 # average fanout of values written-back
+system.cpu.iew.WB:consumers 83917558 # num instructions consuming a value
+system.cpu.iew.WB:count 104895459 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.516831 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 43371139 # num instructions producing a value
-system.cpu.iew.WB:rate 0.885745 # insts written-back per cycle
-system.cpu.iew.WB:sent 106195350 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2628455 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 987035 # Number of cycles IEW is blocking
+system.cpu.iew.WB:producers 43371156 # num instructions producing a value
+system.cpu.iew.WB:rate 0.885045 # insts written-back per cycle
+system.cpu.iew.WB:sent 106112224 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2628306 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 987032 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 32508348 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1016199 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 2305298 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 23389031 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 117101137 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 29636005 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2065669 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 107090838 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 2107 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispatchedInsts 117101013 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 29636004 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2065127 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 107007708 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 2101 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 908 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 3514572 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 39558 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 3514410 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 39551 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 247077 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.squashedLoads 5193052 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 2833293 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 39532 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1768227 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1768078 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 860228 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 255816186 # number of integer regfile reads
-system.cpu.int_regfile_writes 78479487 # number of integer regfile writes
-system.cpu.ipc 0.833936 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.833936 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 255733219 # number of integer regfile reads
+system.cpu.int_regfile_writes 78479500 # number of integer regfile writes
+system.cpu.ipc 0.833889 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.833889 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 57364104 52.55% 52.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 80354 0.07% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 124 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 52.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 30140236 27.61% 80.24% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 21571681 19.76% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 57280423 52.52% 52.52% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 80354 0.07% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 124 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 1 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 7 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 52.59% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 30140240 27.63% 80.22% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 21571686 19.78% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 109156507 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 1323138 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.012121 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 109072835 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 1323141 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012131 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 1303 0.10% 0.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 1305 0.10% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.10% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.10% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 1094336 82.71% 82.81% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 1094337 82.71% 82.81% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 227499 17.19% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 117533456 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.928727 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.126434 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 117532765 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.928021 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.124128 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 53481972 45.50% 45.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 35549975 30.25% 75.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 18295748 15.57% 91.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 5807729 4.94% 96.26% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 2883694 2.45% 98.71% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 1109227 0.94% 99.66% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 329629 0.28% 99.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 70692 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 53487199 45.51% 45.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 35551116 30.25% 75.76% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 18289887 15.56% 91.32% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 5815919 4.95% 96.27% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2890149 2.46% 98.73% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1119018 0.95% 99.68% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 322627 0.27% 99.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 52060 0.04% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 4790 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 117533456 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.920997 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 117532765 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.920291 # Inst issue rate
system.cpu.iq.fp_alu_accesses 187 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 370 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 59 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 568 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 110479458 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 337237563 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 104978377 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 134232957 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 116084938 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 109156507 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 110395789 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 337069521 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 104895400 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 134025371 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 115977121 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 109072835 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1016199 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 17094247 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 68325 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 16994478 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 68315 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 348408 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 30276342 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 30228049 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.958506 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 102310 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 80290 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34268.509897 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34268.464842 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31112.930905 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 46997 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1140901500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 1140900000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.414659 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 33293 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 78 # number of ReadReq MSHR hits
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 187029 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34356.533410 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34356.522348 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 51426 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 4658849000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 4658847500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.725037 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 135603 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 78 # number of demand (read+write) MSHR hits
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.075665 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.490596 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2479.385419 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16075.863311 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2479.385320 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 16075.863563 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 187029 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34356.533410 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34356.522348 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.624055 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 51426 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 4658849000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 4658847500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.725037 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 135603 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 78 # number of overall MSHR hits
system.cpu.l2cache.replacements 115260 # number of replacements
system.cpu.l2cache.sampled_refs 134133 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18555.248730 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 18555.248883 # Cycle average of tags in use
system.cpu.l2cache.total_refs 70079 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 88459 # number of writebacks
system.cpu.memDep0.conflictingStores 10924699 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 32508348 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 23389031 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 153116651 # number of misc regfile reads
+system.cpu.misc_regfile_reads 153116664 # number of misc regfile reads
system.cpu.misc_regfile_writes 1948149 # number of misc regfile writes
-system.cpu.numCycles 118519960 # number of cpu cycles simulated
+system.cpu.numCycles 118519938 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 1866194 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 1866182 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 74745628 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 1883 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 30389505 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 833530 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IdleCycles 30389111 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 833533 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 333412635 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 124050705 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 93358658 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 68672790 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 3514572 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1591233 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 18613027 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 333388241 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 124050583 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 93358664 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 68672664 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 3514410 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1591236 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 18613033 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 83717 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 333328918 # Number of integer rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 333304524 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 11499162 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 818368 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3724500 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 3724501 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 819368 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 229794357 # The number of ROB reads
-system.cpu.rob.rob_writes 237655572 # The number of ROB writes
-system.cpu.timesIdled 60726 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 229793704 # The number of ROB reads
+system.cpu.rob.rob_writes 237655161 # The number of ROB writes
+system.cpu.timesIdled 60746 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:56:25
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/o3-timing
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:34:24
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 736332221500 because target called exit()
+Exiting @ tick 741617860500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 152870 # Simulator instruction rate (inst/s)
-host_mem_usage 238404 # Number of bytes of host memory used
-host_seconds 11182.08 # Real time elapsed on the host
-host_tick_rate 65849295 # Simulator tick rate (ticks/s)
+host_inst_rate 95203 # Simulator instruction rate (inst/s)
+host_mem_usage 256912 # Number of bytes of host memory used
+host_seconds 17955.42 # Real time elapsed on the host
+host_tick_rate 41303275 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1709408682 # Number of instructions simulated
-sim_seconds 0.736332 # Number of seconds simulated
-sim_ticks 736332221500 # Number of ticks simulated
+sim_insts 1709408664 # Number of instructions simulated
+sim_seconds 0.741618 # Number of seconds simulated
+sim_ticks 741617860500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 251161589 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 289953961 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 251301725 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 290055524 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 20139757 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 310539803 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 310539803 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 20139557 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 310557354 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 310557354 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 203576342 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 42336019 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 41094487 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1325593863 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.289542 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.917523 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1326705477 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.288461 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.905257 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 632760901 47.73% 47.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 317626873 23.96% 71.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 153247647 11.56% 83.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 83932703 6.33% 89.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 35877325 2.71% 92.29% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 27102905 2.04% 94.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 13190001 1.00% 95.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 19519489 1.47% 96.81% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 42336019 3.19% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 628813054 47.40% 47.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 321601613 24.24% 71.64% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 154175798 11.62% 83.26% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 85373201 6.43% 89.69% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 35866236 2.70% 92.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 27097363 2.04% 94.44% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 13157860 0.99% 95.43% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 19525865 1.47% 96.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 41094487 3.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1325593863 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1326705477 # Number of insts commited each cycle
system.cpu.commit.COM:count 1709408682 # Number of instructions committed
system.cpu.commit.COM:fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 660773875 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 33291323 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 30574219 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1709408682 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 333 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 724671522 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 1709408682 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1709408682 # Number of Instructions Simulated
-system.cpu.cpi 0.861505 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.861505 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 535355954 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 14975.678248 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11475.231071 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 527355564 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 119811266500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.014944 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 8000390 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 345154 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 87845602000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.014299 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7655236 # number of ReadReq MSHR misses
+system.cpu.commit.commitSquashedInsts 722443769 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 1709408664 # Number of Instructions Simulated
+system.cpu.committedInsts_total 1709408664 # Number of Instructions Simulated
+system.cpu.cpi 0.867689 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.867689 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 536310912 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 14847.958953 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11472.623282 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 528392695 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 117569361000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.014764 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 7918217 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 262533 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 87830778500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.014275 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7655684 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 23783.327584 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20862.502653 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 168018197 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 108640123688 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.026467 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 4567911 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 2675787 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 39474441969 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_avg_miss_latency 23573.653690 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20855.792552 # average WriteReq mshr miss latency
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+system.cpu.dcache.WriteReq_miss_rate 0.024515 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 4230879 # number of WriteReq misses
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+system.cpu.dcache.WriteReq_mshr_miss_latency 39461891617 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.010963 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1892124 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3127.917167 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 1892131 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_targets 19937.500000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 72.834141 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 25171 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 72.974594 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 25122 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 78732803 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 78569847 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 159500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 707942062 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18176.791771 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 695373761 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 228451390188 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.017753 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 12568301 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 3020941 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 127320043969 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.013486 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9547360 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 708897020 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 17886.650772 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 13332.125739 # average overall mshr miss latency
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+system.cpu.dcache.demand_misses 12149096 # number of demand (read+write) misses
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+system.cpu.dcache.demand_mshr_misses 9547815 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997284 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4084.873750 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 707942062 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18176.791771 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13335.628275 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.997303 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4084.953054 # Average occupied blocks per context
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+system.cpu.dcache.overall_avg_mshr_miss_latency 13332.125739 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 695373761 # number of overall hits
-system.cpu.dcache.overall_miss_latency 228451390188 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.017753 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 12568301 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 3020941 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 127320043969 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.013486 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9547360 # number of overall MSHR misses
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+system.cpu.dcache.overall_misses 12149096 # number of overall misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9543264 # number of replacements
-system.cpu.dcache.sampled_refs 9547360 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9543719 # number of replacements
+system.cpu.dcache.sampled_refs 9547815 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4084.873750 # Cycle average of tags in use
-system.cpu.dcache.total_refs 695373761 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7250730000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 3122652 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 107521017 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 2640561192 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 660508331 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 547645494 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 111598676 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 9919021 # Number of cycles decode is unblocking
+system.cpu.dcache.tagsinuse 4084.953054 # Cycle average of tags in use
+system.cpu.dcache.total_refs 696747924 # Total number of references to valid blocks.
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+system.cpu.dcache.writebacks 3122334 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 116148050 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 2638178862 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 655478683 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 543495866 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 108887211 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 11582877 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 310539803 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 305341372 # Number of cache lines fetched
-system.cpu.fetch.Cycles 575112901 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 5844114 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2356609774 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 3056047 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 35765564 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.210869 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 305341372 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 251161589 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.600235 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1437192539 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.882507 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.825084 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 310557354 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 305363576 # Number of cache lines fetched
+system.cpu.fetch.Cycles 575148381 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 5854767 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2356063229 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 488598 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 33050006 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.209378 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 305363576 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 251301725 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.588462 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1435592687 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.884283 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.825499 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 863142869 60.06% 60.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 76123612 5.30% 65.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 84397778 5.87% 71.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 62407182 4.34% 75.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 54486198 3.79% 79.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 66150908 4.60% 83.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 49722936 3.46% 87.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 19741369 1.37% 88.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 161019687 11.20% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 861509887 60.01% 60.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 76125416 5.30% 65.31% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 84428440 5.88% 71.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 62504000 4.35% 75.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 54555625 3.80% 79.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 66078288 4.60% 83.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 49716683 3.46% 87.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19740436 1.38% 88.79% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 160933912 11.21% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1437192539 # Number of instructions fetched each cycle (Total)
-system.cpu.fp_regfile_reads 66 # number of floating regfile reads
+system.cpu.fetch.rateDist::total 1435592687 # Number of instructions fetched each cycle (Total)
+system.cpu.fp_regfile_reads 64 # number of floating regfile reads
system.cpu.fp_regfile_writes 62 # number of floating regfile writes
-system.cpu.icache.ReadReq_accesses 305341372 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34138.917794 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34194.369973 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 305340411 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 32807500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_accesses 305363576 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34138.773389 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34223.489933 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 305362614 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 32841500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 961 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 215 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 25509000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 962 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 217 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 25496500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000002 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 746 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 745 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 409303.500000 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 409882.703356 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 305341372 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34138.917794 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
-system.cpu.icache.demand_hits 305340411 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 32807500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 305363576 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34138.773389 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34223.489933 # average overall mshr miss latency
+system.cpu.icache.demand_hits 305362614 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 32841500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000003 # miss rate for demand accesses
-system.cpu.icache.demand_misses 961 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 215 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 25509000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 962 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 217 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 25496500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000002 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 746 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 745 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.297244 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 608.756375 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 305341372 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34138.917794 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34194.369973 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.297532 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 609.346021 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 305363576 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34138.773389 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34223.489933 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 305340411 # number of overall hits
-system.cpu.icache.overall_miss_latency 32807500 # number of overall miss cycles
+system.cpu.icache.overall_hits 305362614 # number of overall hits
+system.cpu.icache.overall_miss_latency 32841500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000003 # miss rate for overall accesses
-system.cpu.icache.overall_misses 961 # number of overall misses
-system.cpu.icache.overall_mshr_hits 215 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 25509000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 962 # number of overall misses
+system.cpu.icache.overall_mshr_hits 217 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 25496500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000002 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 746 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 745 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 10 # number of replacements
-system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 745 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 608.756375 # Cycle average of tags in use
-system.cpu.icache.total_refs 305340411 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 609.346021 # Cycle average of tags in use
+system.cpu.icache.total_refs 305362614 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 35471905 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 234624640 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.389966 # Inst execution rate
-system.cpu.iew.EXEC:refs 783869507 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 215578815 # Number of stores executed
+system.cpu.idleCycles 47643035 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 234627924 # Number of branches executed
+system.cpu.iew.EXEC:nop 4671909 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.375387 # Inst execution rate
+system.cpu.iew.EXEC:refs 783939674 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 215608294 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 2289056926 # num instructions consuming a value
-system.cpu.iew.WB:count 2009251521 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.549566 # average fanout of values written-back
+system.cpu.iew.WB:consumers 2287060354 # num instructions consuming a value
+system.cpu.iew.WB:count 2005204740 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.549071 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1257988693 # num instructions producing a value
-system.cpu.iew.WB:rate 1.364365 # insts written-back per cycle
-system.cpu.iew.WB:sent 2020755883 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 34959273 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 18898435 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 660629203 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 422 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 10495423 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 320206682 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2433961539 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 568290692 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 53852412 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2046953136 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 1105294 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 1255759101 # num instructions producing a value
+system.cpu.iew.WB:rate 1.351912 # insts written-back per cycle
+system.cpu.iew.WB:sent 2013818862 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 32077179 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 18912819 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 660681336 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 423 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 10498008 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 320240164 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2431733440 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 568331380 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 53845340 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2040022874 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 1107254 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 81032 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 111598676 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 1881770 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 78756 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 108887211 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 1884872 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 185278 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 29166049 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 474578 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 185254 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 28251686 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 475798 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 2909115 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 2910400 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 174702372 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 145359637 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 2909115 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 16680292 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 18278981 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 5217275964 # number of integer regfile reads
-system.cpu.int_regfile_writes 1582136898 # number of integer regfile writes
-system.cpu.ipc 1.160759 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.160759 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.squashedLoads 174754505 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 145393119 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 2910400 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 13800164 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 18277015 # Number of branches that were predicted taken incorrectly
+system.cpu.int_regfile_reads 5213407852 # number of integer regfile reads
+system.cpu.int_regfile_writes 1582208082 # number of integer regfile writes
+system.cpu.ipc 1.152486 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.152486 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 1282325001 61.04% 61.04% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 1250884 0.06% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 20 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 3 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 17 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 61.10% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 577865457 27.51% 88.61% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 239364164 11.39% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1275319810 60.91% 60.91% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 1250756 0.06% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 20 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 3 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 17 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 60.97% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 577902067 27.60% 88.57% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 239395539 11.43% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 2100805548 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 35252464 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.016780 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 2093868214 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 35323579 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.016870 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 38199 0.11% 0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 38144 0.11% 0.11% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 1 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMult 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatMultAcc 0 0.00% 0.11% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::SimdFloatSqrt 0 0.00% 0.11% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 25515421 72.38% 72.49% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 9698844 27.51% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 25553394 72.34% 72.45% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 9732040 27.55% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 1437192539 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.461743 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.631414 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 1435592687 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.458539 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.617960 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 547476469 38.09% 38.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 329329940 22.91% 61.01% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 229433093 15.96% 76.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 157481559 10.96% 87.93% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 82220449 5.72% 93.65% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 49053587 3.41% 97.06% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 31255179 2.17% 99.24% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 9054164 0.63% 99.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 1888099 0.13% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 542472821 37.79% 37.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 332842678 23.19% 60.97% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 233352202 16.25% 77.23% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 155519573 10.83% 88.06% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 81101345 5.65% 93.71% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 48382072 3.37% 97.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 32454212 2.26% 99.34% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 9020871 0.63% 99.97% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 446913 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 1437192539 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.426534 # Inst issue rate
-system.cpu.iq.fp_alu_accesses 101 # Number of floating point alu accesses
-system.cpu.iq.fp_inst_queue_reads 196 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_wakeup_accesses 78 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 2136057911 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 5702380947 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 2009251443 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 3154359191 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 2433961117 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2100805548 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 422 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 717692858 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 28325044 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 89 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 1287267033 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 1435592687 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.411689 # Inst issue rate
+system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses
+system.cpu.iq.fp_inst_queue_reads 193 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
+system.cpu.iq.int_alu_accesses 2129191694 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 5686973961 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 2005204664 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 3140550876 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 2427061108 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2093868214 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 423 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 710783267 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 28321460 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 90 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 1287397497 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 1892128 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34475.157161 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31331.098502 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_hits 979531 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 31461925000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 0.482313 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 912597 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 28592666500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482313 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 912597 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7655978 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34344.776594 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31123.973478 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5633361 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 69466329000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.264188 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 2022617 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_accesses 1892135 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34468.560268 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31327.409096 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 979500 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 31457214500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.482331 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 912635 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 28590490000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.482331 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 912635 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 7656425 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34342.856557 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31123.713689 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 5633283 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 69480475500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.264241 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 2023142 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.cpu.l2cache.ReadReq_mshr_miss_latency 62951535500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264186 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 2022606 # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 3122652 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 3122652 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3948.352875 # average number of cycles each access was blocked
+system.cpu.l2cache.ReadReq_mshr_miss_latency 62967350000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.264240 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 2023131 # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 3122334 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 3122334 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 3959.932754 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.651904 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 3582 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 2.651251 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 3569 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 14143000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 14133000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9548106 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34385.313643 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 6612892 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 100928254000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.307413 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 2935214 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9548560 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34381.933641 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31187.036024 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 6612783 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 100937690000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.307458 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 2935777 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 91544202000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.307412 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 2935203 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 91557840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.307456 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 2935766 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.494634 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.321250 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 16208.167153 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 10526.735069 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 9548106 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34385.313643 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31188.371639 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.492711 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.322099 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 16145.140731 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10554.551428 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 9548560 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34381.933641 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31187.036024 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 6612892 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 100928254000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.307413 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 2935214 # number of overall misses
+system.cpu.l2cache.overall_hits 6612783 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 100937690000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.307458 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 2935777 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 91544202000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.307412 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 2935203 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 91557840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.307456 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 2935766 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2922772 # number of replacements
-system.cpu.l2cache.sampled_refs 2950094 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2923336 # number of replacements
+system.cpu.l2cache.sampled_refs 2950658 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 26734.902222 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7823366 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 156475359000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1217059 # number of writebacks
-system.cpu.memDep0.conflictingLoads 102861524 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 93795307 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 660629203 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 320206682 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 3121183601 # number of misc regfile reads
+system.cpu.l2cache.tagsinuse 26699.692159 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7822936 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 156475358000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1217176 # number of writebacks
+system.cpu.memDep0.conflictingLoads 104356221 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 93983481 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 660681336 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 320240164 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 3120702507 # number of misc regfile reads
system.cpu.misc_regfile_writes 895 # number of misc regfile writes
-system.cpu.numCycles 1472664444 # number of cpu cycles simulated
+system.cpu.numCycles 1483235722 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.rename.RENAME:BlockCycles 52825853 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:BlockCycles 54941029 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1347252520 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 13396688 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 691140909 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 38063722 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 9972 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 7136669468 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2563712800 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1945900239 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 526018927 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 111598676 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 55598501 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 598647716 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 1008 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 7136668460 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 9673 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 448 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 110186399 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 445 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 3717337450 # The number of ROB reads
-system.cpu.rob.rob_writes 4979785274 # The number of ROB writes
-system.cpu.timesIdled 1109854 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 13387428 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 685531408 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 44918840 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 10136 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 7132306649 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2561579932 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1946061364 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 524157862 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 108887211 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 62065425 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 598808841 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 996 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 7132305653 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 9752 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 450 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 114534338 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 447 # count of temporary serializing insts renamed
+system.cpu.rob.rob_reads 3717462842 # The number of ROB reads
+system.cpu.rob.rob_writes 4972618229 # The number of ROB writes
+system.cpu.timesIdled 1594989 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 02:00:24
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/o3-timing/smred.sv2
+M5 compiled Feb 21 2011 14:34:16
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 15:12:03
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sav
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 149819218000 because target called exit()
+122 123 124 Exiting @ tick 149819214000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 61621 # Simulator instruction rate (inst/s)
-host_mem_usage 241964 # Number of bytes of host memory used
-host_seconds 2999.07 # Real time elapsed on the host
-host_tick_rate 49955205 # Simulator tick rate (ticks/s)
+host_inst_rate 52926 # Simulator instruction rate (inst/s)
+host_mem_usage 260544 # Number of bytes of host memory used
+host_seconds 3491.51 # Real time elapsed on the host
+host_tick_rate 42909528 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 184806751 # Number of instructions simulated
+sim_insts 184792363 # Number of instructions simulated
sim_seconds 0.149819 # Number of seconds simulated
-sim_ticks 149819218000 # Number of ticks simulated
+sim_ticks 149819214000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 51777441 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 55728819 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 55728820 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 12604932 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 57019634 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 57019634 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 57019635 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 57019635 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 39499925 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 586569 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 285162307 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 285162046 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::mean 0.648076 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::stdev 0.934649 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 151202157 53.02% 53.02% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 102481067 35.94% 88.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 22788720 7.99% 96.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 3864440 1.36% 98.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2118453 0.74% 99.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 1126211 0.39% 99.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 151201890 53.02% 53.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 102481075 35.94% 88.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 22788718 7.99% 96.95% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3864443 1.36% 98.31% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2118451 0.74% 99.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1126210 0.39% 99.45% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 605325 0.21% 99.66% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 389365 0.14% 99.79% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 586569 0.21% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 285162307 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 285162046 # Number of insts commited each cycle
system.cpu.commit.COM:count 184806751 # Number of instructions committed
system.cpu.commit.COM:fp_insts 1730659 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 42081439 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 12955642 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 12955566 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 184806751 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1569953 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 36913939 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 184806751 # Number of Instructions Simulated
-system.cpu.committedInsts_total 184806751 # Number of Instructions Simulated
-system.cpu.cpi 1.621361 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.621361 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 32436972 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 31572.372561 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32361.760660 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 32435383 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 50168500 # number of ReadReq miss cycles
+system.cpu.commit.commitSquashedInsts 36913868 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 184792363 # Number of Instructions Simulated
+system.cpu.committedInsts_total 184792363 # Number of Instructions Simulated
+system.cpu.cpi 1.621487 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.621487 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 32436973 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 31572.057898 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32361.072902 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 32435384 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 50168000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000049 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1589 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 862 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 23527000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 23526500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 727 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 12273971 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 25387.973098 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35046.203111 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 25388.039035 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35046.660567 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_hits 12266388 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 192517000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency 192517500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_rate 0.000618 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_misses 7583 # number of WriteReq misses
system.cpu.dcache.WriteReq_mshr_hits 6490 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 38305500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency 38306000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 1093 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 24561.412637 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 24561.413187 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 9000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 44710943 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses 44710944 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 26459.387266 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 44701771 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits 44701772 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 242685500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000205 # miss rate for demand accesses
system.cpu.dcache.demand_misses 9172 # number of demand (read+write) misses
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.337576 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1382.712740 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 44710943 # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0 1382.712770 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 44710944 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 26459.387266 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 33973.901099 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 44701771 # number of overall hits
+system.cpu.dcache.overall_hits 44701772 # number of overall hits
system.cpu.dcache.overall_miss_latency 242685500 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000205 # miss rate for overall accesses
system.cpu.dcache.overall_misses 9172 # number of overall misses
system.cpu.dcache.replacements 46 # number of replacements
system.cpu.dcache.sampled_refs 1820 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1382.712740 # Cycle average of tags in use
-system.cpu.dcache.total_refs 44701771 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1382.712770 # Cycle average of tags in use
+system.cpu.dcache.total_refs 44701772 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 17 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 21645695 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 264148403 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 61114586 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 200863194 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 14404012 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 1538832 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles 21645694 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 264148336 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 61114397 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 200863123 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 14403927 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 1538831 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 57019634 # Number of branches that fetch encountered
+system.cpu.fetch.Branches 57019635 # Number of branches that fetch encountered
system.cpu.fetch.CacheLines 24416320 # Number of cache lines fetched
system.cpu.fetch.Cycles 213842486 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.IcacheSquashes 1112165 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 254182972 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 47170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 13195953 # Number of cycles fetch has spent squashing
+system.cpu.fetch.MiscStallCycles 47096 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 13195878 # Number of cycles fetch has spent squashing
system.cpu.fetch.branchRate 0.190295 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 24416320 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 51777441 # Number of branches that fetch has predicted taken
system.cpu.fetch.rate 0.848299 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 299566319 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.927729 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 299565972 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.927730 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.045167 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 86216737 28.78% 28.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 186583672 62.28% 91.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 86216390 28.78% 28.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 186583671 62.28% 91.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 11093729 3.70% 94.77% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 7887786 2.63% 97.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 1768857 0.59% 97.99% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 2263080 0.76% 98.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1007502 0.34% 99.08% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1007503 0.34% 99.08% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 913678 0.31% 99.39% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 1831278 0.61% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 299566319 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 299565972 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 2799107 # number of floating regfile reads
system.cpu.fp_regfile_writes 2446180 # number of floating regfile writes
system.cpu.icache.ReadReq_accesses 24416320 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 25129.997165 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21979.962430 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 25130.564219 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 21980.432060 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 24412793 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 88633500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 88635500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000144 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 3527 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 333 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 70204000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000131 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 3194 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 24416320 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 25129.997165 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21979.962430 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 25130.564219 # average overall miss latency
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system.cpu.icache.demand_hits 24412793 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 88633500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000144 # miss rate for demand accesses
system.cpu.icache.demand_misses 3527 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 333 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 70204000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 70205500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000131 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 3194 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.617996 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1265.656539 # Average occupied blocks per context
+system.cpu.icache.occ_blocks::0 1265.656561 # Average occupied blocks per context
system.cpu.icache.overall_accesses 24416320 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 25129.997165 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21979.962430 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 24412793 # number of overall hits
-system.cpu.icache.overall_miss_latency 88633500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000144 # miss rate for overall accesses
system.cpu.icache.overall_misses 3527 # number of overall misses
system.cpu.icache.overall_mshr_hits 333 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 70204000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000131 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 3194 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 1539 # number of replacements
system.cpu.icache.sampled_refs 3194 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1265.656539 # Cycle average of tags in use
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system.cpu.icache.total_refs 24412793 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 72118 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 72457 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 40333139 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.675496 # Inst execution rate
-system.cpu.iew.EXEC:refs 46706722 # number of memory reference insts executed
+system.cpu.iew.EXEC:nop 106308 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.675299 # Inst execution rate
+system.cpu.iew.EXEC:refs 46706723 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 12922741 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 166977315 # num instructions consuming a value
-system.cpu.iew.WB:count 199490949 # cumulative count of insts written-back
+system.cpu.iew.WB:consumers 166977314 # num instructions consuming a value
+system.cpu.iew.WB:count 199432136 # cumulative count of insts written-back
system.cpu.iew.WB:fanout 0.694920 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 116035924 # num instructions producing a value
-system.cpu.iew.WB:rate 0.665772 # insts written-back per cycle
-system.cpu.iew.WB:sent 200460633 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 13076729 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 116035928 # num instructions producing a value
+system.cpu.iew.WB:rate 0.665576 # insts written-back per cycle
+system.cpu.iew.WB:sent 200401741 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 13076652 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 1256 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 37075609 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 1668755 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 11833620 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 14988552 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 221729697 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 33783981 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10734422 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 202404420 # Number of executed instructions
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+system.cpu.iew.iewDispStoreInsts 14988549 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 221729626 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewExecutedInsts 202345530 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 14404012 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 14403927 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 103 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.memOrderViolation 295230 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 7520997 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 2461724 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedStores 2461721 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 295230 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1407561 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 1407484 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 11669168 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 457836856 # number of integer regfile reads
-system.cpu.int_regfile_writes 195349958 # number of integer regfile writes
-system.cpu.ipc 0.616766 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.616766 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 457778046 # number of integer regfile reads
+system.cpu.int_regfile_writes 195349960 # number of integer regfile writes
+system.cpu.ipc 0.616718 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.616718 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 33154 0.02% 77.03% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 157340 0.07% 77.11% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 74720 0.04% 77.27% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 439795 0.21% 77.47% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 197622 0.09% 77.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 71713 0.03% 77.61% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::MemRead 34601051 16.23% 93.84% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 318 0.00% 77.60% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 34601052 16.24% 93.84% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 13124839 6.16% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 213138842 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 1172618 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.005502 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 213075488 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 1172568 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005503 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 53 0.00% 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 3 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 383292 32.69% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 299566319 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711491 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.811323 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 299565972 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.711281 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 0.810682 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 130437800 43.54% 43.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 140705247 46.97% 90.51% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 18781279 6.27% 96.78% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 5495734 1.83% 98.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 2758024 0.92% 99.54% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 1051071 0.35% 99.89% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 286459 0.10% 99.98% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 28010 0.01% 99.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 130442943 43.54% 43.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 140707808 46.97% 90.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 18780101 6.27% 96.78% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 5513171 1.84% 98.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2752255 0.92% 99.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1032616 0.34% 99.89% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 286376 0.10% 99.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 28007 0.01% 99.99% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 22695 0.01% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 299566319 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.711320 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 299565972 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.711109 # Inst issue rate
system.cpu.iq.fp_alu_accesses 1965612 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 3923910 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 1824312 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 2255873 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 212345848 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 723342864 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 197666637 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 240391153 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 220060942 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 213138842 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 212282444 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 723212864 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 197607824 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 240197118 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 219954563 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 213075488 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 1668755 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 20677309 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 250153 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 20589653 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 247258 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 98802 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 37784077 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 37700924 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1093 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34262.672811 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.133641 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31130.875576 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_miss_latency 37175000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 37175500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 0.992681 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1085 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 33777000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992681 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1085 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 3921 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34264.029618 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34264.419330 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.500393 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1355 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 87921500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 87922500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.654425 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 2566 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_hits 20 # number of ReadReq MSHR hits
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 5014 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34263.626404 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34264.037250 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1363 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 125096500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 125098000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.728161 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 3651 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 20 # number of demand (read+write) MSHR hits
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.occ_%::0 0.055506 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000152 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1818.805023 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 1818.805056 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 4.996217 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 5014 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34263.626404 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34264.037250 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31096.254475 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1363 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 125096500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 125098000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.728161 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 3651 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 20 # number of overall MSHR hits
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 2555 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 1823.801240 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 1823.801274 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1355 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 3889323 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2640936 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 37075609 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14988552 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 328971278 # number of misc regfile reads
+system.cpu.memDep0.insertedStores 14988549 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 328971277 # number of misc regfile reads
system.cpu.misc_regfile_writes 4891827 # number of misc regfile writes
-system.cpu.numCycles 299638437 # number of cpu cycles simulated
+system.cpu.numCycles 299638429 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 3074 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 178683528 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2322 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 73277760 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 73277569 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 19202 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 601080290 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 249997565 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 249829292 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 190277990 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 14404012 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1750038 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 71145762 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:RenameLookups 601039980 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 249997488 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 249829289 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 190277920 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 14403927 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1750037 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 71145759 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:fp_rename_lookups 14827185 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 586253105 # Number of integer rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 586212795 # Number of integer rename lookups
system.cpu.rename.RENAME:serializeStallCycles 19853445 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 2086015 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 2928694 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1863087 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 506291228 # The number of ROB reads
-system.cpu.rob.rob_writes 457856948 # The number of ROB writes
-system.cpu.timesIdled 1363 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 506290895 # The number of ROB reads
+system.cpu.rob.rob_writes 457856720 # The number of ROB writes
+system.cpu.timesIdled 1374 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
+executable=/chips/pd/randd/dist/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
All Rights Reserved
-M5 compiled Feb 7 2011 01:56:16
-M5 revision 4b4b02c5553c 7929 default qtip reupdatestats.patch tip
-M5 started Feb 7 2011 01:58:16
-M5 executing on burrito
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/o3-timing
+M5 compiled Feb 23 2011 14:37:21
+M5 revision bc7f8168ee84 7973 default ext/update_regressions.patch qtip tip
+M5 started Feb 23 2011 14:37:24
+M5 executing on u200439-lin.austin.arm.com
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 10317500 because target called exit()
+Exiting @ tick 10283500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 29952 # Simulator instruction rate (inst/s)
-host_mem_usage 234448 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-host_tick_rate 54904580 # Simulator tick rate (ticks/s)
+host_inst_rate 6235 # Simulator instruction rate (inst/s)
+host_mem_usage 252896 # Number of bytes of host memory used
+host_seconds 0.90 # Real time elapsed on the host
+host_tick_rate 11404126 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5620 # Number of instructions simulated
sim_seconds 0.000010 # Number of seconds simulated
-sim_ticks 10317500 # Number of ticks simulated
+sim_ticks 10283500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 790 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 2144 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 2145 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 348 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 2189 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 2189 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 2190 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2190 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 840 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 10656 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.527402 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.275771 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 10507 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.534882 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.283154 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 8217 77.11% 77.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 1132 10.62% 87.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 525 4.93% 92.66% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 313 2.94% 95.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 174 1.63% 97.23% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 143 1.34% 98.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 45 0.42% 99.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 38 0.36% 99.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 69 0.65% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 8067 76.78% 76.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1134 10.79% 87.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 524 4.99% 92.56% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 313 2.98% 95.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 174 1.66% 97.19% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 143 1.36% 98.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 45 0.43% 98.98% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 38 0.36% 99.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 69 0.66% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 10656 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 10507 # Number of insts commited each cycle
system.cpu.commit.COM:count 5620 # Number of instructions committed
system.cpu.commit.COM:fp_insts 16 # Number of committed floating point instructions.
system.cpu.commit.COM:function_calls 0 # Number of function calls committed.
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 2145 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 548 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 526 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5620 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 1 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 6019 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 6008 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5620 # Number of Instructions Simulated
system.cpu.committedInsts_total 5620 # Number of Instructions Simulated
-system.cpu.cpi 3.671886 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.671886 # CPI: Total CPI of All Threads
+system.cpu.cpi 3.659786 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.659786 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1812 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 32038.043478 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29730.088496 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 31853.260870 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 29433.628319 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1628 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5895000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 5861000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.101545 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 184 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 71 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3359500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3326000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.062362 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 113 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 924 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35706.185567 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency 35561.461794 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36109.756098 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 633 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 10390500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.314935 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 291 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 250 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_hits 623 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 10704000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.325758 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 301 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 260 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_miss_latency 1480500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate 0.044372 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_misses 41 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 14.681818 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 14.616883 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2736 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 34285.263158 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31428.571429 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2261 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 16285500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.173611 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 475 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 321 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_avg_miss_latency 34154.639175 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31211.038961 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2251 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16565000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.177266 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 485 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 4806500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.056287 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_misses 154 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.022828 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 93.502986 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.022805 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 93.407309 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2736 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 34285.263158 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31428.571429 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 34154.639175 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31211.038961 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2261 # number of overall hits
-system.cpu.dcache.overall_miss_latency 16285500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.173611 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 475 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 321 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4840000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 2251 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16565000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.177266 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 485 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 331 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 4806500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.056287 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 154 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 93.502986 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2261 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 93.407309 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2251 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 805 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 14956 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 7320 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2481 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1162 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:BlockedCycles 735 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 14966 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 7256 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2466 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1138 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 49 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1675 # Number of cache lines fetched
-system.cpu.fetch.Cycles 2612 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 323 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 12619 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 583 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.106077 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1675 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Branches 2190 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1676 # Number of cache lines fetched
+system.cpu.fetch.Cycles 2616 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 324 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 12629 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 562 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.106476 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1676 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 790 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.611504 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 11818 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.321713 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.741660 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rate 0.614012 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 11644 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.344040 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.759565 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9206 77.90% 77.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 206 1.74% 79.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 151 1.28% 80.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 211 1.79% 82.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 193 1.63% 84.34% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 242 2.05% 86.39% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 136 1.15% 87.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 103 0.87% 88.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1370 11.59% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 9028 77.53% 77.53% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 206 1.77% 79.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 151 1.30% 80.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 211 1.81% 82.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 193 1.66% 84.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 242 2.08% 86.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 137 1.18% 87.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 103 0.88% 88.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 1373 11.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11818 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 11644 # Number of instructions fetched each cycle (Total)
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.icache.ReadReq_accesses 1675 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 34635.549872 # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses 1676 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 34634.271100 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 33596.573209 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1284 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 13542500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.233433 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_hits 1285 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13542000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.233294 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 391 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 10784500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.191642 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.191527 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 321 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.003115 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1675 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 34635.549872 # average overall miss latency
+system.cpu.icache.demand_accesses 1676 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 34634.271100 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 33596.573209 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1284 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 13542500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.233433 # miss rate for demand accesses
+system.cpu.icache.demand_hits 1285 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 13542000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.233294 # miss rate for demand accesses
system.cpu.icache.demand_misses 391 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10784500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.191642 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.191527 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 321 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.079518 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 162.851965 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 1675 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 34635.549872 # average overall miss latency
+system.cpu.icache.occ_%::0 0.079640 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 163.103725 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1676 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 34634.271100 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 33596.573209 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1284 # number of overall hits
-system.cpu.icache.overall_miss_latency 13542500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.233433 # miss rate for overall accesses
+system.cpu.icache.overall_hits 1285 # number of overall hits
+system.cpu.icache.overall_miss_latency 13542000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.233294 # miss rate for overall accesses
system.cpu.icache.overall_misses 391 # number of overall misses
system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10784500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.191642 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.191527 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 321 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 5 # number of replacements
system.cpu.icache.sampled_refs 321 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 162.851965 # Cycle average of tags in use
-system.cpu.icache.total_refs 1284 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 163.103725 # Cycle average of tags in use
+system.cpu.icache.total_refs 1285 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8818 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 8924 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1306 # Number of branches executed
-system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.417184 # Inst execution rate
+system.cpu.iew.EXEC:nop 20 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.417493 # Inst execution rate
system.cpu.iew.EXEC:refs 3129 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1169 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 7928 # num instructions consuming a value
-system.cpu.iew.WB:count 7988 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.467709 # average fanout of values written-back
+system.cpu.iew.WB:consumers 7925 # num instructions consuming a value
+system.cpu.iew.WB:count 7989 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.467886 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:producers 3708 # num instructions producing a value
-system.cpu.iew.WB:rate 0.387091 # insts written-back per cycle
-system.cpu.iew.WB:sent 8290 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 642 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:rate 0.388419 # insts written-back per cycle
+system.cpu.iew.WB:sent 8268 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 620 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 230 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 2545 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 2 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 596 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1646 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11906 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispStoreInsts 1654 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11895 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 1960 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 475 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8609 # Number of executed instructions
+system.cpu.iew.iewExecSquashedInsts 474 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8587 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1162 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1138 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 28 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.memOrderViolation 34 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 2 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread.0.squashedLoads 1338 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 708 # Number of stores squashed
+system.cpu.iew.lsq.thread.0.squashedStores 716 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 34 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 609 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 587 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 33 # Number of branches that were predicted taken incorrectly
-system.cpu.int_regfile_reads 19236 # number of integer regfile reads
-system.cpu.int_regfile_writes 5710 # number of integer regfile writes
-system.cpu.ipc 0.272340 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.272340 # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads 19241 # number of integer regfile reads
+system.cpu.int_regfile_writes 5711 # number of integer regfile writes
+system.cpu.ipc 0.273240 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.273240 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 5717 62.93% 62.93% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.99% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.03% 63.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 63.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 63.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 63.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 2133 23.48% 86.50% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1226 13.50% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 5694 62.84% 62.84% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAdd 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAddAcc 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdAlu 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCmp 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdCvt 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMisc 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMult 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdMultAcc 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShift 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdShiftAcc 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdSqrt 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAdd 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatAlu 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCmp 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatCvt 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatDiv 0 0.00% 62.90% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMisc 3 0.03% 62.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMult 0 0.00% 62.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatMultAcc 0 0.00% 62.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::SimdFloatSqrt 0 0.00% 62.93% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 2133 23.54% 86.47% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1226 13.53% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 9084 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 9061 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 181 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.019925 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate 0.019976 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 4 2.21% 2.21% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.21% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 68 37.57% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 11818 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.768658 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.451524 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 11644 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.778169 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.459347 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 8185 69.26% 69.26% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 1366 11.56% 80.82% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 758 6.41% 87.23% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 566 4.79% 92.02% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 474 4.01% 96.03% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 284 2.40% 98.43% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 122 1.03% 99.47% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 8032 68.98% 68.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1346 11.56% 80.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 757 6.50% 87.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 566 4.86% 91.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 475 4.08% 95.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 283 2.43% 98.41% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 122 1.05% 99.46% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 48 0.41% 99.87% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.13% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 11818 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.440202 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 11644 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.440539 # Inst issue rate
system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses
system.cpu.iq.fp_inst_queue_reads 54 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_writes 58 # Number of floating instruction queue writes
-system.cpu.iq.int_alu_accesses 9243 # Number of integer alu accesses
-system.cpu.iq.int_inst_queue_reads 30172 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_wakeup_accesses 7972 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.int_inst_queue_writes 17831 # Number of integer instruction queue writes
-system.cpu.iq.iqInstsAdded 11904 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 9084 # Number of instructions issued
+system.cpu.iq.int_alu_accesses 9220 # Number of integer alu accesses
+system.cpu.iq.int_inst_queue_reads 29952 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_wakeup_accesses 7973 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_writes 17769 # Number of integer instruction queue writes
+system.cpu.iq.iqInstsAdded 11873 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9061 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 2 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 5957 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 5926 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
system.cpu.iq.iqSquashedOperandsExamined 10171 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 41 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34500 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34487.804878 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31365.853659 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1414500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 1414000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 41 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1286000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 41 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 434 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34308.860759 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34312.182741 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31166.666667 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 39 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 13552000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.910138 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 395 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_hits 40 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 13519000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.907834 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 394 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_miss_latency 11968000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.884793 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 384 # number of ReadReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.101562 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.104167 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 475 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34326.834862 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34328.735632 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.882353 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 39 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14966500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.917895 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 436 # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_hits 40 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 14933000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.915789 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 435 # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_miss_latency 13254000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.894737 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 425 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.006167 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 202.074939 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.006174 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 202.304778 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 475 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34326.834862 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34328.735632 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.882353 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 39 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14966500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.917895 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 436 # number of overall misses
-system.cpu.l2cache.overall_mshr_hits 11 # number of overall MSHR hits
+system.cpu.l2cache.overall_hits 40 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 14933000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.915789 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 435 # number of overall misses
+system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_miss_latency 13254000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.894737 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 425 # number of overall MSHR misses
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.sampled_refs 384 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 202.074939 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 202.304778 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 11 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 2545 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1646 # Number of stores inserted to the mem dependence unit.
-system.cpu.misc_regfile_reads 15396 # number of misc regfile reads
+system.cpu.memDep0.insertedStores 1654 # Number of stores inserted to the mem dependence unit.
+system.cpu.misc_regfile_reads 15406 # number of misc regfile reads
system.cpu.misc_regfile_writes 3 # number of misc regfile writes
-system.cpu.numCycles 20636 # number of cpu cycles simulated
+system.cpu.numCycles 20568 # number of cpu cycles simulated
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4006 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 46 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 7538 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 7474 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 123 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 37508 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 13960 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 10094 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 2314 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1162 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 187 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 6085 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:fp_rename_lookups 744 # Number of floating rename lookups
-system.cpu.rename.RENAME:int_rename_lookups 36764 # Number of integer rename lookups
-system.cpu.rename.RENAME:serializeStallCycles 271 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:RenameLookups 37531 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 13957 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 10098 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2298 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1138 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 185 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 6089 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:fp_rename_lookups 816 # Number of floating rename lookups
+system.cpu.rename.RENAME:int_rename_lookups 36715 # Number of integer rename lookups
+system.cpu.rename.RENAME:serializeStallCycles 203 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 4 # count of serializing insts renamed
system.cpu.rename.RENAME:skidInsts 537 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 1 # count of temporary serializing insts renamed
-system.cpu.rob.rob_reads 22070 # The number of ROB reads
-system.cpu.rob.rob_writes 24470 # The number of ROB writes
-system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rob.rob_reads 21909 # The number of ROB reads
+system.cpu.rob.rob_writes 24423 # The number of ROB writes
+system.cpu.timesIdled 183 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
---------- End Simulation Statistics ----------
All Rights Reserved
-M5 compiled Feb 11 2011 17:53:57
-M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch
-M5 started Feb 11 2011 17:54:00
+M5 compiled Feb 21 2011 14:33:02
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:33:10
M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 2481190 # Simulator instruction rate (inst/s)
-host_mem_usage 374936 # Number of bytes of host memory used
-host_seconds 20.74 # Real time elapsed on the host
-host_tick_rate 1257294139 # Simulator tick rate (ticks/s)
+host_inst_rate 1506664 # Simulator instruction rate (inst/s)
+host_mem_usage 378044 # Number of bytes of host memory used
+host_seconds 34.14 # Real time elapsed on the host
+host_tick_rate 763738517 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 51454118 # Number of instructions simulated
+sim_insts 51436382 # Number of instructions simulated
sim_seconds 0.026074 # Number of seconds simulated
sim_ticks 26073617500 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100454 # number of LoadLockedReq accesses(hits+misses)
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 51454118 # Number of instructions executed
+system.cpu.num_insts 51436382 # Number of instructions executed
system.cpu.num_int_alu_accesses 41848094 # Number of integer alu accesses
system.cpu.num_int_insts 41848094 # number of integer instructions
system.cpu.num_int_register_reads 129780130 # number of times the integer registers were read
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
All Rights Reserved
-M5 compiled Feb 11 2011 17:53:57
-M5 revision 6c65f7ee86c1 7949 default qtip tip ext/vnc_stats_updates.patch
-M5 started Feb 11 2011 17:54:00
+M5 compiled Feb 21 2011 14:33:02
+M5 revision b06fecbc6572 7972 default qtip tip ext/print_mem_more.patch
+M5 started Feb 21 2011 14:33:10
M5 executing on u200439-lin.austin.arm.com
-command line: build/ARM_FS/m5.fast -d build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM_FS/m5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux.arm
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 1425483 # Simulator instruction rate (inst/s)
-host_mem_usage 374960 # Number of bytes of host memory used
-host_seconds 35.49 # Real time elapsed on the host
-host_tick_rate 3232752918 # Simulator tick rate (ticks/s)
+host_inst_rate 844061 # Simulator instruction rate (inst/s)
+host_mem_usage 378168 # Number of bytes of host memory used
+host_seconds 59.91 # Real time elapsed on the host
+host_tick_rate 1914863662 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 50588397 # Number of instructions simulated
+sim_insts 50570667 # Number of instructions simulated
sim_seconds 0.114727 # Number of seconds simulated
sim_ticks 114726567000 # Number of ticks simulated
system.cpu.dcache.LoadLockedReq_accesses::0 100290 # number of LoadLockedReq accesses(hits+misses)
system.cpu.num_fp_register_writes 1834 # number of times the floating registers were written
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.num_idle_cycles 0 # Number of idle cycles
-system.cpu.num_insts 50588397 # Number of instructions executed
+system.cpu.num_insts 50570667 # Number of instructions executed
system.cpu.num_int_alu_accesses 41841366 # Number of integer alu accesses
system.cpu.num_int_insts 41841366 # number of integer instructions
system.cpu.num_int_register_reads 138034734 # number of times the integer registers were read
-build/ARM_FS/tests/fast/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
+build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing FAILED!
projects / gem5.git / commitdiff