t:$dff* -> t:$dff t:$dffe
authorEddie Hung <eddieh@ece.ubc.ca>
Thu, 4 Apr 2019 14:39:19 +0000 (07:39 -0700)
committerEddie Hung <eddieh@ece.ubc.ca>
Thu, 4 Apr 2019 14:39:19 +0000 (07:39 -0700)
techlibs/xilinx/synth_xilinx.cc

index 601a6811d10196e0b92941f5e3b42615853d64ef..5a3725e7ddd47e7eb30a121634abed6add325caa 100644 (file)
@@ -113,7 +113,7 @@ struct SynthXilinxPass : public Pass
                log("        dffsr2dff\n");
                log("        dff2dffe\n");
                log("        opt -full\n");
-               log("        simplemap t:$dff* (without -nosrl and without -retime only)\n");
+               log("        simplemap t:$dff t:$dffe (without -nosrl and without -retime only)\n");
                log("        shregmap -tech xilinx -minlen 3 (without -nosrl and without -retime only)\n");
                log("        techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v\n");
                log("        opt -fast\n");
@@ -266,7 +266,7 @@ struct SynthXilinxPass : public Pass
                        Pass::call(design, "opt -full");
 
                        if (!nosrl && !retime) {
-                               Pass::call(design, "simplemap t:$dff*");
+                               Pass::call(design, "simplemap t:$dff t:$dffe");
                                Pass::call(design, "shregmap -tech xilinx -minlen 3");
                        }