Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.

diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 9739fe10ea64ddeb336b50d66cea6d6ddc4a9a2e..f20ed35f18f5b86bf82b1dd231bbdd36147f1a4f 100644 (file)
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-27  Nick Clifton  <nickc@cambridge.redhat.com>
+
+       * thumbemu.c (ARMul_ThumbDecode, Case 31): Do not set LR to pc +
+       2, it has already been advanced.
+
 2002-05-23  Nick Clifton  <nickc@cambridge.redhat.com>
 
        * thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1)

diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 283e7d5cf5ad1fecee5411939cdaa51389f0605d..1b28edf80f0ab046be41891d93f34b0587b94423 100644 (file)
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -489,7 +489,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
             if r14 is not suitably initialised.  */
          {
            ARMword tmp = (pc + 2);
-           
+
            state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1))
                              & 0xFFFFFFFC);
            CLEART;
@@ -509,8 +509,9 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
          second half of this BL, and if it is we simulate it
          immediately.  */
       state->Reg[14] = state->Reg[15] \
-       +(((tinstr & 0x07FF) << 12) \
-         |((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+       + (((tinstr & 0x07FF) << 12) \
+          | ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+
       valid = t_branch;                /* in-case we don't have the 2nd half */
       tinstr = next_instr;     /* move the instruction down */
       pc += 2;                 /* point the pc at the 2nd half */
@@ -543,7 +544,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
          the simulation of it on its own, with undefined results if
          r14 is not suitably initialised.  */
       {
-       ARMword tmp = (pc + 2);
+       ARMword tmp = pc;
+
        state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1));
        state->Reg[14] = (tmp | 1);
        valid = t_branch;