fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...

src/arch/mips/isa/decoder.isa:
    commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
    edit fp format
src/arch/mips/isa/formats/mem.isa:
    fix for basic store instructions

--HG--
extra : convert_revision : 30cb5a474e78ac9292b6ab37d433db947a177731

diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa
index 0af84e36bf5f07b8e3d83f96be000ede12a11582..e55d2e0705d7a608c54e5fa93e9edf631399b2b8 100644 (file)
--- a/src/arch/mips/isa/decoder.isa
+++ b/src/arch/mips/isa/decoder.isa
@@ -27,6 +27,7 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 // Authors: Korey Sewell
+//          Brett Miller
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -557,20 +558,12 @@ decode OPCODE_HI default Unknown::unknown() {
                 }});
 
                 0x1F: deret({{
-                  // if(EJTagImplemented()) {
-                  if(Debug_DM == 1){
-                    Debug_DM = 1;
-                    Debug_IEXI = 0;
-                    NPC = DEPC;
-                  }
-                  else
-                    {
-                      // Undefined;
-                    }
-                  //} // EJTag Implemented
-                  //else {
-                  // Reserved Instruction Exception
-                  //}
+                    //if(Debug_DM == 1){
+                    //Debug_DM = 1;
+                    //Debug_IEXI = 0;
+                    //NPC = DEPC;
+                    //}
+                    panic("deret not implemented");
                 }});
               }
 

diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 4b340e2e62a96805f671a9f11f6e708acca2c0cb..4e81ae2cf25e9ce11cb1aff604283cff9ddb2851 100644 (file)
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -150,8 +150,10 @@ output exec {{
                 //Read FCSR from FloatRegFile
                 uint32_t fcsr_bits = cpu->tcBase()->readFloatRegBits(FCSR);
 
+                uint32_t new_fcsr = genInvalidVector(fcsr_bits);
+
                 //Write FCSR from FloatRegFile
-                cpu->tcBase()->setFloatRegOperandBits(FCSR, genInvalidVector(fcsr_bits));
+                cpu->tcBase()->setFloatRegBits(FCSR, new_fcsr);
 
                 if (traceData) { traceData->setData(mips_nan); }
                 return true;

diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 81e2318100b84235c39379499e509bcfce63e6d9..18d1f52f99065457f110886447f2d1ef9673e85a 100644 (file)
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -369,7 +369,6 @@ def template StoreMemAccExecute {{
     {
         Addr EA;
         Fault fault = NoFault;
-        uint64_t write_result = 0;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -383,7 +382,7 @@ def template StoreMemAccExecute {{
 
         if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+                              memAccessFlags, NULL);
             // @NOTE: Need to Call Complete Access to Set Trace Data
             //if (traceData) { traceData->setData(Mem); }
         }
@@ -434,7 +433,6 @@ def template StoreExecute {{
     {
         Addr EA;
         Fault fault = NoFault;
-        uint64_t write_result = 0;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -447,7 +445,7 @@ def template StoreExecute {{
 
         if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
-                              memAccessFlags, &write_result);
+                              memAccessFlags, NULL);
             if (traceData) { traceData->setData(Mem); }
         }