Add early code for libgram

diff --git a/libgram/Makefile b/libgram/Makefile
new file mode 100644 (file)
index 0000000..1f1b138
--- /dev/null
+++ b/libgram/Makefile
@@ -0,0 +1,15 @@
+CSR_CSV_FILE := ddr3soc_resources.csv
+
+OBJS := 
+
+TRIPLE := riscv64-unknown-elf
+
+CC      := $(TRIPLE)-gcc
+AS      := $(TRIPLE)-as
+OBJCOPY := $(TRIPLE)-objcopy
+PYTHON  := python
+
+CFLAGS  := -march=rv32i -mabi=ilp32 -nostdlib -Os -Iinclude
+LDFLAGS := -march=rv32i -mabi=ilp32 -nostdlib
+
+src/

diff --git a/libgram/README.md b/libgram/README.md
new file mode 100644 (file)
index 0000000..f7db922
--- /dev/null
+++ b/libgram/README.md
@@ -0,0 +1,35 @@
+# libgram, the C companion for gram
+
+libgram is the C library for gram core initialization.
+
+## HowTo
+
+Provide the CSV file from your LambdaSoC build to the Makefile:
+
+```bash
+make CSR_CSV_FILE=$SOC_BUILD/soc/soc_resources.csv
+```
+
+In your firmware:
+
+```C
+#include <gram.h>
+
+int main(void) {
+       int err = gram_init();
+
+       /* insert something meaningful here */
+
+       return 0;
+}
+```
+
+Link it to this library and you should be good to go!
+
+## Error handling
+
+```
+GRAM_ERR_NONE: No error happened (hardcoded to zero)
+GRAM_ERR_UNDOCUMENTED: Undocumented error, shame on us lazy coders (take a look at the code)
+GRAM_ERR_MEMTEST: Memtest failed
+```

diff --git a/libgram/include/gram.h b/libgram/include/gram.h
new file mode 100644 (file)
index 0000000..a16f5b8
--- /dev/null
+++ b/libgram/include/gram.h
@@ -0,0 +1,14 @@
+#ifndef GRAM_H
+#define GRAM_H
+
+enum GramError {
+       GRAM_ERR_NONE = 0,
+       GRAM_ERR_UNDOCUMENTED,
+       GRAM_ERR_MEMTEST,
+       
+};
+
+int gram_init(void);
+int gram_memtest(void);
+
+#endif /* GRAM_H */

diff --git a/libgram/src/dfii.h b/libgram/src/dfii.h
new file mode 100644 (file)
index 0000000..f4d3e23
--- /dev/null
+++ b/libgram/src/dfii.h
@@ -0,0 +1,16 @@
+#ifndef DFII_H
+#define DFII_H
+
+#define DFII_CONTROL_SEL (1 << 1)
+#define DFII_CONTROL_CKE (1 << 2)
+#define DFII_CONTROL_ODT (1 << 3)
+#define DFII_CONTROL_RESET_N (1 << 4)
+
+#define DFII_COMMAND_CS (1 << 1)
+#define DFII_COMMAND_WE (1 << 2)
+#define DFII_COMMAND_CAS (1 << 3)
+#define DFII_COMMAND_RAS (1 << 4)
+#define DFII_COMMAND_WRDATA (1 << 5)
+#define DFII_COMMAND_WRDATA (1 << 6)
+
+#endif /* DFII_H */

diff --git a/libgram/src/helpers.h b/libgram/src/helpers.h
new file mode 100644 (file)
index 0000000..3418f72
--- /dev/null
+++ b/libgram/src/helpers.h
@@ -0,0 +1,6 @@
+#ifndef HELPERS_H
+#define HELPERS_H
+
+
+
+#endif HELPERS_H

diff --git a/libgram/src/hw_regs.h b/libgram/src/hw_regs.h
new file mode 100644 (file)
index 0000000..93ef450
--- /dev/null
+++ b/libgram/src/hw_regs.h
@@ -0,0 +1,28 @@
+#ifndef HW_REGS_H
+#define HW_REGS_H
+
+struct ECP5PHY {
+       uint32_t dly_sel;
+       uint32_t rdly_dq_rst;
+       uint32_t rdly_dq_inc;
+       uint32_t rdly_dq_bitslip_rst;
+       uint32_t rdly_dq_bitslip;
+       uint32_t burstdet_clr;
+       uint32_t burstdet_seen;
+} __attribute__((packed));
+
+struct DFII_Phase {
+       uint32_t command;
+       uint32_t command_issue;
+       uint32_t address;
+       uint32_t baddress;
+       uint32_t wrdata;
+       uint32_t rddata;
+} __attribute__((packed));
+
+struct DFII {
+       uint32_t control;
+
+} __attribute__((packed));
+
+#endif /* HW_REGS_H */
\ No newline at end of file

diff --git a/libgram/src/init.c b/libgram/src/init.c
new file mode 100644 (file)
index 0000000..4c517f4
--- /dev/null
+++ b/libgram/src/init.c
@@ -0,0 +1,40 @@
+#include <gram.h>
+
+int gram_init(void) {
+#ifdef CSR_DDRCTRL_BASE
+       ddrctrl_init_done_write(0);
+       ddrctrl_init_error_write(0);
+#endif
+
+       sdrsw();
+       init_sequence();
+
+#ifdef CSR_DDRPHY_BASE
+#ifdef DDRPHY_CMD_DELAY
+       ddrphy_cdly(DDRPHY_CMD_DELAY);
+#endif
+#if CSR_DDRPHY_EN_VTC_ADDR
+       ddrphy_en_vtc_write(0);
+#endif
+#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
+       sdrlevel();
+#endif
+#if CSR_DDRPHY_EN_VTC_ADDR
+       ddrphy_en_vtc_write(1);
+#endif
+#endif
+       sdrhw();
+
+       if(!memtest()) {
+#ifdef CSR_DDRCTRL_BASE
+               ddrctrl_init_done_write(1);
+               ddrctrl_init_error_write(1);
+#endif
+               return GRAM_ERR_MEMTEST;
+       }
+#ifdef CSR_DDRCTRL_BASE
+       ddrctrl_init_done_write(1);
+#endif
+
+       return GRAM_ERR_NONE;
+}

diff --git a/libgram/src/memtest.c b/libgram/src/memtest.c
new file mode 100644 (file)
index 0000000..69da9b1
--- /dev/null
+++ b/libgram/src/memtest.c
@@ -0,0 +1,5 @@
+#include <gram.h>
+
+int gram_memtest(void) {
+       return 0;
+}

diff --git a/libgram/tools/csv2c b/libgram/tools/csv2c
new file mode 100755 (executable)
index 0000000..d9c16f8
--- /dev/null
+++ b/libgram/tools/csv2c
@@ -0,0 +1,24 @@
+#!/usr/bin/env python3
+import csv
+import argparse
+
+def generateHeader(input_file, output_file):
+       constant = output_file.replace('.', '_').upper()
+       header = "#ifndef {}\n#define {}\n".format(constant, constant)
+
+       with open('test.csv', newline='\n') as csvfile:
+               csrreader = csv.reader(filter(lambda row: row[0]!='#', csvfile), delimiter=',')
+               for row in csrreader:
+                       header += "volatile uint32_t *{} = {};\n".format(row[0].strip(), row[1].strip())
+
+       header += "#endif /* {} */\n".format(constant)
+
+       return header
+
+if __name__ == "__main__":
+       parser = argparse.ArgumentParser()
+       parser.add_argument("in_csv", help="input csv file")
+       parser.add_argument("out_h", help="output header file")
+       args = parser.parse_args()
+
+       print(generateHeader(args.in_csv, args.out_h))