add more regs profiles to ls012 optable.csv

diff --git a/openpower/sv/rfc/ls012/optable.csv b/openpower/sv/rfc/ls012/optable.csv
index 721733fccae564896ea94bdab3bb34cd03917260..e7f096e275152c216823519678ef3a36279953df 100644 (file)
--- a/openpower/sv/rfc/ls012/optable.csv
+++ b/openpower/sv/rfc/ls012/optable.csv
@@ -1,24 +1,24 @@
 op, rfc, priority, cost, SVP64, group, PO1, page, regs
 # LD/ST-Postincrement (FP TODO)
-lbzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lbzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lhzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lhzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lhaup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lhaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lwzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lwzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-lwaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-ldup,     ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-ldupx,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 
-stbup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-stbupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-sthup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-sthupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-stwup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-stwupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-stdup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 
-stdupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore,
+lbzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lbzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lhzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lhzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lhaup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lhaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lwzup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+lwzupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+lwaupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+ldup,     ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 1R2W
+ldupx,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedload, 2R2W
+stbup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stbupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+sthup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+sthupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+stwup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stwupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
+stdup,    ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 2R1W
+stdupx,   ls011, high, ??, yes, EXT2xx, ??, isa/pifixedstore, 3R1W
 FP-LD,    ls011, high, ??, yes, EXT2xx, ??, TODO,
 FP-ST,    ls011, high, ??, yes, EXT2xx, ??, TODO,
 # Bitmanip LUT2/3 operations. high cost high reward
@@ -55,18 +55,18 @@ mv.swizzle,  TBD,   TBD,  4,  yes, TBD,    yes, sv/mv.swizzle, 2R2W
 fmv.swizzle, TBD,   TBD,  4,  yes, TBD,    yes, sv/mv.swizzle, 2R2W
 # CR weirds
 crrweird,    TBD,   high, 8,  yes, TBD,    no, sv/cr_int_predication, 1r1W1w
-mfcrweird,   TBD,   high, 8,  yes, TBD,    no, sv/cr_int_predication, 
-mtcrrweird,  TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication,
-mtcrweird,   TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication,
-crweirder,   TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication,
-mcrfm,       TBD,   high, 9,  yes, EXT0xx, no, sv/cr_int_predication,
+mfcrweird,   TBD,   high, 8,  yes, TBD,    no, sv/cr_int_predication, 1r1W1w
+mtcrrweird,  TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication, 1R1r1w
+mtcrweird,   TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication, 1R1r1w
+crweirder,   TBD,   high, 9,  yes, TBD,    no, sv/cr_int_predication, 2r1w
+mcrfm,       TBD,   high, 9,  yes, EXT0xx, no, sv/cr_int_predication, 2r1w
 # fclass (Scalar variant of xvtstdcsp)
 fptstp(s),   TBD,   high,  10, yes, EXT0xx, no, sv/fclass, 1R1w
 # INT<->FP mv
-fmvfg(s),    ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv,
-fcvtfg(s),   ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv,
-fcvttg(s),   ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv,
-fcvtstg(s),  ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv,
+fmvfg(s),    ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w
+fcvtfg(s),   ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w
+fcvttg(s),   ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w
+fcvtstg(s),  ls006, high, 10, yes, EXT0xx, no, sv/int_fp_mv, 1R1W1w
 # Big-Integer Chained 3-in 2-out (64-bit Carry)
 dsld,        ls003, high, 5,  yes, EXT0xx, no, sv/biginteger, 3R2W1w
 dsrd,        ls003, high, 5,  yes, EXT0xx, no, sv/biginteger, 3R2W1w