(no commit message)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 7a5339070e27d44812f2e81988e3acc5ae32e5ce..3aa7ba12c91683a2c19bf6c8df608b3788f3f61c 100644 (file)
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -19,6 +19,11 @@ Source code:
 
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
+Video walkthrough of regfile relationship to Function Units in core:
+<https://youtu.be/7Th1b-jq40k>
+
+[[!img core_regfiles_fus_pickers.jpg size="500px"]]
+
 # Regfile groups, Port Allocations and bit-widths
 
 * INT regfile: 32x 64-bit with 4R1W