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Merge pull request #2396 from YosysHQ/claire/empty-param
authorclairexen <claire@symbioticeda.com>
Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)
committerGitHub <noreply@github.com>
Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)
Ignore empty parameters in Verilog module instantiations


Trivial merge