traceData->setData(data);
}
Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
+ DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
data = TheISA::gtoh(data);
+ DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
+
if (traceData)
traceData->setData(data);
return fault;
{
assert(sizeof(storeData) >= size);
memcpy(&storeData, data, size);
+ DPRINTF(InOrderDynInst, "(2) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
+ threadNumber, seqNum, storeData);
return cpu->write(this, (uint8_t *)&storeData, size, addr, flags, res);
}
inline Fault
InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- storeData = data;
-
- DPRINTF(InOrderDynInst, "[tid:%i]: [sn:%i] Setting store data to %#x.\n",
- threadNumber, seqNum, storeData);
if (traceData) {
traceData->setAddr(addr);
traceData->setData(data);
}
- storeData = TheISA::htog(data);
+ data = TheISA::htog(data);
+ DPRINTF(InOrderDynInst, "(1) [tid:%i]: [sn:%i] Setting store data to %#x.\n",
+ threadNumber, seqNum, data);
return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
}
} else {
cache_req->dataPkt->dataStatic(&cache_req->inst->storeData);
}
+
+ DPRINTF(InOrderCachePort,
+ "[tid:%u]: [sn:%i]: Storing data: %s\n",
+ tid, inst->seqNum,
+ printMemData(cache_req->dataPkt->getPtr<uint8_t>(),
+ cache_req->dataPkt->getSize()));
if (cache_req->memReq->isCondSwap()) {
assert(write_res);