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Add sim only divw
author
Anton Blanchard
<anton@linux.ibm.com>
Wed, 28 Aug 2019 04:07:29 +0000
(14:07 +1000)
committer
Anton Blanchard
<anton@ozlabs.org>
Wed, 28 Aug 2019 04:07:29 +0000
(14:07 +1000)
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
execute1.vhdl
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diff --git
a/execute1.vhdl
b/execute1.vhdl
index f24ccfb500e87a94a25b123d178447f35e10e58e..ae34c1fb9c0069643587b757a092208a1131938f 100644
(file)
--- a/
execute1.vhdl
+++ b/
execute1.vhdl
@@
-336,7
+336,14
@@
begin
if SIM = true then
result := ppc_divwu(e.read_data1, e.read_data2);
result_en := 1;
-
+ else
+ terminate_out <= '1';
+ report "illegal";
+ end if;
+ when OP_DIVW =>
+ if SIM = true then
+ result := ppc_divw(e.read_data1, e.read_data2);
+ result_en := 1;
else
terminate_out <= '1';
report "illegal";