arch-arm: CNTHCTL trap to EL2 only if ARMv8.6-ECV implemented
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 30 Mar 2020 12:58:43 +0000 (13:58 +0100)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 6 Apr 2020 08:31:26 +0000 (08:31 +0000)
In condGenericTimerCommonEL1SystemAccessTrapEL2 we were trapping
accesses to the EL1 virtual timer/counter registers to EL2, not
considering that this feature is part of ARMv8.6-ECV only
(not supported at the moment)

Change-Id: Ic03bcae436a105fb139a74126881b665ee08c912
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Adrian Herrera <adrian.herrera@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27408
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/miscregs_types.hh
src/arch/arm/utility.cc

index 0b7098f69ed53ac16dbad2976af431d7269697af..cbc7adb16b5edaae5e0596a47705a1308a5715c5 100644 (file)
@@ -115,6 +115,7 @@ namespace ArmISA
     EndBitUnion(AA64ISAR1)
 
     BitUnion64(AA64MMFR0)
+        Bitfield<63, 60> ecv;
         Bitfield<47, 44> exs;
         Bitfield<43, 40> tgran4_2;
         Bitfield<39, 36> tgran64_2;
index 7c70def08d43c3c1e7914c4c53f6760d979e6e52..9947bdd28dc94204462d953a1f3d790468e92702 100644 (file)
@@ -1086,6 +1086,7 @@ bool
 condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
                                              ThreadContext *tc)
 {
+    const AA64MMFR0 mmfr0 = tc->readMiscRegNoEffect(MISCREG_ID_AA64MMFR0_EL1);
     const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
     const RegVal cnthctl_val = tc->readMiscReg(MISCREG_CNTHCTL_EL2);
     const CNTHCTL cnthctl = cnthctl_val;
@@ -1096,13 +1097,19 @@ condGenericTimerCommonEL1SystemAccessTrapEL2(const MiscRegIndex miscReg,
         return hcr.e2h ? !cnthctl_e2h.el1pcten : !cnthctl.el1pcten;
       case MISCREG_CNTVCT:
       case MISCREG_CNTVCT_EL0:
-        return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
+        if (!mmfr0.ecv)
+            return false;
+        else
+            return hcr.e2h ? cnthctl_e2h.el1tvct : cnthctl.el1tvct;
       case MISCREG_CNTP_CTL ... MISCREG_CNTP_TVAL_S:
       case MISCREG_CNTP_CTL_EL0 ... MISCREG_CNTP_TVAL_EL0:
         return hcr.e2h ? !cnthctl_e2h.el1pten : false;
       case MISCREG_CNTV_CTL ... MISCREG_CNTV_TVAL:
       case MISCREG_CNTV_CTL_EL0 ... MISCREG_CNTV_TVAL_EL0:
-        return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
+        if (!mmfr0.ecv)
+            return false;
+        else
+            return hcr.e2h ? cnthctl_e2h.el1tvt : cnthctl.el1tvt;
       default:
         break;
     }