Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 028cd6d8126f55b8a6b0ba87b3bcf0aed9f70b2a..c4c08d5b83cba8316f7e352c951f24ac1f3f11ae 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -619,7 +619,7 @@ namespace {
                                param_bool("\\CLK_POLARITY");
                                param("\\PRIORITY");
                                port("\\CLK", 1);
-                               port("\\EN", 1);
+                               port("\\EN", param("\\WIDTH"));
                                port("\\ADDR", param("\\ABITS"));
                                port("\\DATA", param("\\WIDTH"));
                                check_expected();
@@ -639,7 +639,7 @@ namespace {
                                port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
                                port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
                                port("\\WR_CLK", param("\\WR_PORTS"));
-                               port("\\WR_EN", param("\\WR_PORTS"));
+                               port("\\WR_EN", param("\\WR_PORTS") * param("\\WIDTH"));
                                port("\\WR_ADDR", param("\\WR_PORTS") * param("\\ABITS"));
                                port("\\WR_DATA", param("\\WR_PORTS") * param("\\WIDTH"));
                                check_expected();

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index e7895521a6d559ab258a927129bb22a6f10b10ff..f09c49298a5a5e40d3aafb65accfc2724f6132fb 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -256,8 +256,9 @@ If this parameter is set to {\tt 1'b1}, a read and write to the same address in
 return the new value. Otherwise the old value is returned.
 \end{itemize}
 
-The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN}, an address input \B{ADDR}
-and a data input \B{DATA}. They also have the following parameters:
+The {\tt \$memwr} cells have a clock input \B{CLK}, an enable input \B{EN} (one
+enable bit for each data bit), an address input \B{ADDR} and a data input
+\B{DATA}. They also have the following parameters:
 
 \begin{itemize}
 \item \B{MEMID} \\
@@ -341,7 +342,7 @@ This input is \B{RD\_PORTS}*\B{WIDTH} bits wide, containing all data signals for
 This input is \B{WR\_PORTS} bits wide, containing all clock signals for the write ports.
 
 \item \B{WR\_EN} \\
-This input is \B{WR\_PORTS} bits wide, containing all enable signals for the write ports.
+This input is \B{WR\_PORTS}*\B{WIDTH} bits wide, containing all enable signals for the write ports.
 
 \item \B{WR\_ADDR} \\
 This input is \B{WR\_PORTS}*\B{ABITS} bits wide, containing all address signals for the write ports.