stats: Update stats for syscall emulation Linux kernel changes.
authorAli Saidi <Ali.Saidi@ARM.com>
Wed, 15 Aug 2012 14:38:05 +0000 (10:38 -0400)
committerAli Saidi <Ali.Saidi@ARM.com>
Wed, 15 Aug 2012 14:38:05 +0000 (10:38 -0400)
160 files changed:
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt

index 647cf0cf8e48bd5917806e15b5022fb3392b5be2..ca675ac92c9020717a009ab43e53624aa3dd1b1d 100644 (file)
@@ -489,7 +489,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -512,7 +512,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 196024f42aad3fc21c1e0dd2f2c613c80e6f825c..5518ac66c0ab23e52d65f78c35c41a58ad5b0bb9 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:32:18
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:42
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 389181871500 because target called exit()
+Exiting @ tick 389171398000 because target called exit()
index 09d53c6a602d81d76a516d55804c95b8b5884c6c..1f6271301f60b1b9bdaf4d8cdf02b2adc6f1fd7f 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.389182                       # Number of seconds simulated
-sim_ticks                                389181871500                       # Number of ticks simulated
-final_tick                               389181871500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.389171                       # Number of seconds simulated
+sim_ticks                                389171398000                       # Number of ticks simulated
+final_tick                               389171398000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 233275                       # Simulator instruction rate (inst/s)
-host_op_rate                                   234010                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               64792479                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223132                       # Number of bytes of host memory used
-host_seconds                                  6006.59                       # Real time elapsed on the host
-sim_insts                                  1401188958                       # Number of instructions simulated
-sim_ops                                    1405604152                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             78592                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1679360                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1757952                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        78592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           78592                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       163456                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            163456                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1228                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              26240                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 27468                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            2554                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 2554                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               201942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              4315103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 4517045                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          201942                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             201942                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            419999                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 419999                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            419999                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              201942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             4315103                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                4937044                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                 172352                       # Simulator instruction rate (inst/s)
+host_op_rate                                   172895                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               47869738                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232600                       # Number of bytes of host memory used
+host_seconds                                  8129.80                       # Real time elapsed on the host
+sim_insts                                  1401188945                       # Number of instructions simulated
+sim_ops                                    1405604139                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             78528                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1679232                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1757760                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        78528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           78528                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       163392                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            163392                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1227                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              26238                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 27465                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            2553                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 2553                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               201783                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              4314891                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 4516673                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          201783                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             201783                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            419846                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 419846                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            419846                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              201783                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             4314891                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                4936519                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                        778363744                       # number of cpu cycles simulated
+system.cpu.numCycles                        778342797                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 98202538                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           88418167                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            3786555                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              66007710                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 65666961                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 98197174                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           88413236                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            3785239                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              66015510                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 65664831                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                     1332                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 219                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          165889798                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1648919647                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    98202538                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           65668293                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     330430884                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                21692843                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              264292230                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  125                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          2686                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 162826473                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                754831                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          778319405                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.124393                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.146166                       # Number of instructions fetched each cycle (Total)
+system.cpu.BPredUnit.usedRAS                     1336                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 221                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles          165881717                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1648798034                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    98197174                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           65666167                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     330411204                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                21674066                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              264316799                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  122                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          2684                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 162819499                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                755607                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          778298464                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.124294                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.146110                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                447888521     57.55%     57.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 74380250      9.56%     67.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 37976870      4.88%     71.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  9085355      1.17%     73.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 28165073      3.62%     76.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18828553      2.42%     79.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 11512004      1.48%     80.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  3871007      0.50%     81.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                146611772     18.84%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                447887260     57.55%     57.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 74376407      9.56%     67.10% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 37977630      4.88%     71.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  9084449      1.17%     73.15% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 28163510      3.62%     76.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18828809      2.42%     79.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 11510131      1.48%     80.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  3871378      0.50%     81.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                146598890     18.84%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            778319405                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.126165                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        2.118444                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                217790097                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             214638982                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 285156910                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              43029734                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               17703682                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             1642636299                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               17703682                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                241734353                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                36955708                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles       51946820                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 303044657                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             126934185                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             1631312586                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents               31546408                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              73332264                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents          3116970                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          1360939473                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            2755912805                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       2722068159                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          33844646                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1244770452                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                116169021                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts            2679381                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts        2694981                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 272918574                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            438732735                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           180262547                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         255381650                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         82499363                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 1517064379                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded             2634738                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1460855259                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued             54931                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       113760463                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    136767182                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved         391067                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     778319405                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.876935                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.427664                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            778298464                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.126162                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        2.118344                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                217730423                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             214714894                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 285147826                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              43019383                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               17685938                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             1642518992                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               17685938                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                241679768                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                36912628                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles       51960575                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 303022356                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             127037199                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             1631180439                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents               31545211                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              73402474                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents          3147906                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          1360824399                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            2755700072                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       2721856567                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          33843505                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1244770439                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                116053960                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts            2679524                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts        2694715                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 273063750                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            438707438                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           180249753                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         255184370                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         82754828                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 1516941659                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded             2635026                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1460769058                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued             54636                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       113641063                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    136677185                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved         391355                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     778298464                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.876875                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.427909                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           147026932     18.89%     18.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           186493885     23.96%     42.85% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           211074443     27.12%     69.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           130841076     16.81%     86.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            70678954      9.08%     95.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            20414805      2.62%     98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             7717737      0.99%     99.48% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             3979587      0.51%     99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               91986      0.01%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           147064057     18.90%     18.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           186545297     23.97%     42.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           210910023     27.10%     69.96% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           130868567     16.81%     86.78% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            70782480      9.09%     95.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            20278912      2.61%     98.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             7762488      1.00%     99.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             3994514      0.51%     99.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               92126      0.01%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       778319405                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       778298464                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  100522      6.26%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                166576     10.38%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     16.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1142590     71.19%     87.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                195193     12.16%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  113664      7.00%      7.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                166579     10.26%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     17.26% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1139490     70.19%     87.45% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                203791     12.55%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             867158324     59.36%     59.36% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             867086456     59.36%     59.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     59.36% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     59.36% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             2642655      0.18%     59.54% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             2642669      0.18%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.54% # Type of FU issued
@@ -193,160 +193,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.54% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.54% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.54% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            419786972     28.74%     88.28% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           171267308     11.72%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            419773044     28.74%     88.28% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           171266889     11.72%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1460855259                       # Type of FU issued
-system.cpu.iq.rate                           1.876829                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     1604881                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001099                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         3684016874                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        1624580550                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1444446185                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads            17672861                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            9115596                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      8537125                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1453449423                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 9010717                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        215321766                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1460769058                       # Type of FU issued
+system.cpu.iq.rate                           1.876768                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     1623524                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001111                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         3683829696                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        1624339460                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1444358901                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads            17685044                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            9115270                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      8537907                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1453371390                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 9021192                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        215484580                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     36219891                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        54743                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       244893                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     13414405                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     36194595                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        55177                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       245195                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     13401611                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3575                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked         58855                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3537                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked         56120                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               17703682                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 1537187                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                135114                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          1613898993                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           4122313                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             438732735                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            180262547                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts            2549072                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  88195                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                  3279                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         244893                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2354936                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1566356                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              3921292                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1455308115                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             417068435                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           5547144                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               17685938                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 1543124                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                135108                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          1613772123                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           4123534                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             438707438                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            180249753                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts            2549312                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  88176                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                  3284                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         245195                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2354964                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1564711                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              3919675                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1455222367                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             417054039                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           5546691                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                      94199876                       # number of nop insts executed
-system.cpu.iew.exec_refs                    587640720                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 89112594                       # Number of branches executed
-system.cpu.iew.exec_stores                  170572285                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.869702                       # Inst execution rate
-system.cpu.iew.wb_sent                     1453906115                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1452983310                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1154403216                       # num instructions producing a value
-system.cpu.iew.wb_consumers                1205257004                       # num instructions consuming a value
+system.cpu.iew.exec_nop                      94195438                       # number of nop insts executed
+system.cpu.iew.exec_refs                    587626307                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 89109233                       # Number of branches executed
+system.cpu.iew.exec_stores                  170572268                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.869642                       # Inst execution rate
+system.cpu.iew.wb_sent                     1453822475                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1452896808                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1154316777                       # num instructions producing a value
+system.cpu.iew.wb_consumers                1205166277                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.866715                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.866654                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.957807                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1485108101                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps       1489523295                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       124289069                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts     1485108088                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1489523282                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       124161815                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           3786555                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    760616334                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.958311                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.503558                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           3785239                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    760613137                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.958319                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.503249                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    241729742     31.78%     31.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    276918822     36.41%     68.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     43178321      5.68%     73.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     54835847      7.21%     81.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     19622698      2.58%     83.65% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     13346857      1.75%     85.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     30466514      4.01%     89.41% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     10424135      1.37%     90.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     70093398      9.22%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    241688690     31.78%     31.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    276879553     36.40%     68.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     43195227      5.68%     73.86% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     54904670      7.22%     81.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     19686775      2.59%     83.66% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     13341138      1.75%     85.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     30448610      4.00%     89.42% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     10352977      1.36%     90.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     70115497      9.22%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    760616334                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts           1485108101                       # Number of instructions committed
-system.cpu.commit.committedOps             1489523295                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    760613137                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts           1485108088                       # Number of instructions committed
+system.cpu.commit.committedOps             1489523282                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      569360986                       # Number of memory references committed
-system.cpu.commit.loads                     402512844                       # Number of loads committed
+system.cpu.commit.refs                      569360985                       # Number of memory references committed
+system.cpu.commit.loads                     402512843                       # Number of loads committed
 system.cpu.commit.membars                       51356                       # Number of memory barriers committed
-system.cpu.commit.branches                   86248929                       # Number of branches committed
+system.cpu.commit.branches                   86248928                       # Number of branches committed
 system.cpu.commit.fp_insts                    8452036                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1319476388                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1319476376                       # Number of committed integer instructions.
 system.cpu.commit.function_calls              1206914                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              70093398                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              70115497                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2304270430                       # The number of ROB reads
-system.cpu.rob.rob_writes                  3245352893                       # The number of ROB writes
-system.cpu.timesIdled                            1469                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           44339                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1401188958                       # Number of Instructions Simulated
-system.cpu.committedOps                    1405604152                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total            1401188958                       # Number of Instructions Simulated
-system.cpu.cpi                               0.555502                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.555502                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.800172                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.800172                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               1980619061                       # number of integer regfile reads
-system.cpu.int_regfile_writes              1276279795                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                  16952700                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                 10491726                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               593312421                       # number of misc regfile reads
+system.cpu.rob.rob_reads                   2304117867                       # The number of ROB reads
+system.cpu.rob.rob_writes                  3245080355                       # The number of ROB writes
+system.cpu.timesIdled                            1467                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           44333                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                  1401188945                       # Number of Instructions Simulated
+system.cpu.committedOps                    1405604139                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1401188945                       # Number of Instructions Simulated
+system.cpu.cpi                               0.555487                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.555487                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.800221                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.800221                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               1980525328                       # number of integer regfile reads
+system.cpu.int_regfile_writes              1276196147                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                  16956232                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                 10491758                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               593298094                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                2190883                       # number of misc regfile writes
-system.cpu.icache.replacements                    216                       # number of replacements
-system.cpu.icache.tagsinuse               1046.067933                       # Cycle average of tags in use
-system.cpu.icache.total_refs                162824561                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1364                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               119372.845308                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                    214                       # number of replacements
+system.cpu.icache.tagsinuse               1046.066234                       # Cycle average of tags in use
+system.cpu.icache.total_refs                162817587                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1362                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               119543.015419                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1046.067933                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst    1046.066234                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.510775                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.510775                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    162824561                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       162824561                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     162824561                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        162824561                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    162824561                       # number of overall hits
-system.cpu.icache.overall_hits::total       162824561                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    162817587                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       162817587                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     162817587                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        162817587                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    162817587                       # number of overall hits
+system.cpu.icache.overall_hits::total       162817587                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         1912                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          1912                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         1912                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total           1912                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         1912                       # number of overall misses
 system.cpu.icache.overall_misses::total          1912                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     62993000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     62993000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     62993000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     62993000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     62993000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     62993000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    162826473                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    162826473                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    162826473                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    162826473                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    162826473                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    162826473                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62928500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62928500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62928500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62928500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62928500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62928500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    162819499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    162819499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    162819499                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    162819499                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    162819499                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    162819499                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000012                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000012                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000012                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000012                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000012                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000012                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32946.129707                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 32946.129707                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 32946.129707                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 32946.129707                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 32946.129707                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 32946.129707                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 32912.395397                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 32912.395397                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 32912.395397                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 32912.395397                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 32912.395397                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 32912.395397                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -355,106 +355,106 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          547                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          547                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          547                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          547                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          547                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          547                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1365                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1365                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1365                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1365                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1365                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     44905000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     44905000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     44905000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     44905000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     44905000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     44905000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          549                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          549                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          549                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          549                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          549                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          549                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1363                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1363                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1363                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1363                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1363                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1363                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     44825000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     44825000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     44825000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     44825000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     44825000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     44825000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000008                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000008                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000008                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32897.435897                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 32897.435897                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32897.435897                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 32897.435897                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32887.013940                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32887.013940                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32887.013940                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 32887.013940                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32887.013940                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 32887.013940                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 458041                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.912001                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                365776449                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 462137                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 791.489210                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                 457891                       # number of replacements
+system.cpu.dcache.tagsinuse               4094.911972                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                365599087                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 461987                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 791.362283                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              160490000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.912001                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data    4094.911972                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999734                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999734                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    200799973                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       200799973                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    164975157                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      164975157                       # number of WriteReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    200622584                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       200622584                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    164975184                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      164975184                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data         1319                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total            1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data     365775130                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        365775130                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    365775130                       # number of overall hits
-system.cpu.dcache.overall_hits::total       365775130                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       900450                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        900450                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data      1871659                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total      1871659                       # number of WriteReq misses
+system.cpu.dcache.demand_hits::cpu.data     365597768                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        365597768                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    365597768                       # number of overall hits
+system.cpu.dcache.overall_hits::total       365597768                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900300                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900300                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1871632                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1871632                       # number of WriteReq misses
 system.cpu.dcache.SwapReq_misses::cpu.data            7                       # number of SwapReq misses
 system.cpu.dcache.SwapReq_misses::total             7                       # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data      2772109                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2772109                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2772109                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2772109                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  11941437000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  11941437000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  57464288206                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  57464288206                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data        69500                       # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total        69500                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  69405725206                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  69405725206                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  69405725206                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  69405725206                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    201700423                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    201700423                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data      2771932                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2771932                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2771932                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2771932                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11940266500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11940266500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57531206941                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57531206941                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data        69000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total        69000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  69471473441                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  69471473441                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  69471473441                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  69471473441                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    201522884                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    201522884                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data         1326                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total         1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    368547239                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    368547239                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    368547239                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    368547239                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004464                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.004464                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data    368369700                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    368369700                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    368369700                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    368369700                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004467                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.004467                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011218                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.011218                       # miss rate for WriteReq accesses
 system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.005279                       # miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_miss_rate::total     0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.007522                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.007522                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.007522                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.007522                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13261.632517                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13261.632517                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30702.327831                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 30702.327831                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data  9928.571429                       # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency::total  9928.571429                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25037.155900                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25037.155900                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 25037.155900                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 25037.155900                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007525                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.007525                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007525                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.007525                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13262.541930                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13262.541930                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30738.524956                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 30738.524956                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data  9857.142857                       # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::total  9857.142857                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25062.473914                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 25062.473914                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25062.473914                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 25062.473914                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs         4500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
@@ -463,140 +463,140 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs         2250
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       442976                       # number of writebacks
-system.cpu.dcache.writebacks::total            442976                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       700359                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       700359                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1609620                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total      1609620                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data      2309979                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total      2309979                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data      2309979                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total      2309979                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       200091                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       200091                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       262039                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       262039                       # number of WriteReq MSHR misses
+system.cpu.dcache.writebacks::writebacks       442836                       # number of writebacks
+system.cpu.dcache.writebacks::total            442836                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       700344                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       700344                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1609608                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1609608                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2309952                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2309952                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2309952                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2309952                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       199956                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       199956                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       262024                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       262024                       # number of WriteReq MSHR misses
 system.cpu.dcache.SwapReq_mshr_misses::cpu.data            7                       # number of SwapReq MSHR misses
 system.cpu.dcache.SwapReq_mshr_misses::total            7                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       462130                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       462130                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       462130                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       462130                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    927899000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    927899000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5906951258                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   5906951258                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_misses::cpu.data       461980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       461980                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       461980                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       461980                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    927311500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    927311500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5914389505                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5914389505                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        47000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::total        47000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6834850258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6834850258                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6834850258                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6834850258                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6841701005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6841701005                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6841701005                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6841701005                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000992                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001571                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001571                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001570                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.001570                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.005279                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.SwapReq_mshr_miss_rate::total     0.005279                       # mshr miss rate for SwapReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001254                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.001254                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001254                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.001254                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  4637.384990                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  4637.384990                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22542.259961                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22542.259961                       # average WriteReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  4637.577767                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  4637.577767                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22571.938086                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22571.938086                       # average WriteReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data  6714.285714                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total  6714.285714                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14789.886521                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 14789.886521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14789.886521                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 14789.886521                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14809.517739                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 14809.517739                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14809.517739                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 14809.517739                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  2683                       # number of replacements
-system.cpu.l2cache.tagsinuse             22381.394167                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  541833                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 24313                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 22.285732                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  2682                       # number of replacements
+system.cpu.l2cache.tagsinuse             22381.194058                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  541474                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 24308                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 22.275547                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20744.483714                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    995.293943                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    641.616510                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.633071                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.030374                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.019581                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.683026                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst          137                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       195649                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         195786                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       442976                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       442976                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       240248                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       240248                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst          137                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       435897                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          436034                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst          137                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       435897                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         436034                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1228                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4437                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5665                       # number of ReadReq misses
+system.cpu.l2cache.occ_blocks::writebacks 20744.863113                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    994.979192                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    641.351753                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.633083                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.030364                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.019573                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.683020                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          136                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       195513                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         195649                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       442836                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       442836                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       240236                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       240236                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          136                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       435749                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          435885                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          136                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       435749                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         435885                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1227                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4435                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5662                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        21803                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        21803                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1228                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        26240                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         27468                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1228                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        26240                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        27468                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42725500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    151899500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    194625000                       # number of ReadReq miss cycles
+system.cpu.l2cache.demand_misses::cpu.inst         1227                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        26238                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         27465                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1227                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        26238                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        27465                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42694000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    151831500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    194525500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    842839500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total    842839500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     42725500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    994739000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1037464500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     42725500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    994739000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1037464500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1365                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       200086                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       201451                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       442976                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       442976                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       262051                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       262051                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1365                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       462137                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       463502                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1365                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       462137                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       463502                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.899634                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022175                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.028121                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083201                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.083201                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.899634                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.056780                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.059262                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.899634                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.056780                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.059262                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34792.752443                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.730674                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34355.692851                       # average ReadReq miss latency
+system.cpu.l2cache.demand_miss_latency::cpu.inst     42694000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    994671000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1037365000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     42694000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    994671000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1037365000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1363                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       199948                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       201311                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       442836                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       442836                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       262039                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       262039                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1363                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       461987                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       463350                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1363                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       461987                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       463350                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.900220                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022181                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.028126                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.083205                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.083205                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.900220                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.056794                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.059275                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.900220                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.056794                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.059275                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34795.436023                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34234.836528                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34356.322854                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38657.042609                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38657.042609                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34792.752443                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.260671                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 37769.932285                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34792.752443                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.260671                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 37769.932285                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34795.436023                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37909.558655                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37770.435099                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34795.436023                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37909.558655                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37770.435099                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -605,52 +605,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         2554                       # number of writebacks
-system.cpu.l2cache.writebacks::total             2554                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1228                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4437                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5665                       # number of ReadReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks         2553                       # number of writebacks
+system.cpu.l2cache.writebacks::total             2553                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1227                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4435                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5662                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21803                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        21803                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1228                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        26240                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        27468                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1228                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        26240                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        27468                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38798500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    138491500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    177290000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1227                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        26238                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        27465                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1227                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        26238                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        27465                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     38769500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    138429500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    177199000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    776754500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    776754500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38798500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    915246000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    954044500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38798500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    915246000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    954044500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022175                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.028121                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083201                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083201                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056780                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.059262                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.899634                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056780                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.059262                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.869056                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31295.675199                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     38769500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    915184000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    953953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     38769500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    915184000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    953953500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.900220                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022181                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.028126                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.083205                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.083205                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.900220                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.056794                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.059275                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.900220                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.056794                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.059275                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31596.984515                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31212.965051                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.185094                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35626.037701                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35626.037701                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34879.801829                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34732.943789                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31594.869707                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34879.801829                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34732.943789                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31596.984515                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34880.097568                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34733.424358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31596.984515                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34880.097568                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34733.424358                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 47913c070aaaaeae29a57d86d58de983aa065021..bd29989f903e9df08950ee78a9efe3c395f03a91 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index bf7412ed2e7a209df8b489a6ba66dfabc87c4405..a424ec0a0f0f779fb3d2e2873d03a8aa2f7e6950 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:45:41
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:47
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 744764119000 because target called exit()
+Exiting @ tick 744764112500 because target called exit()
index ed36e3ce074a561eccc59ade091a5c3e607b7407..4e5a83c1928059a2bf2aa2212f08f8707eccc606 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.744764                       # Number of seconds simulated
-sim_ticks                                744764119000                       # Number of ticks simulated
-final_tick                               744764119000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                744764112500                       # Number of ticks simulated
+final_tick                               744764112500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3186892                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3196366                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1598188492                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214172                       # Number of bytes of host memory used
-host_seconds                                   466.01                       # Real time elapsed on the host
-sim_insts                                  1485108101                       # Number of instructions simulated
-sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst        5940452044                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        1385817593                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           7326269637                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   5940452044                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      5940452044                       # Number of instructions bytes read from this memory
+host_inst_rate                                3155762                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3165144                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1582576951                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222108                       # Number of bytes of host memory used
+host_seconds                                   470.60                       # Real time elapsed on the host
+sim_insts                                  1485108088                       # Number of instructions simulated
+sim_ops                                    1489523282                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        5940451992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        1385817592                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           7326269584                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   5940451992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      5940451992                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      614672063                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         614672063                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         1485113011                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          402512844                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            1887625855                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst         1485112998                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          402512843                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1887625841                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         166846816                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            166846816                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data               1326                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                  1326                       # Number of other requests responded to by this memory
 system.physmem.bw_read::cpu.inst           7976286575                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1860746990                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9837033566                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1860747005                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9837033580                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst      7976286575                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total         7976286575                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           825324485                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              825324485                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           825324492                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              825324492                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst          7976286575                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2686071475                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10662358051                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2686071498                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10662358072                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                       1489528239                       # number of cpu cycles simulated
+system.cpu.numCycles                       1489528226                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1485108101                       # Number of instructions committed
-system.cpu.committedOps                    1489523295                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.committedInsts                  1485108088                       # Number of instructions committed
+system.cpu.committedOps                    1489523282                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1319481286                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
 system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     78161763                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_conditional_control_insts     78161762                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1319481286                       # number of integer instructions
 system.cpu.num_fp_insts                       8454127                       # number of float instructions
-system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1234343158                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          2499743560                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234343145                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     569365767                       # number of memory refs
-system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_mem_refs                     569365766                       # number of memory refs
+system.cpu.num_load_insts                   402515345                       # Number of load instructions
 system.cpu.num_store_insts                  166850421                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1489528239                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1489528226                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index ed5d7509c8169447f0b7ddb1b98616e23c181164..cd17d9d7320f3cdd438d7c08797a88c1fad21405 100644 (file)
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 7b12cccb1b59d5783c0ac79138ee26dfc2c99629..7275352c5de199c4ce69ebc0a054bddfbe0489fb 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:13:11
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:49
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -38,4 +38,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2063177751000 because target called exit()
+Exiting @ tick 2063177737000 because target called exit()
index 607412a8124fa22705b541bf50e16aeb44f469ae..3078a0fec4dae744736f09ab561b109a5b974985 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.063178                       # Number of seconds simulated
-sim_ticks                                2063177751000                       # Number of ticks simulated
-final_tick                               2063177751000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2063177737000                       # Number of ticks simulated
+final_tick                               2063177737000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1349558                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1353570                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1874864984                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222108                       # Number of bytes of host memory used
-host_seconds                                  1100.44                       # Real time elapsed on the host
-sim_insts                                  1485108101                       # Number of instructions simulated
-sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1527975                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1532517                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2122729697                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231576                       # Number of bytes of host memory used
+host_seconds                                   971.95                       # Real time elapsed on the host
+sim_insts                                  1485108088                       # Number of instructions simulated
+sim_ops                                    1489523282                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             65728                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1672576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1738304                       # Number of bytes read from this memory
@@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst               31858                       # To
 system.physmem.bw_total::cpu.data              810680                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                 920801                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   49                       # Number of system calls
-system.cpu.numCycles                       4126355502                       # number of cpu cycles simulated
+system.cpu.numCycles                       4126355474                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  1485108101                       # Number of instructions committed
-system.cpu.committedOps                    1489523295                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
+system.cpu.committedInsts                  1485108088                       # Number of instructions committed
+system.cpu.committedOps                    1489523282                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1319481286                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
 system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     78161763                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1319481298                       # number of integer instructions
+system.cpu.num_conditional_control_insts     78161762                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1319481286                       # number of integer instructions
 system.cpu.num_fp_insts                       8454127                       # number of float instructions
-system.cpu.num_int_register_reads          2499743582                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1234343157                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          2499743560                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1234343144                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads             16769332                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes            10359244                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     569365767                       # number of memory refs
-system.cpu.num_load_insts                   402515346                       # Number of load instructions
+system.cpu.num_mem_refs                     569365766                       # number of memory refs
+system.cpu.num_load_insts                   402515345                       # Number of load instructions
 system.cpu.num_store_insts                  166850421                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 4126355502                       # Number of busy cycles
+system.cpu.num_busy_cycles                 4126355474                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                    118                       # number of replacements
-system.cpu.icache.tagsinuse                906.409372                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1485111905                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                906.409378                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1485111892                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               1341564.491418                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     906.409372                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     906.409378                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.442583                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.442583                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst   1485111905                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1485111905                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1485111905                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1485111905                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1485111905                       # number of overall hits
-system.cpu.icache.overall_hits::total      1485111905                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst   1485111892                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1485111892                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1485111892                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1485111892                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1485111892                       # number of overall hits
+system.cpu.icache.overall_hits::total      1485111892                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         1107                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          1107                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         1107                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     58777000
 system.cpu.icache.demand_miss_latency::total     58777000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     58777000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     58777000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1485113012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1485113012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1485113012                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1485113012                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1485113012                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1485113012                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1485112999                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1485112999                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1485112999                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1485112999                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1485112999                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1485112999                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
@@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50095.754291
 system.cpu.icache.overall_avg_mshr_miss_latency::total 50095.754291                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 449125                       # number of replacements
-system.cpu.dcache.tagsinuse               4095.205153                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                568907765                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4095.205181                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                568907764                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              588945000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4095.205153                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                1255.254642                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              588931000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4095.205181                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999806                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    402319358                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       402319358                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    402319357                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       402319357                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    166587088                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      166587088                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data         1319                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total            1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data     568906446                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        568906446                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    568906446                       # number of overall hits
-system.cpu.dcache.overall_hits::total       568906446                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     568906445                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        568906445                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    568906445                       # number of overall hits
+system.cpu.dcache.overall_hits::total       568906445                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       193486                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        193486                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       259728                       # number of WriteReq misses
@@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data   7443302000
 system.cpu.dcache.demand_miss_latency::total   7443302000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data   7443302000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total   7443302000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    402512844                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    402512844                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data    402512843                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    402512843                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    166846816                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data         1326                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total         1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    569359660                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    569359660                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    569359660                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    569359660                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    569359659                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    569359659                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    569359659                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    569359659                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000481                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000481                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001557                       # miss rate for WriteReq accesses
@@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13423.371741
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13423.371741                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  2614                       # number of replacements
-system.cpu.l2cache.tagsinuse             22185.384662                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             22185.384813                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  527657                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23998                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 21.987541                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20828.536366                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    857.441703                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    499.406594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 20828.536507                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    857.441709                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    499.406597                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.635636                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.026167                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.015241                       # Average percentage of cache occupancy
index 9d85601cfdf742f51d42f07f136443640de840f3..c34a24e32bd10e6d68d5fac4a57487105c40ca76 100644 (file)
@@ -510,7 +510,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -533,7 +533,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index e9fade7f1011626ff3d11c2de61b9febca4b3aa7..df6cae2daf42708a3b050d732c69412f9b40bb15 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 12:44:41
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:23:13
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -19,12 +19,12 @@ info: Increasing stack size by one page.
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Compressing Input Data, level 3
+info: Increasing stack size by one page.
 Compressed data 97831 bytes in length
 Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Compressing Input Data, level 5
-info: Increasing stack size by one page.
 Compressed data 83382 bytes in length
 Uncompressing Data
 Uncompressed data 1048576 bytes in length
@@ -40,4 +40,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 636963896500 because target called exit()
+Exiting @ tick 636923447500 because target called exit()
index 5a09d9960921759ed33091f1e1be84ac3801aa98..e0bb93d0f3de05dea69f2a7a3cdbeca41a226e1e 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.636964                       # Number of seconds simulated
-sim_ticks                                636963896500                       # Number of ticks simulated
-final_tick                               636963896500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.636923                       # Number of seconds simulated
+sim_ticks                                636923447500                       # Number of ticks simulated
+final_tick                               636923447500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  94339                       # Simulator instruction rate (inst/s)
-host_op_rate                                   173825                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               68282764                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230548                       # Number of bytes of host memory used
-host_seconds                                  9328.33                       # Real time elapsed on the host
-sim_insts                                   880025312                       # Number of instructions simulated
-sim_ops                                    1621493982                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             59072                       # Number of bytes read from this memory
+host_inst_rate                                  70364                       # Simulator instruction rate (inst/s)
+host_op_rate                                   129650                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               50926468                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235448                       # Number of bytes of host memory used
+host_seconds                                 12506.73                       # Real time elapsed on the host
+sim_insts                                   880025277                       # Number of instructions simulated
+sim_ops                                    1621493925                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             58944                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1694720                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1753792                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        59072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           59072                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks       162752                       # Number of bytes written to this memory
-system.physmem.bytes_written::total            162752                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst                923                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total              1753664                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        58944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           58944                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks       163072                       # Number of bytes written to this memory
+system.physmem.bytes_written::total            163072                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst                921                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data              26480                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 27403                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks            2543                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                 2543                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst                92740                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              2660622                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 2753362                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst           92740                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total              92740                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            255512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 255512                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            255512                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst               92740                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             2660622                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3008874                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                 27401                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks            2548                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                 2548                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst                92545                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              2660791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 2753336                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst           92545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total              92545                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            256031                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 256031                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            256031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst               92545                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             2660791                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3009366                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1273927794                       # number of cpu cycles simulated
+system.cpu.numCycles                       1273846896                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                155476696                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          155476696                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           26665974                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              76215157                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 75849392                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                155381473                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          155381473                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           26661992                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              76481328                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 76085061                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          180766435                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1491872316                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   155476696                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           75849392                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     402325403                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                93614087                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              624018674                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  140                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          1031                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 185889439                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               8548075                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples         1273900868                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.002953                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.238276                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          180777781                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1491151373                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   155381473                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           76085061                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     402336644                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                93587210                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              623938160                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  145                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          1139                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 185942531                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               8615707                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples         1273819882                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.001935                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.237130                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                878792706     68.98%     68.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 24409433      1.92%     70.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 14960209      1.17%     72.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 18025508      1.41%     73.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 26731742      2.10%     75.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 18277101      1.43%     77.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 28493019      2.24%     79.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 39802935      3.12%     82.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                224408215     17.62%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                878702474     68.98%     68.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 24435713      1.92%     70.90% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 15105270      1.19%     72.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 18072889      1.42%     73.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 26727903      2.10%     75.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 18276740      1.43%     77.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 28604131      2.25%     79.28% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 39838610      3.13%     82.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                224056152     17.59%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total           1273900868                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.122045                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.171081                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                300130332                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             537055352                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 281851498                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              88074501                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               66789185                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2370363864                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               66789185                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                352614235                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles               124117956                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           1807                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 302560946                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             427816739                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2274265358                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents              293377579                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             103041568                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents              112                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          3464406080                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            7122244281                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       7122237233                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              7048                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            2493860970                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                970545110                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 88                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             88                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 745535849                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            545979333                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           222242756                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         352158228                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores        146951837                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2027253751                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                 556                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1785885865                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            143298                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       405620982                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1049961378                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved            506                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples    1273900868                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.401903                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.311945                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total           1273819882                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.121978                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.170589                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                300142098                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             537000439                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 281769365                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              88141967                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               66766013                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2369867389                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               66766013                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                352580189                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles               124109997                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           1918                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 302594361                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             427767404                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2274189452                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents              293406849                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             103032322                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents               51                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          3464260390                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            7121426016                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       7121418052                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              7964                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            2493860878                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                970399512                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 94                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             94                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 745525627                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            545851562                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           222235793                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         352099065                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores        146974262                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2027094513                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                 587                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1785918647                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            140586                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       405462466                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1049512028                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved            537                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples    1273819882                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.402018                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.312119                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           346798223     27.22%     27.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           447596849     35.14%     62.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           243149127     19.09%     81.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           151409869     11.89%     93.33% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            40759247      3.20%     96.53% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            32504128      2.55%     99.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             9931846      0.78%     99.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1400181      0.11%     99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              351398      0.03%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           346849812     27.23%     27.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           447400536     35.12%     62.35% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           243205365     19.09%     81.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           151321871     11.88%     93.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            40825213      3.20%     96.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            32566088      2.56%     99.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             9897563      0.78%     99.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1402374      0.11%     99.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              351060      0.03%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total      1273900868                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total      1273819882                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                  262837     10.20%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2136217     82.89%     93.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                178017      6.91%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                  260443     10.10%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     10.10% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2141420     83.03%     93.13% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                177309      6.87%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass          46812745      2.62%      2.62% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1067077874     59.75%     62.37% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass          46812744      2.62%      2.62% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1067089927     59.75%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     62.37% # Type of FU issued
@@ -194,158 +194,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     62.37% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     62.37% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     62.37% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            479524386     26.85%     89.22% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           192470860     10.78%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            479538721     26.85%     89.22% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           192477255     10.78%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1785885865                       # Type of FU issued
-system.cpu.iq.rate                           1.401874                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2577071                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.001443                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4848392282                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2433055974                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1727031567                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 685                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               2066                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses           68                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1741649976                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     215                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        208887212                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1785918647                       # Type of FU issued
+system.cpu.iq.rate                           1.401988                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2579172                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.001444                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4848376217                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2432738390                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1727118998                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                 717                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               2336                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses           76                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1741684846                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     229                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        208839211                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    126937208                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        36775                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       189921                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     34056699                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    126809441                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        36531                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       190384                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     34049736                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         2072                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           462                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         2138                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           453                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               66789185                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  397482                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                 85620                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2027254307                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts          63893728                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             545979333                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            222242756                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 83                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                  48032                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                   669                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         189921                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        2137684                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect     24653436                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             26791120                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1767797184                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             473889834                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          18088681                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               66766013                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  400873                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                 86074                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2027095100                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts          63749855                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             545851562                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            222235793                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 88                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                  48364                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                   665                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         190384                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        2138396                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect     24649145                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             26787541                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1767801211                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             473822669                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          18117436                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    665730625                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                109718993                       # Number of branches executed
-system.cpu.iew.exec_stores                  191840791                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.387675                       # Inst execution rate
-system.cpu.iew.wb_sent                     1728379028                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1727031635                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1262282896                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2985352291                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    665669278                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                109723805                       # Number of branches executed
+system.cpu.iew.exec_stores                  191846609                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.387766                       # Inst execution rate
+system.cpu.iew.wb_sent                     1728448502                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1727119074                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1262324846                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2985456049                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.355675                       # insts written-back per cycle
+system.cpu.iew.wb_rate                       1.355829                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.422825                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      880025312                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps       1621493982                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       405765098                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts      880025277                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1621493925                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       405606358                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          26666115                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples   1207111683                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.343284                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.660206                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          26662143                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples   1207053869                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.343348                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.659934                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    437166011     36.22%     36.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    432802967     35.85%     72.07% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     93484629      7.74%     79.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3    134841213     11.17%     90.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     35727207      2.96%     93.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     23483214      1.95%     95.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     25551681      2.12%     98.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      8874954      0.74%     98.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15179807      1.26%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    437041200     36.21%     36.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    432850092     35.86%     72.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     93447270      7.74%     79.81% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3    134928627     11.18%     90.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     35706636      2.96%     93.95% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     23539949      1.95%     95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     25505485      2.11%     98.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      8872667      0.74%     98.74% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15161943      1.26%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total   1207111683                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            880025312                       # Number of instructions committed
-system.cpu.commit.committedOps             1621493982                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total   1207053869                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            880025277                       # Number of instructions committed
+system.cpu.commit.committedOps             1621493925                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      607228182                       # Number of memory references committed
-system.cpu.commit.loads                     419042125                       # Number of loads committed
+system.cpu.commit.refs                      607228178                       # Number of memory references committed
+system.cpu.commit.loads                     419042121                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                  107161579                       # Number of branches committed
+system.cpu.commit.branches                  107161574                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1621354492                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1621354435                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15179807                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15161943                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   3219190956                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4121324121                       # The number of ROB writes
-system.cpu.timesIdled                             604                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           26926                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   880025312                       # Number of Instructions Simulated
-system.cpu.committedOps                    1621493982                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             880025312                       # Number of Instructions Simulated
-system.cpu.cpi                               1.447604                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.447604                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.690797                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.690797                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               4473882728                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2589957068                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                        68                       # number of floating regfile reads
-system.cpu.misc_regfile_reads               911502074                       # number of misc regfile reads
-system.cpu.icache.replacements                     17                       # number of replacements
-system.cpu.icache.tagsinuse                828.056964                       # Cycle average of tags in use
-system.cpu.icache.total_refs                185888078                       # Total number of references to valid blocks.
+system.cpu.rob.rob_reads                   3218992209                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4120983322                       # The number of ROB writes
+system.cpu.timesIdled                             600                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           27014                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   880025277                       # Number of Instructions Simulated
+system.cpu.committedOps                    1621493925                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             880025277                       # Number of Instructions Simulated
+system.cpu.cpi                               1.447512                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.447512                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.690841                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.690841                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4473913165                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2590095162                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                        76                       # number of floating regfile reads
+system.cpu.misc_regfile_reads               911461004                       # number of misc regfile reads
+system.cpu.icache.replacements                     22                       # number of replacements
+system.cpu.icache.tagsinuse                826.529270                       # Cycle average of tags in use
+system.cpu.icache.total_refs                185941160                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    930                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               199879.653763                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               199936.731183                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     828.056964                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.404325                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.404325                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    185888078                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       185888078                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     185888078                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        185888078                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    185888078                       # number of overall hits
-system.cpu.icache.overall_hits::total       185888078                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1361                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1361                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1361                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1361                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1361                       # number of overall misses
-system.cpu.icache.overall_misses::total          1361                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     47861000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     47861000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     47861000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     47861000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     47861000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     47861000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    185889439                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    185889439                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    185889439                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    185889439                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    185889439                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    185889439                       # number of overall (read+write) accesses
+system.cpu.icache.occ_blocks::cpu.inst     826.529270                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.403579                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.403579                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    185941162                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       185941162                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     185941162                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        185941162                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    185941162                       # number of overall hits
+system.cpu.icache.overall_hits::total       185941162                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1369                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1369                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1369                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1369                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1369                       # number of overall misses
+system.cpu.icache.overall_misses::total          1369                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     47914000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     47914000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     47914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     47914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     47914000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     47914000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    185942531                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    185942531                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    185942531                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    185942531                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    185942531                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    185942531                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000007                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000007                       # miss rate for demand accesses
 system.cpu.icache.demand_miss_rate::total     0.000007                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000007                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000007                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35166.054372                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35166.054372                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35166.054372                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35166.054372                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35166.054372                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35166.054372                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34999.269540                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 34999.269540                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34999.269540                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 34999.269540                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34999.269540                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 34999.269540                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -354,94 +354,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          431                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          431                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          431                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          431                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          431                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          431                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          930                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          930                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          930                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          930                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          930                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          930                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     34220000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     34220000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     34220000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     34220000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     34220000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     34220000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          435                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          435                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          435                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          435                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          435                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          435                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          934                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          934                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          934                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          934                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          934                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          934                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     34118000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     34118000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     34118000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     34118000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     34118000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     34118000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000005                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000005                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36795.698925                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36795.698925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36795.698925                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36795.698925                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36528.907923                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36528.907923                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36528.907923                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36528.907923                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36528.907923                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36528.907923                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                 445433                       # number of replacements
-system.cpu.dcache.tagsinuse               4093.428364                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                452731874                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                 449529                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1007.124955                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              738592000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4093.428364                       # Average occupied blocks per requestor
+system.cpu.dcache.replacements                 445452                       # number of replacements
+system.cpu.dcache.tagsinuse               4093.428018                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                452712586                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                 449548                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                1007.039484                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              738623000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4093.428018                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999372                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    264792027                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       264792027                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    187939847                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      187939847                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     452731874                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        452731874                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    452731874                       # number of overall hits
-system.cpu.dcache.overall_hits::total       452731874                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data       206669                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total        206669                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       246210                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       246210                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data       452879                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total         452879                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data       452879                       # number of overall misses
-system.cpu.dcache.overall_misses::total        452879                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1300622500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1300622500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   2040839000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   2040839000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   3341461500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   3341461500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   3341461500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   3341461500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    264998696                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    264998696                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::cpu.data    264772769                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       264772769                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    187939813                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      187939813                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     452712582                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        452712582                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    452712582                       # number of overall hits
+system.cpu.dcache.overall_hits::total       452712582                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       206710                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        206710                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       246244                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       246244                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       452954                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         452954                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       452954                       # number of overall misses
+system.cpu.dcache.overall_misses::total        452954                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1296370500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1296370500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   2046596000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   2046596000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   3342966500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   3342966500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   3342966500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   3342966500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    264979479                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    264979479                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    453184753                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    453184753                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    453184753                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    453184753                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    453165536                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    453165536                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    453165536                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    453165536                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000780                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000780                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001308                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.001308                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000999                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000999                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000999                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000999                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6293.263624                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  6293.263624                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8289.017505                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total  8289.017505                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  7378.265497                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  7378.265497                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  7378.265497                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  7378.265497                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001309                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.001309                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.001000                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.001000                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.001000                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.001000                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6271.445503                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  6271.445503                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data  8311.252254                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total  8311.252254                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  7380.366439                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  7380.366439                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  7380.366439                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  7380.366439                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -450,32 +450,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks       428496                       # number of writebacks
-system.cpu.dcache.writebacks::total            428496                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3328                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total         3328                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data           20                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total           20                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data         3348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total         3348                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data         3348                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total         3348                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203341                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total       203341                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246190                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       246190                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data       449531                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total       449531                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data       449531                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total       449531                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    607771500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total    607771500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1249776500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1249776500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1857548000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   1857548000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1857548000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   1857548000                       # number of overall MSHR miss cycles
+system.cpu.dcache.writebacks::writebacks       428527                       # number of writebacks
+system.cpu.dcache.writebacks::total            428527                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3377                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         3377                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           23                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           23                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         3400                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         3400                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         3400                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         3400                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       203333                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       203333                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       246221                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       246221                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       449554                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       449554                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       449554                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       449554                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    608060000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total    608060000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1250112000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1250112000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   1858172000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   1858172000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   1858172000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   1858172000                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000767                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000767                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001308                       # mshr miss rate for WriteReq accesses
@@ -484,98 +484,102 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000992
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000992                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000992                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000992                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2988.927467                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2988.927467                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5076.471425                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5076.471425                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4132.191106                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  4132.191106                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4132.191106                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  4132.191106                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2990.463919                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  2990.463919                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  5077.194878                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  5077.194878                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  4133.367738                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  4133.367738                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  4133.367738                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  4133.367738                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  2658                       # number of replacements
-system.cpu.l2cache.tagsinuse             22224.770293                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  517694                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 24236                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                 21.360538                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  2664                       # number of replacements
+system.cpu.l2cache.tagsinuse             22218.876300                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  517817                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 24235                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                 21.366495                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 20809.314009                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    737.283312                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    678.172973                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.635050                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.022500                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.020696                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.678246                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            7                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data       198771                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total         198778                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks       428496                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total       428496                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       224280                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       224280                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            7                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data       423051                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total          423058                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            7                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data       423051                       # number of overall hits
-system.cpu.l2cache.overall_hits::total         423058                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          923                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data         4558                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         5481                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data        21922                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total        21922                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          923                       # number of demand (read+write) misses
+system.cpu.l2cache.occ_blocks::writebacks 20808.584757                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    736.081009                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    674.210534                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.635028                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.022463                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.020575                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.678066                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            9                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       198770                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         198779                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       428527                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       428527                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       224300                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       224300                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            9                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       423070                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          423079                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            9                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       423070                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         423079                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          921                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         4549                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         5470                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        21931                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        21931                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          921                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data        26480                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         27403                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          923                       # number of overall misses
+system.cpu.l2cache.demand_misses::total         27401                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          921                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data        26480                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        27403                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32677500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data    156724000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    189401500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    752017500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    752017500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     32677500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    908741500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    941419000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     32677500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    908741500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    941419000                       # number of overall miss cycles
+system.cpu.l2cache.overall_misses::total        27401                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32620000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    157237500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    189857500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    752514000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    752514000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32620000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    909751500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    942371500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32620000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    909751500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    942371500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          930                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data       203329                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total       204259                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks       428496                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total       428496                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       246202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       246202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       203319                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       204249                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       428527                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       428527                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            4                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            4                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       246231                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       246231                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.inst          930                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data       449531                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total       450461                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       449550                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       450480                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.inst          930                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data       449531                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total       450461                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992473                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022417                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.026834                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089041                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.089041                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992473                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.058906                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.060833                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992473                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.058906                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.060833                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35403.575298                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34384.379114                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34556.011677                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34304.237752                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34304.237752                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35403.575298                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34318.032477                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34354.596212                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35403.575298                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34318.032477                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34354.596212                       # average overall miss latency
+system.cpu.l2cache.overall_accesses::cpu.data       449550                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       450480                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.990323                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.022374                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.026781                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.089067                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.089067                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.990323                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.058903                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.060826                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.990323                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.058903                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.060826                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35418.023887                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34565.289075                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34708.866545                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34312.799234                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34312.799234                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35418.023887                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34356.174471                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34391.865260                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35418.023887                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34356.174471                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34391.865260                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -584,52 +588,52 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks         2543                       # number of writebacks
-system.cpu.l2cache.writebacks::total             2543                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          923                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4558                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         5481                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21922                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total        21922                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          923                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.writebacks::writebacks         2548                       # number of writebacks
+system.cpu.l2cache.writebacks::total             2548                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          921                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         4549                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         5470                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        21931                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        21931                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          921                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data        26480                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        27403                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          923                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        27401                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          921                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data        26480                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        27403                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29745000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    141788500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    171533500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    679883500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    679883500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29745000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    821672000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    851417000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29745000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    821672000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    851417000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022417                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026834                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089041                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089041                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058906                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.060833                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992473                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058906                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.060833                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31107.612988                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31296.022624                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.753307                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.753307                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.909366                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31070.211291                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32226.435536                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.909366                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31070.211291                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::total        27401                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29694500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    141471000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    171165500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    680167500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    680167500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29694500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    821638500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    851333000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29694500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    821638500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    851333000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.990323                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.022374                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.026781                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.089067                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.089067                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.990323                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.058903                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.060826                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.990323                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.058903                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.060826                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.585233                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31099.362497                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31291.681901                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31013.975651                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31013.975651                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.585233                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31028.644260                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31069.413525                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.585233                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31028.644260                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31069.413525                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 6c78f711cf19e3e033695b86188b5da9eec6a630..6d1d261c959108a6f3f608ca1e63dc7f303a7e30 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index db4607fa4bd2af61bd08a47e60bbe3bb7b5358be..177dd7f453783122bbd5acefc355e4482ee91b7b 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:08:17
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:24:05
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 963992704000 because target called exit()
+Exiting @ tick 963992671000 because target called exit()
index 0e02ab2e6c24d4fd901791cad62050dbb95bdaa0..a463fb58916d0f957a05aa2fd84b53d065912b65 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.963993                       # Number of seconds simulated
-sim_ticks                                963992704000                       # Number of ticks simulated
-final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                963992671000                       # Number of ticks simulated
+final_tick                               963992671000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1254577                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2311626                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1374282564                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216676                       # Number of bytes of host memory used
-host_seconds                                   701.45                       # Real time elapsed on the host
-sim_insts                                   880025313                       # Number of instructions simulated
-sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst        9492133912                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        1842452913                       # Number of bytes read from this memory
-system.physmem.bytes_read::total          11334586825                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   9492133912                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      9492133912                       # Number of instructions bytes read from this memory
+host_inst_rate                                1263596                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2328243                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1384161146                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224820                       # Number of bytes of host memory used
+host_seconds                                   696.45                       # Real time elapsed on the host
+sim_insts                                   880025278                       # Number of instructions simulated
+sim_ops                                    1621493926                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        9492133560                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        1842452909                       # Number of bytes read from this memory
+system.physmem.bytes_read::total          11334586469                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   9492133560                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      9492133560                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      864451000                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         864451000                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         1186516739                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          419042125                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            1605558864                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst         1186516695                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          419042121                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1605558816                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         188186057                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            188186057                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           9846686466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1911272674                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11757959140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      9846686466                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         9846686466                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           896740189                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              896740189                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          9846686466                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2808012863                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            12654699330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           9846686438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1911272735                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11757959173                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      9846686438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         9846686438                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           896740220                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              896740220                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          9846686438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2808012955                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            12654699393                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       1927985409                       # number of cpu cycles simulated
+system.cpu.numCycles                       1927985343                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   880025313                       # Number of instructions committed
-system.cpu.committedOps                    1621493983                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.committedInsts                   880025278                       # Number of instructions committed
+system.cpu.committedOps                    1621493926                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1621354436                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_conditional_control_insts     99478856                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1621354436                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          5129484088                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         2493860970                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          5129483910                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2493860878                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     607228182                       # number of memory refs
-system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_mem_refs                     607228178                       # number of memory refs
+system.cpu.num_load_insts                   419042121                       # Number of load instructions
 system.cpu.num_store_insts                  188186057                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1927985409                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1927985343                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 2eec436ef922bfa279c5e35b61f2549580cf375b..05ff130e5a3a765a5fb8d45645b285cf7918d9ab 100644 (file)
@@ -179,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index d6878297d5a05b30ac1ddaa8986cbac986b618e9..371c8d53f616f6cf103d9fd51e7f1718dd0f5173 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 13:03:08
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:30:12
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -39,4 +39,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 1801979727000 because target called exit()
+Exiting @ tick 1801979679000 because target called exit()
index 79bdadab446f5764e5c3c7fd1d5998dd7862d240..12b9ffa3088781fb3a5b50ff2dab80ebf9216f18 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.801980                       # Number of seconds simulated
-sim_ticks                                1801979727000                       # Number of ticks simulated
-final_tick                               1801979727000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1801979679000                       # Number of ticks simulated
+final_tick                               1801979679000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 622629                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1147227                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1274922997                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228496                       # Number of bytes of host memory used
-host_seconds                                  1413.40                       # Real time elapsed on the host
-sim_insts                                   880025313                       # Number of instructions simulated
-sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 670221                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1234919                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1372375195                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233400                       # Number of bytes of host memory used
+host_seconds                                  1313.04                       # Real time elapsed on the host
+sim_insts                                   880025278                       # Number of instructions simulated
+sim_ops                                    1621493926                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             46208                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1682368                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1728576                       # Number of bytes read from this memory
@@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst               25643                       # To
 system.physmem.bw_total::cpu.data              933622                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                1048411                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   48                       # Number of system calls
-system.cpu.numCycles                       3603959454                       # number of cpu cycles simulated
+system.cpu.numCycles                       3603959358                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   880025313                       # Number of instructions committed
-system.cpu.committedOps                    1621493983                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
+system.cpu.committedInsts                   880025278                       # Number of instructions committed
+system.cpu.committedOps                    1621493926                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1621354436                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     99478861                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1621354493                       # number of integer instructions
+system.cpu.num_conditional_control_insts     99478856                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1621354436                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          5129484088                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         2493860970                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          5129483910                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         2493860878                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     607228182                       # number of memory refs
-system.cpu.num_load_insts                   419042125                       # Number of load instructions
+system.cpu.num_mem_refs                     607228178                       # number of memory refs
+system.cpu.num_load_insts                   419042121                       # Number of load instructions
 system.cpu.num_store_insts                  188186057                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3603959454                       # Number of busy cycles
+system.cpu.num_busy_cycles                 3603959358                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      4                       # number of replacements
-system.cpu.icache.tagsinuse                660.169533                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1186516018                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                660.169550                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1186515974                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               1643373.986150                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               1643373.925208                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     660.169533                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     660.169550                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.322348                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.322348                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst   1186516018                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1186516018                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1186516018                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1186516018                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1186516018                       # number of overall hits
-system.cpu.icache.overall_hits::total      1186516018                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst   1186515974                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1186515974                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1186515974                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1186515974                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1186515974                       # number of overall hits
+system.cpu.icache.overall_hits::total      1186515974                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           722                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     40521000
 system.cpu.icache.demand_miss_latency::total     40521000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     40521000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     40521000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1186516740                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1186516740                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1186516740                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1186516740                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1186516740                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1186516740                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1186516696                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1186516696                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1186516696                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1186516696                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1186516696                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1186516696                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000001                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53123.268698
 system.cpu.icache.overall_avg_mshr_miss_latency::total 53123.268698                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 437952                       # number of replacements
-system.cpu.dcache.tagsinuse               4094.884021                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                606786134                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4094.884130                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                606786130                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                1372.670239                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              788858000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4094.884021                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                1372.670230                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              788810000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4094.884130                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.999728                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.999728                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    418844799                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       418844799                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    418844795                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       418844795                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    187941335                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      187941335                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     606786134                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        606786134                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    606786134                       # number of overall hits
-system.cpu.dcache.overall_hits::total       606786134                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     606786130                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        606786130                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    606786130                       # number of overall hits
+system.cpu.dcache.overall_hits::total       606786130                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       197326                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        197326                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       244722                       # number of WriteReq misses
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data   7311185000
 system.cpu.dcache.demand_miss_latency::total   7311185000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data   7311185000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total   7311185000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    419042125                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    419042125                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data    419042121                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    419042121                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    607228182                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    607228182                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    607228182                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    607228182                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    607228178                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    607228178                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    607228178                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    607228178                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000471                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000471                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001300                       # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13539.346406
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 13539.346406                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  2581                       # number of replacements
-system.cpu.l2cache.tagsinuse             22161.849584                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             22161.850174                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  506758                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 23832                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 21.263763                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21018.400125                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    596.832039                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    546.617420                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 21018.400685                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    596.832055                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    546.617434                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.641431                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.018214                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.016681                       # Average percentage of cache occupancy
index a0039b696491a8a83765bb17d6ee98272e5ad987..771a85baa5706a1f1a2482b65bdad60387e611e5 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index c071d26fa30feac72d89a9410eb62a9f1e5320a5..fddfdedb3fb5f0291ebb535e182137c16885d462 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:53:37
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:50
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 122215830000 because target called exit()
+Exiting @ tick 122215823500 because target called exit()
index 804f585d614445c7af19e12029cfe5254bc95438..7dd162db7cc33cfc70d59e02a34b6ee98b577833 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.122216                       # Number of seconds simulated
-sim_ticks                                122215830000                       # Number of ticks simulated
-final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                122215823500                       # Number of ticks simulated
+final_tick                               122215823500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2951739                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2951861                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1479540198                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346528                       # Number of bytes of host memory used
-host_seconds                                    82.60                       # Real time elapsed on the host
-sim_insts                                   243825163                       # Number of instructions simulated
-sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst         977686044                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         328674009                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1306360053                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    977686044                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       977686044                       # Number of instructions bytes read from this memory
+host_inst_rate                                2900370                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2900489                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1453791405                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 355144                       # Number of bytes of host memory used
+host_seconds                                    84.07                       # Real time elapsed on the host
+sim_insts                                   243825150                       # Number of instructions simulated
+sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         977685992                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         328674008                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1306360000                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    977685992                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       977685992                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data       91606089                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          91606089                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          244421511                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           82220434                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             326641945                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          244421498                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           82220433                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             326641931                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          22901951                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             22901951                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data               3886                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                  3886                       # Number of other requests responded to by this memory
 system.physmem.bw_read::cpu.inst           7999667834                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2689291633                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10688959466                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2689291768                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10688959601                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst      7999667834                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total         7999667834                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           749543566                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              749543566                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           749543606                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              749543606                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst          7999667834                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3438835198                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11438503032                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3438835373                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11438503207                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
+system.cpu.numCycles                        244431648                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   243825163                       # Number of instructions committed
-system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.committedInsts                   243825150                       # Number of instructions committed
+system.cpu.committedOps                     243835265                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             194726494                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
 system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_conditional_control_insts     18619959                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726494                       # number of integer instructions
 system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451567                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           456818988                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451554                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711442                       # number of memory refs
-system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_mem_refs                     105711441                       # number of memory refs
+system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  244431661                       # Number of busy cycles
+system.cpu.num_busy_cycles                  244431648                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 2ba8ced6e29ac0063a2e297937aa2e4ea1fe0899..22dd9c24ea51e75d9bd1fd23f32656eb7d510537 100644 (file)
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index f34d81d2694dfe2837dd75f2d299477fa9b3478c..869cdf52451217b19c2837717c550e4c859c904c 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:31:43
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:15:25
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 362481577000 because target called exit()
+Exiting @ tick 362481563000 because target called exit()
index 5f77178bca5766fa477c38b744befa8d721cd7aa..44702e46fbd0c18ec56f435caa8ae8c9725fe350 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.362482                       # Number of seconds simulated
-sim_ticks                                362481577000                       # Number of ticks simulated
-final_tick                               362481577000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                362481563000                       # Number of ticks simulated
+final_tick                               362481563000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1217197                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1217247                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1809539933                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 354248                       # Number of bytes of host memory used
-host_seconds                                   200.32                       # Real time elapsed on the host
-sim_insts                                   243825163                       # Number of instructions simulated
-sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1415125                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1415183                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2103788292                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 363728                       # Number of bytes of host memory used
+host_seconds                                   172.30                       # Real time elapsed on the host
+sim_insts                                   243825150                       # Number of instructions simulated
+sim_ops                                     243835265                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             56256                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            942336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               998592                       # Number of bytes read from this memory
@@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst              155197                       # To
 system.physmem.bw_total::cpu.data             2599680                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                2754877                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  443                       # Number of system calls
-system.cpu.numCycles                        724963154                       # number of cpu cycles simulated
+system.cpu.numCycles                        724963126                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   243825163                       # Number of instructions committed
-system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
+system.cpu.committedInsts                   243825150                       # Number of instructions committed
+system.cpu.committedOps                     243835265                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             194726494                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
 system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18619960                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    194726506                       # number of integer instructions
+system.cpu.num_conditional_control_insts     18619959                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    194726494                       # number of integer instructions
 system.cpu.num_fp_insts                         11630                       # number of float instructions
-system.cpu.num_int_register_reads           456819010                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          215451566                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           456818988                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          215451553                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                23256                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  90                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     105711442                       # number of memory refs
-system.cpu.num_load_insts                    82803522                       # Number of load instructions
+system.cpu.num_mem_refs                     105711441                       # number of memory refs
+system.cpu.num_load_insts                    82803521                       # Number of load instructions
 system.cpu.num_store_insts                   22907920                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  724963154                       # Number of busy cycles
+system.cpu.num_busy_cycles                  724963126                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     25                       # number of replacements
-system.cpu.icache.tagsinuse                725.564686                       # Cycle average of tags in use
-system.cpu.icache.total_refs                244420630                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                725.564713                       # Cycle average of tags in use
+system.cpu.icache.total_refs                244420617                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               277120.880952                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     725.564686                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     725.564713                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.354280                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.354280                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        244420630                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    244420630                       # number of overall hits
-system.cpu.icache.overall_hits::total       244420630                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    244420617                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       244420617                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     244420617                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        244420617                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    244420617                       # number of overall hits
+system.cpu.icache.overall_hits::total       244420617                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          882                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           882                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          882                       # number of demand (read+write) misses
@@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     49333000
 system.cpu.icache.demand_miss_latency::total     49333000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     49333000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     49333000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    244421512                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    244421512                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    244421499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244421499                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244421499                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244421499                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244421499                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244421499                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
@@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52933.106576
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52933.106576                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 935475                       # number of replacements
-system.cpu.dcache.tagsinuse               3563.804804                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                104186700                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               3563.804941                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                104186699                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           134384281000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    3563.804804                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                 110.887521                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           134384267000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    3563.804941                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.870070                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.870070                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     81327576                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81327576                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       22855241                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data         3882                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total            3882                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data     104182818                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        104182818                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    104182818                       # number of overall hits
-system.cpu.dcache.overall_hits::total       104182818                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     104182817                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        104182817                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    104182817                       # number of overall hits
+system.cpu.dcache.overall_hits::total       104182817                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       892857                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        892857                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data        46710                       # number of WriteReq misses
@@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data  13778134000
 system.cpu.dcache.demand_miss_latency::total  13778134000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  13778134000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  13778134000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     82220433                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82220433                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     22901951                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data         3886                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total         3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    105122384                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    105122384                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    105122384                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    105122384                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.010859                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002040                       # miss rate for WriteReq accesses
@@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11664.344320
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11664.344320                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              9744.633089                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              9744.633464                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 1813121                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 15586                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                116.330104                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks  8861.504688                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    738.799807                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    144.328594                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks  8861.505031                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    738.799835                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    144.328599                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.270432                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.022546                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004405                       # Average percentage of cache occupancy
index 02825e2f467d7ba5165b1155f9b15a24d861370e..c43765666fbfd336c3492de76519210682e04777 100644 (file)
@@ -510,7 +510,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -533,7 +533,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index dec2c9148fd97807c2fda07a68b920addc1e96e3..29d21ef4520a5c397e7e020b4df095a3af8987de 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 13:12:36
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:35:52
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,6 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-Exiting @ tick 68340167000 because target called exit()
+Exiting @ tick 68408131000 because target called exit()
index 4e7a26f1217e88832e1bf6a2ae7c21797a6e2160..740e607ea2ffbcc02729c36d3ce0f1ff329cf768 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.068340                       # Number of seconds simulated
-sim_ticks                                 68340167000                       # Number of ticks simulated
-final_tick                                68340167000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.068408                       # Number of seconds simulated
+sim_ticks                                 68408131000                       # Number of ticks simulated
+final_tick                                68408131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107513                       # Simulator instruction rate (inst/s)
-host_op_rate                                   189313                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               46506224                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 365660                       # Number of bytes of host memory used
-host_seconds                                  1469.48                       # Real time elapsed on the host
-sim_insts                                   157988582                       # Number of instructions simulated
-sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             68608                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data           1893120                       # Number of bytes read from this memory
-system.physmem.bytes_read::total              1961728                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        68608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           68608                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks        20288                       # Number of bytes written to this memory
-system.physmem.bytes_written::total             20288                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               1072                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data              29580                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 30652                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks             317                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total                  317                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              1003919                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             27701425                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                28705344                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         1003919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            1003919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks            296868                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total                 296868                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks            296868                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             1003919                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            27701425                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               29002212                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                  92617                       # Simulator instruction rate (inst/s)
+host_op_rate                                   163083                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               40102422                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 370556                       # Number of bytes of host memory used
+host_seconds                                  1705.84                       # Real time elapsed on the host
+sim_insts                                   157988547                       # Number of instructions simulated
+sim_ops                                     278192462                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             68352                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           1892736                       # Number of bytes read from this memory
+system.physmem.bytes_read::total              1961088                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        68352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           68352                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks        20352                       # Number of bytes written to this memory
+system.physmem.bytes_written::total             20352                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               1068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data              29574                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 30642                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks             318                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total                  318                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               999179                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             27668290                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                28667469                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          999179                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             999179                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks            297508                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total                 297508                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks            297508                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              999179                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            27668290                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               28964978                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        136680335                       # number of cpu cycles simulated
+system.cpu.numCycles                        136816263                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 36129289                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           36129289                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            1086629                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              25668657                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 25566381                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 36128371                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           36128371                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            1086051                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              25676514                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 25568930                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           28038648                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      196448149                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    36129289                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           25566381                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59446336                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                 8437809                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               41835148                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   32                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           182                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  27320717                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                151811                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          136641889                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.527241                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.343736                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           28040484                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      196465722                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    36128371                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           25568930                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59455138                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                 8440333                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               41957570                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   37                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           207                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  27323760                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                153045                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          136778320                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.524833                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.343005                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                 79944033     58.51%     58.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  2167208      1.59%     60.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2997757      2.19%     62.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  4111297      3.01%     65.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  8027988      5.88%     71.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  5053640      3.70%     74.87% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  2897429      2.12%     76.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  1474644      1.08%     78.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 29967893     21.93%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                 80075177     58.54%     58.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  2168654      1.59%     60.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2999031      2.19%     62.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  4111689      3.01%     65.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  8029506      5.87%     71.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  5053851      3.69%     74.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  2898853      2.12%     77.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  1472297      1.08%     78.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 29969262     21.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            136641889                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.264334                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.437282                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40756149                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              32464330                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46271327                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles               9828540                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                7321543                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              341364323                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                7321543                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 46061495                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                 6368629                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles           8995                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  50367831                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              26513396                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              337564097                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    23                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                   5026                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              24245573                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            73928                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           414895608                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1010438546                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1010435932                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups              2614                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             341010940                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                 73884668                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                483                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts            475                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  57387793                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            108215751                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            37227533                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          46388866                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores          7855106                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  331925513                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                2461                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 311467723                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            186069                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined        53480941                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined     93052835                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           2015                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     136641889                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.279445                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.722907                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            136778320                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.264065                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.435982                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40775641                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              32574420                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46270758                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles               9832617                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                7324884                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              341365831                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                7324884                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 46092133                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                 6411510                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles           9224                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  50365166                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              26575403                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              337580749                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    29                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents                   5005                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              24325640                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            73870                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           414916926                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1010481124                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1010477953                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups              3171                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             341010848                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                 73906078                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                481                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts            476                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  57495301                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            108229908                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            37227556                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          46399442                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores          8017088                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  331952532                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                2380                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 311468511                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            188619                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined        53509766                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined     93151802                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           1934                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     136778320                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.277177                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.722818                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            29493706     21.58%     21.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            18268502     13.37%     34.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            26067174     19.08%     54.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            31248056     22.87%     76.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            17426975     12.75%     89.65% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             8824728      6.46%     96.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             3769643      2.76%     98.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             1473533      1.08%     99.95% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8               69572      0.05%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            29621399     21.66%     21.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            18208303     13.31%     34.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            26183268     19.14%     54.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            31189173     22.80%     76.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            17472478     12.77%     89.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             8789771      6.43%     96.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             3781191      2.76%     98.88% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             1461656      1.07%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8               71081      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       136641889                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       136778320                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   22788      1.09%      1.09% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   22736      1.09%      1.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      1.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntDiv                       0      0.00%      1.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::FloatAdd                     0      0.00%      1.09% # attempts to use FU when none available
@@ -160,15 +160,15 @@ system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      1.09% # at
 system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      1.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      1.09% # attempts to use FU when none available
 system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      1.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                1944579     92.77%     93.86% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                128653      6.14%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                1942986     92.77%     93.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                128630      6.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass             29247      0.01%      0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             177257579     56.91%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             177262228     56.91%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     56.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                 116      0.00%     56.92% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                 143      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     56.92% # Type of FU issued
@@ -194,159 +194,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     56.92% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     56.92% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     56.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             99693088     32.01%     88.93% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            34487693     11.07%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             99693377     32.01%     88.93% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            34483516     11.07%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              311467723                       # Type of FU issued
-system.cpu.iq.rate                           2.278804                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2096020                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.006729                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          761858485                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         385440526                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    308377955                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                 939                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes               1362                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          296                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              313534078                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                     418                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         52563213                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              311468511                       # Type of FU issued
+system.cpu.iq.rate                           2.276546                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2094352                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.006724                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          761997211                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         385495678                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    308386892                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                1102                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes               1693                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          371                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              313533109                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                     507                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         52559129                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     17436363                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        94862                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation        33518                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores      5787782                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     17450524                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        94828                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation        33225                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores      5787805                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         3294                       # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked           766                       # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads         3313                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked           747                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                7321543                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  823106                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                106434                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           331927974                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts             49382                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             108215751                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             37227533                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                475                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                   1169                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 29139                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents          33518                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         614396                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect       578149                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1192545                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             309546199                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              99164124                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           1921524                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles                7324884                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  821379                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                106718                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           331954912                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts             49233                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             108229908                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             37227556                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                477                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                   1080                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 29147                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents          33225                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect         614391                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect       577456                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              1191847                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             309549319                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              99164391                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           1919192                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    133270548                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 31554842                       # Number of branches executed
-system.cpu.iew.exec_stores                   34106424                       # Number of stores executed
-system.cpu.iew.exec_rate                     2.264746                       # Inst execution rate
-system.cpu.iew.wb_sent                      308908711                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     308378251                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 227159905                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 466461304                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    133267604                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 31551799                       # Number of branches executed
+system.cpu.iew.exec_stores                   34103213                       # Number of stores executed
+system.cpu.iew.exec_rate                     2.262518                       # Inst execution rate
+system.cpu.iew.wb_sent                      308913193                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     308387263                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 227149501                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 466434365                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       2.256201                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.486986                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       2.254025                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.486991                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts        53739498                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts      157988547                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        278192462                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts        53766564                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           1086653                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    129320346                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     2.151189                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.664667                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           1086077                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    129453436                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     2.148977                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.662392                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     48978430     37.87%     37.87% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     24328173     18.81%     56.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     16731567     12.94%     69.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12545678      9.70%     79.33% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      3454921      2.67%     82.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      3553253      2.75%     84.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2757236      2.13%     86.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1133891      0.88%     87.75% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     15837197     12.25%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     48953386     37.82%     37.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     24330343     18.79%     56.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     17047293     13.17%     69.78% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12542277      9.69%     79.47% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      3298814      2.55%     82.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      3552746      2.74%     84.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2756547      2.13%     86.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1133806      0.88%     87.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     15838224     12.23%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    129320346                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
-system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    129453436                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            157988547                       # Number of instructions committed
+system.cpu.commit.committedOps              278192462                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      122219139                       # Number of memory references committed
-system.cpu.commit.loads                      90779388                       # Number of loads committed
+system.cpu.commit.refs                      122219135                       # Number of memory references committed
+system.cpu.commit.loads                      90779384                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                   29309710                       # Number of branches committed
+system.cpu.commit.branches                   29309705                       # Number of branches committed
 system.cpu.commit.fp_insts                         40                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 278186227                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 278186170                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              15837197                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              15838224                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    445415166                       # The number of ROB reads
-system.cpu.rob.rob_writes                   671194708                       # The number of ROB writes
-system.cpu.timesIdled                            2012                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           38446                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
-system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
-system.cpu.cpi                               0.865128                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.865128                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.155898                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.155898                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                705405399                       # number of integer regfile reads
-system.cpu.int_regfile_writes               373270395                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       345                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                      188                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               197984504                       # number of misc regfile reads
-system.cpu.icache.replacements                     90                       # number of replacements
-system.cpu.icache.tagsinuse                845.686115                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 27319306                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   1079                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25319.097312                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                    445574238                       # The number of ROB reads
+system.cpu.rob.rob_writes                   671251501                       # The number of ROB writes
+system.cpu.timesIdled                            1985                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           37943                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   157988547                       # Number of Instructions Simulated
+system.cpu.committedOps                     278192462                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             157988547                       # Number of Instructions Simulated
+system.cpu.cpi                               0.865988                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.865988                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.154750                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.154750                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                705392602                       # number of integer regfile reads
+system.cpu.int_regfile_writes               373276329                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       441                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                      230                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               197984249                       # number of misc regfile reads
+system.cpu.icache.replacements                     87                       # number of replacements
+system.cpu.icache.tagsinuse                844.199846                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 27322358                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   1076                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               25392.526022                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     845.686115                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.412933                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.412933                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     27319307                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        27319307                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      27319307                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         27319307                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     27319307                       # number of overall hits
-system.cpu.icache.overall_hits::total        27319307                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         1410                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          1410                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         1410                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           1410                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         1410                       # number of overall misses
-system.cpu.icache.overall_misses::total          1410                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     52106500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     52106500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     52106500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     52106500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     52106500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     52106500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     27320717                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     27320717                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     27320717                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     27320717                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     27320717                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     27320717                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000052                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000052                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000052                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000052                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000052                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36954.964539                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36954.964539                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36954.964539                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36954.964539                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36954.964539                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36954.964539                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     844.199846                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.412207                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.412207                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     27322358                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27322358                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27322358                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27322358                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27322358                       # number of overall hits
+system.cpu.icache.overall_hits::total        27322358                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1402                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1402                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1402                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1402                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1402                       # number of overall misses
+system.cpu.icache.overall_misses::total          1402                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     51713500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     51713500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     51713500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     51713500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     51713500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     51713500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27323760                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27323760                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27323760                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27323760                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27323760                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27323760                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000051                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000051                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000051                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000051                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000051                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000051                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36885.520685                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36885.520685                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36885.520685                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36885.520685                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36885.520685                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36885.520685                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -355,94 +355,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          328                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          328                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          328                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          328                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          328                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          328                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1082                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         1082                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         1082                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         1082                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         1082                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         1082                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     39682000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     39682000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     39682000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     39682000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     39682000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     39682000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000040                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000040                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000040                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36674.676525                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36674.676525                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36674.676525                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36674.676525                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          325                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          325                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          325                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          325                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          325                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          325                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1077                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1077                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1077                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1077                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1077                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1077                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     39505500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     39505500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     39505500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     39505500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     39505500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     39505500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000039                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000039                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000039                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000039                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36681.058496                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36681.058496                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36681.058496                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36681.058496                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36681.058496                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36681.058496                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2072150                       # number of replacements
-system.cpu.dcache.tagsinuse               4072.380318                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 75593684                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2076246                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  36.408828                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            22734551000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4072.380318                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.994233                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.994233                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     44236411                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        44236411                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     31357262                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       31357262                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      75593673                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         75593673                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     75593673                       # number of overall hits
-system.cpu.dcache.overall_hits::total        75593673                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2315078                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2315078                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data        82489                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total        82489                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      2397567                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        2397567                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      2397567                       # number of overall misses
-system.cpu.dcache.overall_misses::total       2397567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  16784018500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  16784018500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data   1571310000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total   1571310000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  18355328500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  18355328500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  18355328500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  18355328500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     46551489                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     46551489                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2072121                       # number of replacements
+system.cpu.dcache.tagsinuse               4072.371520                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 75597840                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2076217                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  36.411339                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle            22802887000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4072.371520                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994231                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994231                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     44240568                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        44240568                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31357263                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31357263                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      75597831                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         75597831                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     75597831                       # number of overall hits
+system.cpu.dcache.overall_hits::total        75597831                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2315103                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2315103                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        82488                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        82488                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2397591                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2397591                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2397591                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2397591                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  16770812000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  16770812000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1571570000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1571570000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  18342382000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  18342382000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  18342382000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  18342382000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     46555671                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     46555671                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     77991240                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     77991240                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     77991240                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     77991240                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049732                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.049732                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data     77995422                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     77995422                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     77995422                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     77995422                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.049728                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.049728                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002624                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.002624                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.030741                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.030741                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.030741                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.030741                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7249.871711                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total  7249.871711                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19048.721648                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 19048.721648                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data  7655.814624                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total  7655.814624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data  7655.814624                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total  7655.814624                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.030740                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.030740                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.030740                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.030740                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  7244.088924                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total  7244.088924                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19052.104549                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 19052.104549                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  7650.338194                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total  7650.338194                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  7650.338194                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total  7650.338194                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -451,140 +451,138 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2064802                       # number of writebacks
-system.cpu.dcache.writebacks::total           2064802                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       320846                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       320846                       # number of ReadReq MSHR hits
+system.cpu.dcache.writebacks::writebacks      2065063                       # number of writebacks
+system.cpu.dcache.writebacks::total           2065063                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       320901                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       320901                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          469                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          469                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       321315                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       321315                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       321315                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       321315                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994232                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1994232                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82020                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total        82020                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2076252                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2076252                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2076252                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2076252                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6184007000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   6184007000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1313707000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total   1313707000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7497714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   7497714000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7497714000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   7497714000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042839                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042839                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_hits::cpu.data       321370                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       321370                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       321370                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       321370                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994202                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994202                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82019                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82019                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2076221                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2076221                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2076221                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2076221                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6183631000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6183631000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1313937000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1313937000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7497568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   7497568000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7497568000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7497568000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042835                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042835                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002609                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002609                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026622                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.026622                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026622                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.026622                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3100.946630                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3100.946630                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16016.910510                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16016.910510                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3611.177256                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total  3611.177256                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3611.177256                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total  3611.177256                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026620                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.026620                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026620                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.026620                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  3100.804733                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  3100.804733                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16019.910021                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16019.910021                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3611.160854                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total  3611.160854                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3611.160854                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total  3611.160854                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                  1468                       # number of replacements
-system.cpu.l2cache.tagsinuse             20085.228280                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 4027172                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                 30631                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                131.473736                       # Average number of references to valid blocks.
+system.cpu.l2cache.replacements                  1458                       # number of replacements
+system.cpu.l2cache.tagsinuse             20067.979072                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 4027415                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                 30622                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                131.520312                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19589.019970                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    262.767533                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    233.440777                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.597809                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.008019                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.007124                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.612953                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst            7                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1993528                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1993535                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2064802                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2064802                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data            1                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total            1                       # number of UpgradeReq hits
+system.cpu.l2cache.occ_blocks::writebacks 19572.608886                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    263.032470                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    232.337716                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.597309                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.008027                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.007090                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.612426                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            8                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1993505                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1993513                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2065063                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2065063                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data        53141                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total        53141                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst            7                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2046669                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2046676                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst            7                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2046669                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2046676                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         1072                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          588                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         1660                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data            2                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total            2                       # number of UpgradeReq misses
+system.cpu.l2cache.demand_hits::cpu.inst            8                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2046646                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2046654                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            8                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2046646                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2046654                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1068                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          582                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1650                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data        28992                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total        28992                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         1072                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data        29580                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total         30652                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         1072                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data        29580                       # number of overall misses
-system.cpu.l2cache.overall_misses::total        30652                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     38191500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20878500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     59070000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    989300500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total    989300500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     38191500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data   1010179000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total   1048370500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     38191500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data   1010179000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total   1048370500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         1079                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data      1994116                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1995195                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2064802                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2064802                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data            3                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total            3                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.demand_misses::cpu.inst         1068                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        29574                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         30642                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1068                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        29574                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        30642                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     37986000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     20700500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     58686500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    989313000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    989313000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     37986000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   1010013500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   1047999500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     37986000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   1010013500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   1047999500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1076                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994087                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995163                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2065063                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2065063                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data        82133                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total        82133                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         1079                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2076249                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2077328                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         1079                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2076249                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2077328                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993513                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000295                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.000832                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.666667                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.666667                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.demand_accesses::cpu.inst         1076                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2076220                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2077296                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1076                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2076220                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2077296                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992565                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000292                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.000827                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.352988                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total     0.352988                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993513                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.014247                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.014755                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993513                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.014247                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.014755                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35626.399254                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35507.653061                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35584.337349                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.223648                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.223648                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35626.399254                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.743746                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34202.352212                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35626.399254                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.743746                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34202.352212                       # average overall miss latency
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992565                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.014244                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.014751                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992565                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.014244                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.014751                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35567.415730                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35567.869416                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35567.575758                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34123.654801                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34123.654801                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35567.415730                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34152.076148                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34201.406566                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35567.415730                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34152.076148                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34201.406566                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -593,60 +591,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks          317                       # number of writebacks
-system.cpu.l2cache.writebacks::total              317                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1072                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          588                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         1660                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            2                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total            2                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.writebacks::writebacks          318                       # number of writebacks
+system.cpu.l2cache.writebacks::total              318                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1068                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          582                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1650                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        28992                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total        28992                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         1072                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data        29580                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total        30652                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         1072                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data        29580                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total        30652                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34797000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     19023000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     53820000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        62000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        62000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    899044500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    899044500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34797000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    918067500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    952864500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34797000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    918067500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    952864500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000295                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000832                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.666667                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.666667                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1068                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        29574                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        30642                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1068                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        29574                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        30642                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34610000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     18859500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     53469500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    899045000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    899045000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34610000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    917904500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    952514500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34610000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    917904500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    952514500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992565                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000292                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.000827                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.352988                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.352988                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014247                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.014755                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993513                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014247                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.014755                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32352.040816                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32421.686747                       # average ReadReq mshr miss latency
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992565                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.014244                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.014751                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992565                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.014244                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.014751                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32406.367041                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32404.639175                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32405.757576                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.088990                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.088990                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31036.764706                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31086.535952                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32459.888060                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31036.764706                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31086.535952                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.106236                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.106236                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32406.367041                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31037.549875                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31085.258795                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32406.367041                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31037.549875                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31085.258795                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3fd88efc27ff981a93d3f637b1ebdc47d4f5f168..2bc190729fdb634fc0b53216b97e62ebb1ca4d28 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index 9f1b85cdf1040b101dc788267bd78dd9ccd5c7f1..36c1a507af4fd6437edc3c0f00f0aa202d97f4f2 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:20:09
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:40:35
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 168950072000 because target called exit()
+Exiting @ tick 168950039000 because target called exit()
index 75d2c32b929147fbca5a5fb010a08abcc7403e1d..624b796e91c7d6ff5907ad5fa90a846cac0477be 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.168950                       # Number of seconds simulated
-sim_ticks                                168950072000                       # Number of ticks simulated
-final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                168950039000                       # Number of ticks simulated
+final_tick                               168950039000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1244063                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2190595                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1330377575                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351912                       # Number of bytes of host memory used
-host_seconds                                   126.99                       # Real time elapsed on the host
-sim_insts                                   157988583                       # Number of instructions simulated
-sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst        1741569664                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         717246015                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           2458815679                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1741569664                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1741569664                       # Number of instructions bytes read from this memory
+host_inst_rate                                1227990                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2162293                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1313189467                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 359036                       # Number of bytes of host memory used
+host_seconds                                   128.66                       # Real time elapsed on the host
+sim_insts                                   157988548                       # Number of instructions simulated
+sim_ops                                     278192463                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        1741569312                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         717246011                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           2458815323                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1741569312                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1741569312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      243173115                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         243173115                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          217696208                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           90779450                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             308475658                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          217696164                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           90779446                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             308475610                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          31439751                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             31439751                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          10308191310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           4245313462                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             14553504772                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     10308191310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        10308191310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1439319393                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1439319393                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         10308191310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          5684632854                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            15992824164                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst          10308191240                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           4245314267                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             14553505507                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst     10308191240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total        10308191240                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1439319674                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1439319674                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst         10308191240                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          5684633941                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            15992825181                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
+system.cpu.numCycles                        337900079                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   157988583                       # Number of instructions committed
-system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.committedInsts                   157988548                       # Number of instructions committed
+system.cpu.committedOps                     278192463                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             278186171                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186171                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           834011910                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           834011732                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010822                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     122219139                       # number of memory refs
-system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_mem_refs                     122219135                       # number of memory refs
+system.cpu.num_load_insts                    90779384                       # Number of load instructions
 system.cpu.num_store_insts                   31439751                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  337900145                       # Number of busy cycles
+system.cpu.num_busy_cycles                  337900079                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 44c2b2c0ac78ec84ea0ee5126bf10c36ab7160aa..fb9534d75e63ea91f6c06cba2ccc186930134a66 100644 (file)
@@ -179,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 85144f91b9e20b55fc665afde13caff0552708b3..25187946ee46c08709c175ccbd87c4e6d660e9d5 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 13:28:56
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:42:54
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +23,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 368209254000 because target called exit()
+Exiting @ tick 368209206000 because target called exit()
index cca34d6d035e9b9eba5340fe80914010dede1a83..be2824a9dc1eb97010a629c166076ca44b3dc479 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.368209                       # Number of seconds simulated
-sim_ticks                                368209254000                       # Number of ticks simulated
-final_tick                               368209254000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                368209206000                       # Number of ticks simulated
+final_tick                               368209206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 606195                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1067413                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1412802854                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 363612                       # Number of bytes of host memory used
-host_seconds                                   260.62                       # Real time elapsed on the host
-sim_insts                                   157988583                       # Number of instructions simulated
-sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 651126                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1146527                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1517517563                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 367484                       # Number of bytes of host memory used
+host_seconds                                   242.64                       # Real time elapsed on the host
+sim_insts                                   157988548                       # Number of instructions simulated
+sim_ops                                     278192463                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             51712                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           1879680                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              1931392                       # Number of bytes read from this memory
@@ -24,54 +24,54 @@ system.physmem.num_reads::total                 30178                       # Nu
 system.physmem.num_writes::writebacks             227                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  227                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst               140442                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              5104923                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 5245365                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              5104924                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 5245366                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          140442                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             140442                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks             39456                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total                  39456                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks             39456                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst              140442                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             5104923                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                5284821                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             5104924                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                5284822                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  444                       # Number of system calls
-system.cpu.numCycles                        736418508                       # number of cpu cycles simulated
+system.cpu.numCycles                        736418412                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   157988583                       # Number of instructions committed
-system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
+system.cpu.committedInsts                   157988548                       # Number of instructions committed
+system.cpu.committedOps                     278192463                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             278186171                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     18628012                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    278186228                       # number of integer instructions
+system.cpu.num_conditional_control_insts     18628007                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    278186171                       # number of integer instructions
 system.cpu.num_fp_insts                            40                       # number of float instructions
-system.cpu.num_int_register_reads           834011910                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          341010914                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           834011732                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          341010822                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   40                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                  26                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     122219139                       # number of memory refs
-system.cpu.num_load_insts                    90779388                       # Number of load instructions
+system.cpu.num_mem_refs                     122219135                       # number of memory refs
+system.cpu.num_load_insts                    90779384                       # Number of load instructions
 system.cpu.num_store_insts                   31439751                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  736418508                       # Number of busy cycles
+system.cpu.num_busy_cycles                  736418412                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     24                       # number of replacements
-system.cpu.icache.tagsinuse                665.897663                       # Cycle average of tags in use
-system.cpu.icache.total_refs                217695401                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                665.897748                       # Cycle average of tags in use
+system.cpu.icache.total_refs                217695357                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               269424.946782                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     665.897663                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     665.897748                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.325145                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.325145                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    217695401                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       217695401                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     217695401                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        217695401                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    217695401                       # number of overall hits
-system.cpu.icache.overall_hits::total       217695401                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    217695357                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       217695357                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     217695357                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        217695357                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    217695357                       # number of overall hits
+system.cpu.icache.overall_hits::total       217695357                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           808                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     45336000
 system.cpu.icache.demand_miss_latency::total     45336000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     45336000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     45336000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    217696209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    217696209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    217696209                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    217696209                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    217696209                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    217696165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    217696165                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    217696165                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    217696165                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    217696165                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    217696165                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000004                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53108.910891
 system.cpu.icache.overall_avg_mshr_miss_latency::total 53108.910891                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2062733                       # number of replacements
-system.cpu.dcache.tagsinuse               4076.463091                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                120152372                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4076.463619                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                120152368                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle           126234114000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4076.463091                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                  58.133676                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle           126234066000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4076.463619                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.995230                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.995230                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     88818730                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        88818730                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     88818726                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88818726                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     31333642                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       31333642                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     120152372                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        120152372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    120152372                       # number of overall hits
-system.cpu.dcache.overall_hits::total       120152372                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     120152368                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        120152368                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    120152368                       # number of overall hits
+system.cpu.dcache.overall_hits::total       120152368                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      1960720                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1960720                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       106109                       # number of WriteReq misses
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data  30195678000
 system.cpu.dcache.demand_miss_latency::total  30195678000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  30195678000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  30195678000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     90779450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     90779446                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     90779446                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    122219201                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    122219197                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    122219197                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    122219197                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    122219197                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021599                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.021599                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003375                       # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11609.663644
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 11609.663644                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                  1081                       # number of replacements
-system.cpu.l2cache.tagsinuse             19722.096664                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             19722.099231                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 3991053                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                 30157                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                132.342508                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 19370.042647                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    209.723692                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    142.330324                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 19370.045173                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    209.723718                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    142.330341                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.591127                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.006400                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.004344                       # Average percentage of cache occupancy
index ea9092f76f6fee14933e4de402a35f319f6afdf9..5b84c1efd37f5ba3ca0e1eabe45a336fe8b6feb8 100755 (executable)
@@ -1,28 +1,15 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 26 2012 21:30:36
-gem5 started Jul 26 2012 23:13:36
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:47:07
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: ***********************info: Increasing stack size by one page.
-***************info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-***********
+**************************
  58924 words stored in 3784810 bytes
 
 
@@ -35,6 +22,8 @@ Processing sentences in batch mode
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
 * do you know where John 's 
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
 * how fast the program is it 
 * I am wondering whether to invite to the party 
@@ -80,4 +69,4 @@ Echoing of input sentence turned on.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 460506550000 because target called exit()
+Exiting @ tick 460397003000 because target called exit()
index ba1f3f77bf43420ea5801dbbc757522a0c74a2f0..622f1b2562ea43e60640f38aa62033a0d5af2b33 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.460507                       # Number of seconds simulated
-sim_ticks                                460506550000                       # Number of ticks simulated
-final_tick                               460506550000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.460397                       # Number of seconds simulated
+sim_ticks                                460397003000                       # Number of ticks simulated
+final_tick                               460397003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  78127                       # Simulator instruction rate (inst/s)
-host_op_rate                                   144467                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               43510964                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 271484                       # Number of bytes of host memory used
-host_seconds                                 10583.69                       # Real time elapsed on the host
-sim_insts                                   826877144                       # Number of instructions simulated
-sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            221568                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data          27602688                       # Number of bytes read from this memory
-system.physmem.bytes_read::total             27824256                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       221568                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          221568                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks     20791168                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          20791168                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               3462                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data             431292                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                434754                       # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks          324862                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total               324862                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst               481140                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             59939838                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                60420978                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          481140                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             481140                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          45148474                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               45148474                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          45148474                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              481140                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            59939838                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              105569452                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                  79363                       # Simulator instruction rate (inst/s)
+host_op_rate                                   146752                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               44188751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 271496                       # Number of bytes of host memory used
+host_seconds                                 10418.87                       # Real time elapsed on the host
+sim_insts                                   826877109                       # Number of instructions simulated
+sim_ops                                    1528988699                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            220608                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data          27602816                       # Number of bytes read from this memory
+system.physmem.bytes_read::total             27823424                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       220608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          220608                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks     20793216                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          20793216                       # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst               3447                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             431294                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                434741                       # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks          324894                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total               324894                       # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst               479169                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             59954378                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                60433547                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          479169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             479169                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          45163665                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               45163665                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          45163665                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              479169                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            59954378                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              105597212                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                        921013101                       # number of cpu cycles simulated
+system.cpu.numCycles                        920794007                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                225814140                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted          225814140                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect           14312639                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups             160732187                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                155963049                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                225794462                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted          225794462                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect           14310990                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups             160522970                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                155979425                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles          191714211                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                     1263294933                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                   225814140                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches          155963049                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                     392136096                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                98589209                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles              239295269                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                25132                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles        236819                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                 183551766                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes               3669107                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          907433762                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.580701                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.385285                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles          191744262                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                     1263331162                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                   225794462                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches          155979425                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                     392171634                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                98591454                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles              238962985                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                25426                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles        259827                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                 183595750                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes               3654130                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          907193017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.581432                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.385361                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                519759842     57.28%     57.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                 26004641      2.87%     60.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                 29087197      3.21%     63.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                 30312943      3.34%     66.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                 19607781      2.16%     68.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                 25619101      2.82%     71.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                 32643698      3.60%     75.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                 30879699      3.40%     78.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                193518860     21.33%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                519485485     57.26%     57.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                 25996327      2.87%     60.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                 29110749      3.21%     63.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                 30309742      3.34%     66.68% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                 19641750      2.17%     68.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                 25638200      2.83%     71.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                 32631023      3.60%     75.27% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                 30872435      3.40%     78.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                193507306     21.33%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            907433762                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.245180                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.371636                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                253860681                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles             190389456                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                 329095586                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              50061804                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               84026235                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts             2290781397                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total            907193017                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.245217                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.372002                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                253820361                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles             190155093                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                 329181376                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              50007304                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               84028883                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts             2290797520                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                     2                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles               84026235                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                290493220                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                45042707                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          15282                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                 340016370                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles             147839948                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts             2240790840                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                  1987                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               24419621                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents             107426362                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents            12159                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands          2887400396                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            6494628948                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       6493753174                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups            875774                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps            1993077484                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                894322912                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1296                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1278                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                 351952477                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads            540247389                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores           217453734                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads         211358657                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         61297047                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                 2143407595                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded               68408                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                1846659650                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued           1592160                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       612815347                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined   1231279567                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved          67855                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     907433762                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         2.035035                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.801518                       # Number of insts issued each cycle
+system.cpu.rename.SquashCycles               84028883                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                290488558                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                45108603                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          15221                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                 340002879                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles             147548873                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts             2240764057                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                  2605                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               24418127                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents             107087338                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents            11838                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands          2887342076                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            6494384791                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       6493512354                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups            872437                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps            1993077392                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                894264684                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1272                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1264                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                 351172253                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads            540287564                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores           217471494                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads         211537272                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         61160620                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                 2143475674                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded               68305                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                1846648177                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued           1590040                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       612877032                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined   1231244444                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved          67752                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     907193017                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         2.035563                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.801610                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0           248935467     27.43%     27.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1           159182837     17.54%     44.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2           153661987     16.93%     61.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3           149232137     16.45%     78.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            98738940     10.88%     89.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5            59680898      6.58%     95.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6            27969436      3.08%     98.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7             8976918      0.99%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8             1055142      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0           248716450     27.42%     27.42% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1           159225433     17.55%     44.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2           153829003     16.96%     61.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3           148683388     16.39%     78.31% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            98997552     10.91%     89.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5            59757299      6.59%     95.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6            27989930      3.09%     98.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7             8953405      0.99%     99.89% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8             1040557      0.11%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       907433762                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       907193017                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                 2635361     18.49%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                8379879     58.81%     77.30% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite               3234007     22.70%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                 2618041     18.27%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     18.27% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                8472648     59.14%     77.41% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite               3236053     22.59%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           2716087      0.15%      0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu            1219498090     66.04%     66.19% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           2706611      0.15%      0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu            1219512996     66.04%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     66.19% # Type of FU issued
@@ -195,159 +195,159 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.19% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.19% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.19% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead            447052191     24.21%     90.39% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite           177393282      9.61%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead            447033831     24.21%     90.39% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite           177394739      9.61%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total             1846659650                       # Type of FU issued
-system.cpu.iq.rate                           2.005031                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                    14249247                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007716                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads         4616586705                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes        2756248953                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses   1806266388                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads                7764                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes             302326                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses          267                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses             1858190079                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                    2731                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads        168174825                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total             1846648177                       # Type of FU issued
+system.cpu.iq.rate                           2.005495                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                    14326742                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007758                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads         4616398570                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes        2756384375                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses   1806263116                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads                7583                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes             297698                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses          240                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses             1858265657                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                    2651                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads        168095723                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads    156145229                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses       432412                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       271180                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     68293794                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads    156185408                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses       429800                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       272503                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     68311550                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads         7298                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads         6430                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               84026235                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                 6572859                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles               1284585                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts          2143476003                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts           2866964                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts             540247389                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts            217453979                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               5268                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 966767                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 66701                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         271180                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect       10086388                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      5256785                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts             15343173                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts            1818783281                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts             438633483                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts          27876369                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               84028883                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                 6582029                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles               1299784                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts          2143543979                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts           2844739                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts             540287564                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts            217471735                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               5098                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 982320                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 66743                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         272503                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect       10083086                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      5258850                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts             15341936                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts            1818766036                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts             438618649                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts          27882141                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                    610463331                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                170879553                       # Number of branches executed
-system.cpu.iew.exec_stores                  171829848                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.974764                       # Inst execution rate
-system.cpu.iew.wb_sent                     1813538943                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                    1806266655                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                1378870906                       # num instructions producing a value
-system.cpu.iew.wb_consumers                2933493121                       # num instructions consuming a value
+system.cpu.iew.exec_refs                    610454199                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                170875981                       # Number of branches executed
+system.cpu.iew.exec_stores                  171835550                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.975215                       # Inst execution rate
+system.cpu.iew.wb_sent                     1813520986                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                    1806263356                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                1378693447                       # num instructions producing a value
+system.cpu.iew.wb_consumers                2933323666                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.961174                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.470044                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.961637                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.470011                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       614512471                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts      826877109                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1528988699                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       614579352                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts          14337883                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    823407527                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.856904                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     2.319659                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts          14336742                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    823164134                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.857453                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     2.320209                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0    305105182     37.05%     37.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1    205650111     24.98%     62.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     74228668      9.01%     71.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     96597559     11.73%     82.78% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4     29968597      3.64%     86.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5     28751826      3.49%     89.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6     15821579      1.92%     91.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7     11746400      1.43%     93.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8     55537605      6.74%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0    305087340     37.06%     37.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1    205283379     24.94%     62.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     74494797      9.05%     71.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     96404931     11.71%     82.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4     29976642      3.64%     86.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5     28775074      3.50%     89.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6     15838255      1.92%     91.82% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7     11740263      1.43%     93.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8     55563453      6.75%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    823407527                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
-system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    823164134                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            826877109                       # Number of instructions committed
+system.cpu.commit.committedOps             1528988699                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                      533262345                       # Number of memory references committed
-system.cpu.commit.loads                     384102160                       # Number of loads committed
+system.cpu.commit.refs                      533262341                       # Number of memory references committed
+system.cpu.commit.loads                     384102156                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                  149758588                       # Number of branches committed
+system.cpu.commit.branches                  149758583                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                1528317614                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                1528317557                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events              55537605                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events              55563453                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                   2911371149                       # The number of ROB reads
-system.cpu.rob.rob_writes                  4371143864                       # The number of ROB writes
-system.cpu.timesIdled                          309440                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                        13579339                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
-system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
-system.cpu.cpi                               1.113845                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.113845                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.897791                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.897791                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads               4004246874                       # number of integer regfile reads
-system.cpu.int_regfile_writes              2286313998                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                       266                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads              1001920728                       # number of misc regfile reads
-system.cpu.icache.replacements                   5588                       # number of replacements
-system.cpu.icache.tagsinuse               1044.044381                       # Cycle average of tags in use
-system.cpu.icache.total_refs                183312403                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7204                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               25445.919350                       # Average number of references to valid blocks.
+system.cpu.rob.rob_reads                   2911168732                       # The number of ROB reads
+system.cpu.rob.rob_writes                  4371280103                       # The number of ROB writes
+system.cpu.timesIdled                          309541                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                        13600990                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   826877109                       # Number of Instructions Simulated
+system.cpu.committedOps                    1528988699                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             826877109                       # Number of Instructions Simulated
+system.cpu.cpi                               1.113580                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.113580                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.898004                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.898004                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads               4004208844                       # number of integer regfile reads
+system.cpu.int_regfile_writes              2286339718                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                       238                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
+system.cpu.misc_regfile_reads              1001924846                       # number of misc regfile reads
+system.cpu.icache.replacements                   5564                       # number of replacements
+system.cpu.icache.tagsinuse               1044.277661                       # Cycle average of tags in use
+system.cpu.icache.total_refs                183360161                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7185                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs               25519.855393                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1044.044381                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.509787                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.509787                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    183329342                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       183329342                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     183329342                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        183329342                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    183329342                       # number of overall hits
-system.cpu.icache.overall_hits::total       183329342                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst       222424                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total        222424                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst       222424                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total         222424                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst       222424                       # number of overall misses
-system.cpu.icache.overall_misses::total        222424                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   1554709500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   1554709500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   1554709500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   1554709500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   1554709500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   1554709500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    183551766                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    183551766                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    183551766                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    183551766                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    183551766                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    183551766                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001212                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.001212                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.001212                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.001212                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.001212                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.001212                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  6989.845970                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total  6989.845970                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst  6989.845970                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total  6989.845970                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst  6989.845970                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total  6989.845970                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1044.277661                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.509901                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.509901                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    183377049                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       183377049                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     183377049                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        183377049                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    183377049                       # number of overall hits
+system.cpu.icache.overall_hits::total       183377049                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       218701                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        218701                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       218701                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         218701                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       218701                       # number of overall misses
+system.cpu.icache.overall_misses::total        218701                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1530978500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1530978500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1530978500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1530978500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1530978500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1530978500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    183595750                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    183595750                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    183595750                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    183595750                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    183595750                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    183595750                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001191                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.001191                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001191                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.001191                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001191                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.001191                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  7000.326930                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total  7000.326930                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  7000.326930                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total  7000.326930                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  7000.326930                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total  7000.326930                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -356,94 +356,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1671                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1671                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1671                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1671                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1671                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1671                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst       220753                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total       220753                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst       220753                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total       220753                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst       220753                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total       220753                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    807012500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    807012500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    807012500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    807012500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    807012500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    807012500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001203                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.001203                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001203                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.001203                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3655.726083                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total  3655.726083                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3655.726083                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total  3655.726083                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1667                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1667                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1667                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1667                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1667                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1667                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       217034                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       217034                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       217034                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       217034                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       217034                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       217034                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    795818000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    795818000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    795818000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    795818000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    795818000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    795818000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001182                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001182                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001182                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.001182                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001182                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.001182                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  3666.789535                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total  3666.789535                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  3666.789535                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total  3666.789535                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  3666.789535                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total  3666.789535                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                2526911                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.001481                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                415013959                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                2531007                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 163.971873                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             2119650000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.001481                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.997803                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.997803                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    266164816                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       266164816                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data    148172858                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total      148172858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     414337674                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        414337674                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    414337674                       # number of overall hits
-system.cpu.dcache.overall_hits::total       414337674                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data      2652510                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total       2652510                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data       987343                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total       987343                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data      3639853                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total        3639853                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data      3639853                       # number of overall misses
-system.cpu.dcache.overall_misses::total       3639853                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data  36720929000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total  36720929000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data  18986429000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total  18986429000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data  55707358000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total  55707358000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data  55707358000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total  55707358000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    268817326                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    268817326                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.replacements                2526946                       # number of replacements
+system.cpu.dcache.tagsinuse               4087.012033                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                415079459                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                2531042                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                 163.995484                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             2118352000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.012033                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997806                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997806                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    266229970                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       266229970                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148176522                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148176522                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     414406492                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        414406492                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    414406492                       # number of overall hits
+system.cpu.dcache.overall_hits::total       414406492                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2652987                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2652987                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       983679                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       983679                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3636666                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3636666                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3636666                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3636666                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  36715559000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  36715559000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  18841751000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  18841751000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  55557310000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  55557310000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  55557310000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  55557310000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    268882957                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    268882957                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    417977527                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    417977527                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    417977527                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    417977527                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    418043158                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    418043158                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    418043158                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    418043158                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009867                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.009867                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006619                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.006619                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.008708                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.008708                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.008708                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.008708                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13843.841871                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13843.841871                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19229.820842                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 19229.820842                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 15304.837311                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 15304.837311                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 15304.837311                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 15304.837311                       # average overall miss latency
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006595                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.006595                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008699                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.008699                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008699                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.008699                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13839.328651                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 13839.328651                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 19154.369464                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 19154.369464                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15276.989968                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 15276.989968                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15276.989968                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 15276.989968                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -452,144 +452,144 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks      2302631                       # number of writebacks
-system.cpu.dcache.writebacks::total           2302631                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data       892307                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total       892307                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3035                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total         3035                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data       895342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total       895342                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data       895342                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total       895342                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760203                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total      1760203                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data       984308                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total       984308                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data      2744511                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total      2744511                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data      2744511                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total      2744511                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12496937149                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total  12496937149                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15830652502                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total  15830652502                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28327589651                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total  28327589651                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28327589651                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total  28327589651                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006548                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006548                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006599                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006599                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.006566                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006566                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.006566                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7099.713584                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7099.713584                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16083.027367                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16083.027367                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10321.543492                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 10321.543492                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10321.543492                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 10321.543492                       # average overall mshr miss latency
+system.cpu.dcache.writebacks::writebacks      2302737                       # number of writebacks
+system.cpu.dcache.writebacks::total           2302737                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       892793                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       892793                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3022                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3022                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       895815                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       895815                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       895815                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       895815                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1760194                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1760194                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       980657                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       980657                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2740851                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2740851                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2740851                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2740851                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  12492277176                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  12492277176                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  15700711503                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  15700711503                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  28192988679                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  28192988679                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  28192988679                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  28192988679                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006546                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.006546                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006575                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.006575                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.006556                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006556                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.006556                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7097.102465                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total  7097.102465                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 16010.400683                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 16010.400683                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10286.217193                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 10286.217193                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10286.217193                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 10286.217193                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.replacements                408577                       # number of replacements
-system.cpu.l2cache.tagsinuse             29310.101870                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                 3608876                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                440919                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  8.184896                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          220647003000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21083.038182                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst    149.770059                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   8077.293628                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.643403                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.004571                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.246499                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.894473                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         3685                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data      1537271                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total        1540956                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks      2302631                       # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total      2302631                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data         1259                       # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total         1259                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data       562411                       # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total       562411                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         3685                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data      2099682                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total         2103367                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         3685                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data      2099682                       # number of overall hits
-system.cpu.l2cache.overall_hits::total        2103367                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3462                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data       222130                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total       225592                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data       212243                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total       212243                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data       209197                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total       209197                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3462                       # number of demand (read+write) misses
+system.cpu.l2cache.replacements                408579                       # number of replacements
+system.cpu.l2cache.tagsinuse             29311.103059                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                 3608561                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                440913                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  8.184293                       # Average number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle          220580493000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21085.621991                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    148.428865                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   8077.052203                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.643482                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.004530                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.246492                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.894504                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         3663                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1537262                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1540925                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2302737                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2302737                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1268                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1268                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       562455                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       562455                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         3663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2099717                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2103380                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         3663                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2099717                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2103380                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3447                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       222139                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       225586                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       208539                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       208539                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       209188                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       209188                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3447                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data       431327                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total        434789                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3462                       # number of overall misses
+system.cpu.l2cache.demand_misses::total        434774                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3447                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data       431327                       # number of overall misses
-system.cpu.l2cache.overall_misses::total       434789                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    121473500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7624503923                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total   7745977423                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10569500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total     10569500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7166790000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total   7166790000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    121473500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data  14791293923                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total  14912767423                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    121473500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data  14791293923                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total  14912767423                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7147                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total       434774                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120849500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   7624606932                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   7745456432                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     10570500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total     10570500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   7166508500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   7166508500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    120849500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  14791115432                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  14911964932                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    120849500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  14791115432                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  14911964932                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7110                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data      1759401                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total      1766548                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::writebacks      2302631                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses::total      2302631                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data       213502                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total       213502                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data       771608                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total       771608                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7147                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data      2531009                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total      2538156                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7147                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data      2531009                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total      2538156                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.484399                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126253                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.127702                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.994103                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total     0.994103                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271118                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.271118                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.484399                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.170417                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.171301                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.484399                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.170417                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.171301                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35087.666089                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34324.512326                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34336.223904                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    49.799051                       # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    49.799051                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.569674                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.569674                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35087.666089                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.529619                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34298.860880                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35087.666089                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.529619                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34298.860880                       # average overall miss latency
+system.cpu.l2cache.ReadReq_accesses::total      1766511                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2302737                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2302737                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       209807                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       209807                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771643                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771643                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7110                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2531044                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2538154                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7110                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2531044                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2538154                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.484810                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.126258                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.127701                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.993956                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total     0.993956                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.271094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.271094                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.484810                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.170415                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.171295                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.484810                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.170415                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.171295                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35059.326951                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34323.585377                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34334.827658                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    50.688360                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total    50.688360                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34258.697918                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34258.697918                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35059.326951                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34292.115801                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34298.198448                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35059.326951                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34292.115801                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34298.198448                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -598,60 +598,60 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::writebacks       324862                       # number of writebacks
-system.cpu.l2cache.writebacks::total           324862                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3462                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222130                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total       225592                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       212243                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total       212243                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209197                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total       209197                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3462                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.writebacks::writebacks       324894                       # number of writebacks
+system.cpu.l2cache.writebacks::total           324894                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3447                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       222139                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       225586                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       208539                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       208539                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       209188                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       209188                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3447                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data       431327                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total       434789                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3462                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       434774                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3447                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data       431327                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total       434789                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    110501000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6934646999                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7045147999                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6580894500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6580894500                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6486675500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6486675500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    110501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13421322499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total  13531823499                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    110501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13421322499                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total  13531823499                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126253                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127702                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.994103                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.994103                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271118                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271118                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170417                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.171301                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.484399                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170417                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.171301                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31218.867325                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31229.600336                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31006.414817                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31006.414817                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31007.497717                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31007.497717                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.351397                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.736543                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31918.255344                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.351397                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.736543                       # average overall mshr miss latency
+system.cpu.l2cache.overall_mshr_misses::total       434774                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    109944000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   6934594999                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   7044538999                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6467053500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6467053500                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   6486625500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   6486625500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    109944000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  13421220499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  13531164499                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    109944000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  13421220499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  13531164499                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.484810                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.126258                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.127701                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.993956                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.993956                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.271094                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.271094                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.484810                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.170415                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.171295                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.484810                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.170415                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.171295                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31895.561358                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31217.368400                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31227.731326                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31011.242501                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31011.242501                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.592749                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31008.592749                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31895.561358                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31116.114917                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31122.294569                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31895.561358                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31116.114917                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31122.294569                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8e0e263beedd6698f1d5cb4d7804552976da5718..631aee4c48f069a317279d3dc5896576099384a5 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index 337e5053a9775f7a9bca333e3dfd6619ac2b3d1a..2e1cac91e8eaa3a0b49bd5686422b03be019f458 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:38:11
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:52:16
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -69,4 +69,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 885229360000 because target called exit()
+Exiting @ tick 885229327000 because target called exit()
index a8445ed5c75196eafc703aa703701794692ae1ca..84b45e732695f3523b385d74d7e706b991bbbae7 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.885229                       # Number of seconds simulated
-sim_ticks                                885229360000                       # Number of ticks simulated
-final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                885229327000                       # Number of ticks simulated
+final_tick                               885229327000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1285236                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2376545                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1375933868                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220604                       # Number of bytes of host memory used
-host_seconds                                   643.37                       # Real time elapsed on the host
-sim_insts                                   826877145                       # Number of instructions simulated
-sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst        8546776872                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        2285655660                       # Number of bytes read from this memory
-system.physmem.bytes_read::total          10832432532                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   8546776872                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      8546776872                       # Number of instructions bytes read from this memory
+host_inst_rate                                1279506                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2365950                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1369799774                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228100                       # Number of bytes of host memory used
+host_seconds                                   646.25                       # Real time elapsed on the host
+sim_insts                                   826877110                       # Number of instructions simulated
+sim_ops                                    1528988700                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        8546776520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        2285655656                       # Number of bytes read from this memory
+system.physmem.bytes_read::total          10832432176                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   8546776520                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      8546776520                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data      991849460                       # Number of bytes written to this memory
 system.physmem.bytes_written::total         991849460                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         1068347109                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data          384102189                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            1452449298                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst         1068347065                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data          384102185                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            1452449250                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         149160201                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            149160201                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           9654872803                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2581992604                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             12236865406                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      9654872803                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         9654872803                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1120443475                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1120443475                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          9654872803                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3702436078                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13357308881                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           9654872765                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2581992695                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             12236865460                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      9654872765                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         9654872765                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1120443516                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1120443516                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          9654872765                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3702436212                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13357308977                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       1770458721                       # number of cpu cycles simulated
+system.cpu.numCycles                       1770458655                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   826877145                       # Number of instructions committed
-system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.committedInsts                   826877110                       # Number of instructions committed
+system.cpu.committedOps                    1528988700                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1528317558                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1528317558                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          4441632810                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1993077484                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          4441632632                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1993077392                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     533262345                       # number of memory refs
-system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_mem_refs                     533262341                       # number of memory refs
+system.cpu.num_load_insts                   384102156                       # Number of load instructions
 system.cpu.num_store_insts                  149160185                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 1770458721                       # Number of busy cycles
+system.cpu.num_busy_cycles                 1770458655                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 2d97cc0b1919be88638588a8fa205acffdede50a..5307ccc0b378b6c85a87843754a298c6e6fc1aa9 100644 (file)
@@ -179,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 1335d36581a2c29ef4d192002bee5aa92001533e..d712433e856d4f1dbbf1b8216b82ec3c9a1a2106 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 13:47:25
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 19:03:12
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -69,4 +69,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 1652606875000 because target called exit()
+Exiting @ tick 1652606827000 because target called exit()
index ae8bc7b58a3772fd32251982489151c4be60dd99..9139f6ef0793fb50533dc4bae8a0f20da2e1d6af 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  1.652607                       # Number of seconds simulated
-sim_ticks                                1652606875000                       # Number of ticks simulated
-final_tick                               1652606875000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                1652606827000                       # Number of ticks simulated
+final_tick                               1652606827000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 673883                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1246085                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1346830511                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 232676                       # Number of bytes of host memory used
-host_seconds                                  1227.03                       # Real time elapsed on the host
-sim_insts                                   826877145                       # Number of instructions simulated
-sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 715148                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1322389                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1429304042                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 236556                       # Number of bytes of host memory used
+host_seconds                                  1156.23                       # Real time elapsed on the host
+sim_insts                                   826877110                       # Number of instructions simulated
+sim_ops                                    1528988700                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            123584                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          27359872                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             27483456                       # Number of bytes read from this memory
@@ -24,54 +24,54 @@ system.physmem.num_reads::total                429429                       # Nu
 system.physmem.num_writes::writebacks          323570                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               323570                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst                74781                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             16555584                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                16630365                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             16555585                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                16630366                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst           74781                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total              74781                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          12530796                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               12530796                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          12530796                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          12530797                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               12530797                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          12530797                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst               74781                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            16555584                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            16555585                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               29161162                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  551                       # Number of system calls
-system.cpu.numCycles                       3305213750                       # number of cpu cycles simulated
+system.cpu.numCycles                       3305213654                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   826877145                       # Number of instructions committed
-system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
+system.cpu.committedInsts                   826877110                       # Number of instructions committed
+system.cpu.committedOps                    1528988700                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            1528317558                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts     92658800                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   1528317615                       # number of integer instructions
+system.cpu.num_conditional_control_insts     92658795                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   1528317558                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads          4441632810                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         1993077484                       # number of times the integer registers were written
+system.cpu.num_int_register_reads          4441632632                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         1993077392                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                     533262345                       # number of memory refs
-system.cpu.num_load_insts                   384102160                       # Number of load instructions
+system.cpu.num_mem_refs                     533262341                       # number of memory refs
+system.cpu.num_load_insts                   384102156                       # Number of load instructions
 system.cpu.num_store_insts                  149160185                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 3305213750                       # Number of busy cycles
+system.cpu.num_busy_cycles                 3305213654                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   1253                       # number of replacements
-system.cpu.icache.tagsinuse                881.608185                       # Cycle average of tags in use
-system.cpu.icache.total_refs               1068344296                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                881.608211                       # Cycle average of tags in use
+system.cpu.icache.total_refs               1068344252                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               379653.252310                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     881.608185                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     881.608211                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.430473                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.430473                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst   1068344296                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      1068344296                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    1068344296                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       1068344296                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   1068344296                       # number of overall hits
-system.cpu.icache.overall_hits::total      1068344296                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst   1068344252                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1068344252                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1068344252                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1068344252                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1068344252                       # number of overall hits
+system.cpu.icache.overall_hits::total      1068344252                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    120792000
 system.cpu.icache.demand_miss_latency::total    120792000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    120792000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    120792000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   1068347110                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   1068347110                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   1068347110                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   1068347110                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   1068347110                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   1068347066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1068347066                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1068347066                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1068347066                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1068347066                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1068347066                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000003                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39925.373134
 system.cpu.icache.overall_avg_mshr_miss_latency::total 39925.373134                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2514362                       # number of replacements
-system.cpu.dcache.tagsinuse               4086.431953                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                530743932                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4086.432071                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                530743928                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle             8218697000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4086.431953                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                 210.741624                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle             8218649000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4086.432071                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997664                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997664                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data    382374775                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total       382374775                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data    382374771                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       382374771                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      148369157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data     530743932                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total        530743932                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data    530743932                       # number of overall hits
-system.cpu.dcache.overall_hits::total       530743932                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data     530743928                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        530743928                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    530743928                       # number of overall hits
+system.cpu.dcache.overall_hits::total       530743928                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data  53256878500
 system.cpu.dcache.demand_miss_latency::total  53256878500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  53256878500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  53256878500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data    384102189                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total    384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data    384102185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    384102185                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data    533262390                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total    533262390                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data    533262390                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total    533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data    533262386                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    533262386                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    533262386                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    533262386                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.004497                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18146.617494
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 18146.617494                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                403150                       # number of replacements
-system.cpu.l2cache.tagsinuse             29113.385052                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29113.385897                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 3572765                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                435501                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  8.203804                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          773011530000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 21035.861184                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst     79.696348                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   7997.827520                       # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle          773011482000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 21035.861795                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     79.696350                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7997.827752                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.641964                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.002432                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.244074                       # Average percentage of cache occupancy
index 49574e0d6579b171233382f313145a496644f9ec..dd4ef298a1242b2c46f9d98035cf91116e695ad3 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index ea448ddbaac623df9b321fb0ee83d49f940f7386..0a5ffdd786372b0e41df0196ea086856735cb935 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:58:33
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:18:28
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 68148678500 because target called exit()
+Exiting @ tick 68148672000 because target called exit()
index 158c6976f6806d375ff148e28e61f737e323e555..932598cf91d079567f196ca5cd67da5a4a2de9ea 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.068149                       # Number of seconds simulated
-sim_ticks                                 68148678500                       # Number of ticks simulated
-final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                 68148672000                       # Number of ticks simulated
+final_tick                                68148672000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2876458                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2913702                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1458542737                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222372                       # Number of bytes of host memory used
-host_seconds                                    46.72                       # Real time elapsed on the host
-sim_insts                                   134398975                       # Number of instructions simulated
-sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst         538214332                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         147559361                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            685773693                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    538214332                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       538214332                       # Number of instructions bytes read from this memory
+host_inst_rate                                2819750                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2856259                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1429788311                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230172                       # Number of bytes of host memory used
+host_seconds                                    47.66                       # Real time elapsed on the host
+sim_insts                                   134398962                       # Number of instructions simulated
+sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         538214280                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            685773640                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    538214280                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       538214280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data       89882950                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          89882950                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          134553583                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           37231301                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             171784884                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          134553570                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           37231300                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             171784870                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          20864304                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             20864304                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data              15916                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                 15916                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7897648844                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2165256381                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10062905226                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7897648844                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7897648844                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1318924328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1318924328                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7897648844                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3484180709                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11381829554                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7897648835                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2165256573                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10062905408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7897648835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7897648835                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1318924454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1318924454                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7897648835                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3484181027                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11381829862                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
+system.cpu.numCycles                        136297345                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398975                       # Number of instructions committed
-system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.committedInsts                   134398962                       # Number of instructions committed
+system.cpu.committedOps                     136139190                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             115187746                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8898969                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187746                       # number of integer instructions
 system.cpu.num_fp_insts                       2326977                       # number of float instructions
-system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147747                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           263032361                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147734                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160249                       # number of memory refs
-system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160248                       # number of memory refs
+system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  136297358                       # Number of busy cycles
+system.cpu.num_busy_cycles                  136297345                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 221d86591edd40102de9ee3e203d4eb5d6958096..a3a9288131520a85ad8ff46f508f6c0697438e46 100644 (file)
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 98fb0b2cde2e4ef5078e012375d0437c373ff401..3a91ca0937392bc23876cb495abfa7d878059bfc 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:32:55
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:19:26
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 204097192000 because target called exit()
+Exiting @ tick 204097178000 because target called exit()
index a6ef183243d592b5a8e7169f856a3aa34bfca18e..fbfcfb0907fbddad5cf8d6d9b3672ef545c8fc0b 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.204097                       # Number of seconds simulated
-sim_ticks                                204097192000                       # Number of ticks simulated
-final_tick                               204097192000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                204097178000                       # Number of ticks simulated
+final_tick                               204097178000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1236624                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1252636                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1877926206                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 229284                       # Number of bytes of host memory used
-host_seconds                                   108.68                       # Real time elapsed on the host
-sim_insts                                   134398975                       # Number of instructions simulated
-sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1441199                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1459859                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2188591939                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238748                       # Number of bytes of host memory used
+host_seconds                                    93.26                       # Real time elapsed on the host
+sim_insts                                   134398962                       # Number of instructions simulated
+sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            665664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7906112                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8571776                       # Number of bytes read from this memory
@@ -24,54 +24,54 @@ system.physmem.num_reads::total                133934                       # Nu
 system.physmem.num_writes::writebacks           82834                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                82834                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.inst              3261505                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             38736995                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                41998500                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38736998                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                41998503                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst         3261505                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total            3261505                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          25974762                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               25974762                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          25974762                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::writebacks          25974764                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               25974764                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          25974764                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst             3261505                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38736995                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               67973262                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38736998                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               67973267                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        408194384                       # number of cpu cycles simulated
+system.cpu.numCycles                        408194356                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   134398975                       # Number of instructions committed
-system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
+system.cpu.committedInsts                   134398962                       # Number of instructions committed
+system.cpu.committedOps                     136139190                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             115187746                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8898970                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    115187758                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8898969                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    115187746                       # number of integer instructions
 system.cpu.num_fp_insts                       2326977                       # number of float instructions
-system.cpu.num_int_register_reads           263032383                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          113147746                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           263032361                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          113147733                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              4725607                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1150968                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      58160249                       # number of memory refs
-system.cpu.num_load_insts                    37275868                       # Number of load instructions
+system.cpu.num_mem_refs                      58160248                       # number of memory refs
+system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  408194384                       # Number of busy cycles
+system.cpu.num_busy_cycles                  408194356                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                 184976                       # number of replacements
-system.cpu.icache.tagsinuse               2004.409813                       # Cycle average of tags in use
-system.cpu.icache.total_refs                134366560                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               2004.409949                       # Cycle average of tags in use
+system.cpu.icache.total_refs                134366547                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle           145330300000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    2004.409813                       # Average occupied blocks per requestor
+system.cpu.icache.avg_refs                 718.445478                       # Average number of references to valid blocks.
+system.cpu.icache.warmup_cycle           145330286000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst    2004.409949                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.978716                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.978716                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    134366560                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       134366560                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     134366560                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        134366560                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    134366560                       # number of overall hits
-system.cpu.icache.overall_hits::total       134366560                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    134366547                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       134366547                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     134366547                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        134366547                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    134366547                       # number of overall hits
+system.cpu.icache.overall_hits::total       134366547                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst       187024                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        187024                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst       187024                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst   3060544000
 system.cpu.icache.demand_miss_latency::total   3060544000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst   3060544000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total   3060544000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    134553584                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    134553584                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    134553584                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    134553584                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    134553571                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    134553571                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    134553571                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    134553571                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    134553571                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    134553571                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001390                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.001390                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.001390                       # miss rate for demand accesses
@@ -136,24 +136,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13364.445205
 system.cpu.icache.overall_avg_mshr_miss_latency::total 13364.445205                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 146582                       # number of replacements
-system.cpu.dcache.tagsinuse               4087.412837                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 57960843                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4087.413116                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 57960842                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle              812044000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4087.412837                       # Average occupied blocks per requestor
+system.cpu.dcache.avg_refs                 384.666919                       # Average number of references to valid blocks.
+system.cpu.dcache.warmup_cycle              812030000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4087.413116                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997904                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997904                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     37185802                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        37185802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     37185801                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37185801                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       20759140                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data        15901                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total           15901                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data      57944942                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         57944942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     57944942                       # number of overall hits
-system.cpu.dcache.overall_hits::total        57944942                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      57944941                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         57944941                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     57944941                       # number of overall hits
+system.cpu.dcache.overall_hits::total        57944941                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data        45499                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total         45499                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       105164                       # number of WriteReq misses
@@ -174,16 +174,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data   7299977000
 system.cpu.dcache.demand_miss_latency::total   7299977000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data   7299977000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total   7299977000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20864304                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data        15916                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total        15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     58095604                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     58095604                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     58095604                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     58095604                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.001222                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005040                       # miss rate for WriteReq accesses
@@ -256,14 +256,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45452.353929
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 45452.353929                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                101560                       # number of replacements
-system.cpu.l2cache.tagsinuse             29278.940429                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             29278.942435                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                  222505                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                132357                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.681097                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 24760.226438                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   3263.271337                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data   1255.442654                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::writebacks 24760.228137                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   3263.271559                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1255.442739                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.755622                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.099587                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.038313                       # Average percentage of cache occupancy
index 4b0cea416e9eda832fadfe58803157c586e3b86a..d332c41fc1043a53f49a71d1451572635959452c 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index c6605043f206bb4e71614e7c680fa0f2b283e019..3c6a6098cb4a006c2bac1e8f0a528f50aeb460a3 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:49:05
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 19:04:29
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 2846007259500 because target called exit()
+Exiting @ tick 2846007226500 because target called exit()
index d066014cc50d46c981ea7771c786dd9c8bce2a25..f428cd22826d580a65568e8c119305e408829325 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  2.846007                       # Number of seconds simulated
-sim_ticks                                2846007259500                       # Number of ticks simulated
-final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                2846007226500                       # Number of ticks simulated
+final_tick                               2846007226500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1390065                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2165848                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1315169413                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216596                       # Number of bytes of host memory used
-host_seconds                                  2163.99                       # Real time elapsed on the host
-sim_insts                                  3008081057                       # Number of instructions simulated
-sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst       32105863408                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data        5023868347                       # Number of bytes read from this memory
-system.physmem.bytes_read::total          37129731755                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst  32105863408                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total     32105863408                       # Number of instructions bytes read from this memory
+host_inst_rate                                1386030                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2159560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1311351119                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224788                       # Number of bytes of host memory used
+host_seconds                                  2170.29                       # Real time elapsed on the host
+sim_insts                                  3008081022                       # Number of instructions simulated
+sim_ops                                    4686862594                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst       32105863056                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data        5023868343                       # Number of bytes read from this memory
+system.physmem.bytes_read::total          37129731399                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst  32105863056                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total     32105863056                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data     1544656790                       # Number of bytes written to this memory
 system.physmem.bytes_written::total        1544656790                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst         4013232926                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data         1239184749                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total            5252417675                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst         4013232882                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data         1239184745                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total            5252417627                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data         438528337                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total            438528337                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          11281019506                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1765233848                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             13046253354                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     11281019506                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        11281019506                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           542745204                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              542745204                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         11281019506                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2307979052                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13588998558                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst          11281019513                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1765233867                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             13046253380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst     11281019513                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total        11281019513                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           542745210                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              542745210                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst         11281019513                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2307979077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13588998590                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                       5692014520                       # number of cpu cycles simulated
+system.cpu.numCycles                       5692014454                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  3008081057                       # Number of instructions committed
-system.cpu.committedOps                    4686862651                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.committedInsts                  3008081022                       # Number of instructions committed
+system.cpu.committedOps                    4686862594                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            4686862523                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   4686862523                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads         14165752766                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         6716691823                       # number of times the integer registers were written
+system.cpu.num_int_register_reads         14165752588                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         6716691731                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                    1677713086                       # number of memory refs
-system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_mem_refs                    1677713082                       # number of memory refs
+system.cpu.num_load_insts                  1239184745                       # Number of load instructions
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                 5692014520                       # Number of busy cycles
+system.cpu.num_busy_cycles                 5692014454                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index f840aa9a44aba8efcb26c626a3d83ec7b25861dd..4471a2bb35d305d824d8a9527900293495f96299 100644 (file)
@@ -179,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 05d9e4afdfc0ad27bad5203f612cbbb7b154ef07..93d28d3546bf8378abb8517e7e64a720da8cbdfc 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 14:08:03
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 19:22:39
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
@@ -24,4 +24,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 5901048931000 because target called exit()
+Exiting @ tick 5901048883000 because target called exit()
index 50b0e856fb11fdd392516930b3d64ec82c887c17..b958342173ed1d35a4a3c45ca10bbf936c53595a 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  5.901049                       # Number of seconds simulated
-sim_ticks                                5901048931000                       # Number of ticks simulated
-final_tick                               5901048931000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                5901048883000                       # Number of ticks simulated
+final_tick                               5901048883000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 821481                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1279942                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1611526350                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228472                       # Number of bytes of host memory used
-host_seconds                                  3661.78                       # Real time elapsed on the host
-sim_insts                                  3008081057                       # Number of instructions simulated
-sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 766833                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1194795                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1504320663                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233368                       # Number of bytes of host memory used
+host_seconds                                  3922.73                       # Real time elapsed on the host
+sim_insts                                  3008081022                       # Number of instructions simulated
+sim_ops                                    4686862594                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             43200                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         139043584                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            139086784                       # Number of bytes read from this memory
@@ -35,43 +35,43 @@ system.physmem.bw_total::cpu.inst                7321                       # To
 system.physmem.bw_total::cpu.data            23562520                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               34990498                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   46                       # Number of system calls
-system.cpu.numCycles                      11802097862                       # number of cpu cycles simulated
+system.cpu.numCycles                      11802097766                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                  3008081057                       # Number of instructions committed
-system.cpu.committedOps                    4686862651                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
+system.cpu.committedInsts                  3008081022                       # Number of instructions committed
+system.cpu.committedOps                    4686862594                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses            4686862523                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts    182173305                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                   4686862580                       # number of integer instructions
+system.cpu.num_conditional_control_insts    182173300                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                   4686862523                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads         14165752766                       # number of times the integer registers were read
-system.cpu.num_int_register_writes         6716691823                       # number of times the integer registers were written
+system.cpu.num_int_register_reads         14165752588                       # number of times the integer registers were read
+system.cpu.num_int_register_writes         6716691731                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                    1677713086                       # number of memory refs
-system.cpu.num_load_insts                  1239184749                       # Number of load instructions
+system.cpu.num_mem_refs                    1677713082                       # number of memory refs
+system.cpu.num_load_insts                  1239184745                       # Number of load instructions
 system.cpu.num_store_insts                  438528337                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                11802097862                       # Number of busy cycles
+system.cpu.num_busy_cycles                11802097766                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     10                       # number of replacements
-system.cpu.icache.tagsinuse                555.745883                       # Cycle average of tags in use
-system.cpu.icache.total_refs               4013232252                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                555.745887                       # Cycle average of tags in use
+system.cpu.icache.total_refs               4013232208                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               5945529.262222                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               5945529.197037                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     555.745883                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst     555.745887                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.271360                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.271360                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst   4013232252                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total      4013232252                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst    4013232252                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total       4013232252                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst   4013232252                       # number of overall hits
-system.cpu.icache.overall_hits::total      4013232252                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst   4013232208                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      4013232208                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    4013232208                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       4013232208                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   4013232208                       # number of overall hits
+system.cpu.icache.overall_hits::total      4013232208                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
@@ -84,12 +84,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst     37868000
 system.cpu.icache.demand_miss_latency::total     37868000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     37868000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     37868000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst   4013232927                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total   4013232927                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst   4013232927                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total   4013232927                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst   4013232927                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total   4013232927                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst   4013232883                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   4013232883                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   4013232883                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   4013232883                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   4013232883                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   4013232883                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000000                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
@@ -136,22 +136,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53100.740741
 system.cpu.icache.overall_avg_mshr_miss_latency::total 53100.740741                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9108581                       # number of replacements
-system.cpu.dcache.tagsinuse               4084.618075                       # Cycle average of tags in use
-system.cpu.dcache.total_refs               1668600409                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               4084.618108                       # Cycle average of tags in use
+system.cpu.dcache.total_refs               1668600405                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
-system.cpu.dcache.warmup_cycle            58864243000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    4084.618075                       # Average occupied blocks per requestor
+system.cpu.dcache.warmup_cycle            58864195000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.occ_blocks::cpu.data    4084.618108                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.997221                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.997221                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data   1231961899                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total      1231961899                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data   1231961895                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total      1231961895                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data    436638510                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total      436638510                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data    1668600409                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total       1668600409                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data   1668600409                       # number of overall hits
-system.cpu.dcache.overall_hits::total      1668600409                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data    1668600405                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total       1668600405                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data   1668600405                       # number of overall hits
+system.cpu.dcache.overall_hits::total      1668600405                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
@@ -168,14 +168,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data 218826366000
 system.cpu.dcache.demand_miss_latency::total 218826366000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data 218826366000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total 218826366000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data   1239184749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total   1239184749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data   1239184745                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total   1239184745                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data    438528337                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total    438528337                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data   1677713086                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total   1677713086                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data   1677713086                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total   1677713086                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data   1677713082                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total   1677713082                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data   1677713082                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total   1677713082                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.005829                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses
@@ -236,14 +236,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21013.400892
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21013.400892                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2158210                       # number of replacements
-system.cpu.l2cache.tagsinuse             30851.471232                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse             30851.471482                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                 8410861                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs               2187939                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  3.844194                       # Average number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle          1317386171000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks 14661.795010                       # Average occupied blocks per requestor
+system.cpu.l2cache.warmup_cycle          1317386123000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.occ_blocks::writebacks 14661.795129                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_blocks::cpu.inst     21.581563                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data  16168.094659                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  16168.094790                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.447442                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.000659                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.493411                       # Average percentage of cache occupancy
index 505ad335a32788f999f80230a957d63c00e45586..48cbbbbde444f61a7f193531251b4d8af8c2b27b 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index 435dd5018aed1f6d76f7ad0edda2277931d18daf..a6bbf65c94a775829c2fe4ac62de286dad71066a 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 15:01:23
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:21:10
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
@@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
 info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 96722951500 because target called exit()
+122 123 124 Exiting @ tick 96722945000 because target called exit()
index 7fc4c3f517d706c2d01a992590c8fa77385039bc..fd4974069fb9cb1d5ff133335d326ea13e0fb4fc 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.096723                       # Number of seconds simulated
-sim_ticks                                 96722951500                       # Number of ticks simulated
-final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                 96722945000                       # Number of ticks simulated
+final_tick                                96722945000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2785942                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2785945                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1392980356                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218424                       # Number of bytes of host memory used
-host_seconds                                    69.44                       # Real time elapsed on the host
-sim_insts                                   193444531                       # Number of instructions simulated
-sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst         773782192                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         223463414                       # Number of bytes read from this memory
-system.physmem.bytes_read::total            997245606                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst    773782192                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total       773782192                       # Number of instructions bytes read from this memory
+host_inst_rate                                2917410                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2917413                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1458714810                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226640                       # Number of bytes of host memory used
+host_seconds                                    66.31                       # Real time elapsed on the host
+sim_insts                                   193444518                       # Number of instructions simulated
+sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst         773782140                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         223463413                       # Number of bytes read from this memory
+system.physmem.bytes_read::total            997245553                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst    773782140                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total       773782140                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data       72065412                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          72065412                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          193445548                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           57735069                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             251180617                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          193445535                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           57735068                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             251180603                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          18976439                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             18976439                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data              22406                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                 22406                       # Number of other requests responded to by this memory
 system.physmem.bw_read::cpu.inst           7999985319                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2310345275                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10310330594                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2310345420                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10310330739                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst      7999985319                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total         7999985319                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           745070440                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              745070440                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           745070490                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              745070490                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::cpu.inst          7999985319                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3055415715                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11055401034                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3055415910                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11055401229                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
-system.cpu.numCycles                        193445904                       # number of cpu cycles simulated
+system.cpu.numCycles                        193445891                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   193444531                       # Number of instructions committed
-system.cpu.committedOps                     193444769                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.committedInsts                   193444518                       # Number of instructions committed
+system.cpu.committedOps                     193444756                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             167974806                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
 system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8665107                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8665106                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    167974806                       # number of integer instructions
 system.cpu.num_fp_insts                       1970372                       # number of float instructions
-system.cpu.num_int_register_reads           352617963                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          163060137                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           352617941                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163060124                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      76733959                       # number of memory refs
-system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_mem_refs                      76733958                       # number of memory refs
+system.cpu.num_load_insts                    57735091                       # Number of load instructions
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  193445904                       # Number of busy cycles
+system.cpu.num_busy_cycles                  193445891                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index fd32216ef27ed4f43cddea923f4fc5bc86f07c84..27af806dde477ec647db7b110f57edcef1dacdfc 100644 (file)
@@ -158,7 +158,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 123985114559d0a17c0b96cb1c8bde4ef9dfd541..d049db054e9d47505e8ab05e61a704ad87625517 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 12:35:14
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:21:48
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -23,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
 info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270628681000 because target called exit()
+122 123 124 Exiting @ tick 270628667000 because target called exit()
index 23f251d47991a36f91ea2a79367a7514de5c0d09..9d89c8f58cd8bed4bc45a85715c8d26529617391 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.270629                       # Number of seconds simulated
-sim_ticks                                270628681000                       # Number of ticks simulated
-final_tick                               270628681000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                270628667000                       # Number of ticks simulated
+final_tick                               270628667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1015199                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1015200                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1420261450                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 225612                       # Number of bytes of host memory used
-host_seconds                                   190.55                       # Real time elapsed on the host
-sim_insts                                   193444531                       # Number of instructions simulated
-sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1532509                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1532510                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2143977461                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235212                       # Number of bytes of host memory used
+host_seconds                                   126.23                       # Real time elapsed on the host
+sim_insts                                   193444518                       # Number of instructions simulated
+sim_ops                                     193444756                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            230208                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            100864                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               331072                       # Number of bytes read from this memory
@@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst              850642                       # To
 system.physmem.bw_total::cpu.data              372703                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                1223344                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  401                       # Number of system calls
-system.cpu.numCycles                        541257362                       # number of cpu cycles simulated
+system.cpu.numCycles                        541257334                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   193444531                       # Number of instructions committed
-system.cpu.committedOps                     193444769                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
+system.cpu.committedInsts                   193444518                       # Number of instructions committed
+system.cpu.committedOps                     193444756                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             167974806                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
 system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8665107                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    167974818                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8665106                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    167974806                       # number of integer instructions
 system.cpu.num_fp_insts                       1970372                       # number of float instructions
-system.cpu.num_int_register_reads           352617963                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          163060136                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           352617941                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          163060123                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3181089                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             2974850                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      76733959                       # number of memory refs
-system.cpu.num_load_insts                    57735092                       # Number of load instructions
+system.cpu.num_mem_refs                      76733958                       # number of memory refs
+system.cpu.num_load_insts                    57735091                       # Number of load instructions
 system.cpu.num_store_insts                   18998867                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  541257362                       # Number of busy cycles
+system.cpu.num_busy_cycles                  541257334                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                  10362                       # number of replacements
-system.cpu.icache.tagsinuse               1591.549936                       # Cycle average of tags in use
-system.cpu.icache.total_refs                193433261                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1591.550018                       # Cycle average of tags in use
+system.cpu.icache.total_refs                193433248                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               15741.639079                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               15741.638021                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1591.549936                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst    1591.550018                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.777124                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.777124                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    193433261                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       193433261                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     193433261                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        193433261                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    193433261                       # number of overall hits
-system.cpu.icache.overall_hits::total       193433261                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    193433248                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       193433248                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     193433248                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        193433248                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    193433248                       # number of overall hits
+system.cpu.icache.overall_hits::total       193433248                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst        12288                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total         12288                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst        12288                       # number of demand (read+write) misses
@@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    323106000
 system.cpu.icache.demand_miss_latency::total    323106000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    323106000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    323106000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    193445549                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    193445549                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    193445549                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    193445549                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    193445549                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    193445549                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    193445536                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    193445536                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    193445536                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    193445536                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    193445536                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    193445536                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000064                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000064                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000064                       # miss rate for demand accesses
@@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594
 system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      2                       # number of replacements
-system.cpu.dcache.tagsinuse               1237.179086                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 76732338                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1237.179149                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 76732337                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               48688.031726                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               48688.031091                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1237.179086                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data    1237.179149                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.302046                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.302046                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     57734571                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        57734571                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     57734570                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        57734570                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       18975362                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data        22405                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total           22405                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data      76709933                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         76709933                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     76709933                       # number of overall hits
-system.cpu.dcache.overall_hits::total        76709933                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      76709932                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         76709932                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     76709932                       # number of overall hits
+system.cpu.dcache.overall_hits::total        76709932                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           498                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         1077                       # number of WriteReq misses
@@ -167,16 +167,16 @@ system.cpu.dcache.demand_miss_latency::cpu.data     88200000
 system.cpu.dcache.demand_miss_latency::total     88200000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data     88200000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     88200000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     57735069                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     57735069                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     57735068                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     57735068                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     18976439                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     18976439                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data        22406                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total        22406                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     76711508                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     76711508                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     76711508                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     76711508                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     76711507                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     76711507                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     76711507                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     76711507                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000009                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000009                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000057                       # miss rate for WriteReq accesses
@@ -249,14 +249,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2678.289467                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2678.289604                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    8691                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  4097                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.121308                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks     0.000456                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2275.240506                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    403.048505                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2275.240623                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    403.048526                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.069435                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
index c72ea59c4cfeaf28633fbf13d788ca1397ba8571..1bbc054557032f155431275a42e5f440a4ca1fa2 100644 (file)
@@ -510,7 +510,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
@@ -533,7 +533,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 6f015db372eca7fba801311a6095b1c30a89a1dc..4fc266b675f69d3e4b158a976e7015e5ab14f036 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 14:16:35
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 19:40:50
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -24,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 87870590500 because target called exit()
+122 123 124 Exiting @ tick 87745680500 because target called exit()
index d6435aa8fe9dbcfc5d74830f8e4980cc39900d83..a2fae1867889dae06bf170e5198b5c295c54c1f2 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.087871                       # Number of seconds simulated
-sim_ticks                                 87870590500                       # Number of ticks simulated
-final_tick                                87870590500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.087746                       # Number of seconds simulated
+sim_ticks                                 87745680500                       # Number of ticks simulated
+final_tick                                87745680500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71260                       # Simulator instruction rate (inst/s)
-host_op_rate                                   119437                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               47410913                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239040                       # Number of bytes of host memory used
-host_seconds                                  1853.38                       # Real time elapsed on the host
-sim_insts                                   132071227                       # Number of instructions simulated
-sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst            219328                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data            125312                       # Number of bytes read from this memory
-system.physmem.bytes_read::total               344640                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst       219328                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total          219328                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst               3427                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1958                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  5385                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2496034                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data              1426097                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                 3922131                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2496034                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2496034                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2496034                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data             1426097                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                3922131                       # Total bandwidth to/from this memory (bytes/s)
+host_inst_rate                                  74091                       # Simulator instruction rate (inst/s)
+host_op_rate                                   124183                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               49224615                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243944                       # Number of bytes of host memory used
+host_seconds                                  1782.56                       # Real time elapsed on the host
+sim_insts                                   132071192                       # Number of instructions simulated
+sim_ops                                     221362960                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst            219904                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data            125632                       # Number of bytes read from this memory
+system.physmem.bytes_read::total               345536                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst       219904                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total          219904                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst               3436                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1963                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  5399                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst              2506152                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              1431774                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                 3937926                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2506152                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2506152                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2506152                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             1431774                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                3937926                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        175741182                       # number of cpu cycles simulated
+system.cpu.numCycles                        175491362                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                 20899544                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted           20899544                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect            2209301                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups              15564510                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                 13831117                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                 20912942                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted           20912942                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect            2216763                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups              15581100                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                 13825679                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles           27321618                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                      227238507                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                    20899544                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches           13831117                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                      59893533                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                19501221                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles               71423982                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                  856                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles          5992                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                  25806035                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                465205                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples          175660343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              2.136482                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             3.300848                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles           27332947                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                      227227686                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                    20912942                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches           13825679                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                      59890374                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                19506044                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles               71169937                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                  648                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles          5818                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                  25808663                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                466739                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples          175411287                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              2.139847                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             3.302571                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                117444586     66.86%     66.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                  3198914      1.82%     68.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                  2491940      1.42%     70.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                  3160979      1.80%     71.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                  3538324      2.01%     73.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                  3753773      2.14%     76.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                  4538217      2.58%     78.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                  2790941      1.59%     80.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                 34742669     19.78%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                117195884     66.81%     66.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                  3196193      1.82%     68.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                  2495974      1.42%     70.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                  3146701      1.79%     71.85% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                  3544894      2.02%     73.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                  3750522      2.14%     76.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                  4536949      2.59%     78.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                  2782229      1.59%     80.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                 34761941     19.82%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total            175660343                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.118922                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.293029                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                 40683921                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles              61195549                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                  46567945                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles              10198566                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles               17014362                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts              366345235                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles               17014362                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                 48576080                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                16382165                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles          23120                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                  48162732                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles              45501884                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts              357078991                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    31                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents               20682611                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents              22563031                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents             2159                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands           507023115                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups            1130829367                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups       1120559538                       # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups          10269829                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps             320143989                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                186879126                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts               1752                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts           1748                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                  95224460                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads             89733433                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores            33126423                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads          59021419                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores         19494501                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                  344814343                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                7981                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                 271092174                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued            252461                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined       122957683                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined    297045432                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved           6735                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples     175660343                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         1.543275                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.467777                       # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total            175411287                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.119168                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.294808                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                 40672745                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles              60972096                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                  46577224                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles              10177659                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles               17011563                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts              366355504                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles               17011563                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                 48566329                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                16269709                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles          22974                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                  48161797                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles              45378915                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts              357087422                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                    17                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents               20597536                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents              22542401                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents             2240                       # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands           506970122                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups            1130784117                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups       1120479639                       # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups          10304478                       # Number of floating rename lookups
+system.cpu.rename.CommittedMaps             320143897                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                186826225                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts               1722                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts           1714                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                  95149637                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads             89685413                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores            33120690                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads          58937447                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores         19448557                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                  344768238                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                7633                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                 271173389                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued            254823                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined       122910358                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined    296566546                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved           6387                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples     175411287                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.545929                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.469162                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0            49300631     28.07%     28.07% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1            52565821     29.92%     57.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2            34438082     19.60%     77.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3            18985110     10.81%     88.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4            12671961      7.21%     95.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5             4951895      2.82%     98.44% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6             2092177      1.19%     99.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7              542850      0.31%     99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8              111816      0.06%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0            49124172     28.01%     28.01% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1            52503398     29.93%     57.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2            34371281     19.59%     77.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3            18965832     10.81%     88.34% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4            12724485      7.25%     95.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5             4970567      2.83%     98.43% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6             2095715      1.19%     99.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7              541828      0.31%     99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8              114009      0.06%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total       175660343                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total       175411287                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                   90987      3.50%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                2226720     85.76%     89.26% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                278883     10.74%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                   95040      3.65%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      3.65% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                2235381     85.95%     89.60% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                270412     10.40%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass           1212971      0.45%      0.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu             176440740     65.09%     65.53% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass           1212866      0.45%      0.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu             176481640     65.08%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntMult                    0      0.00%     65.53% # Type of FU issued
 system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     65.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd             1591628      0.59%     66.12% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd             1593197      0.59%     66.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     66.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     66.12% # Type of FU issued
 system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     66.12% # Type of FU issued
@@ -187,160 +187,160 @@ system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     66.12% # Ty
 system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     66.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     66.12% # Type of FU issued
 system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     66.12% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead             68336239     25.21%     91.33% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite            23510596      8.67%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead             68356368     25.21%     91.32% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite            23529318      8.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total              271092174                       # Type of FU issued
-system.cpu.iq.rate                           1.542565                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                     2596590                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.009578                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads          715388458                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes         463212218                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses    263468773                       # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads             5305284                       # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes            4868318                       # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses      2548590                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses              269817574                       # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses                 2658219                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads         18900853                       # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total              271173389                       # Type of FU issued
+system.cpu.iq.rate                           1.545224                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                     2600833                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.009591                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads          715305678                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes         463103362                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses    263539409                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads             5308043                       # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes            4883539                       # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses      2551351                       # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses              269902017                       # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses                 2659339                       # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads         18957330                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads     33083843                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses        30126                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation       305710                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores     12610707                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads     33035827                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses        30313                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation       305871                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores     12604974                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads        47697                       # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads        47688                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles               17014362                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                  531971                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                245364                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts           344822324                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts            299116                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts              89733433                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts             33126423                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts               1715                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                 158423                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                 34384                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents         305710                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect        1300553                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect      1025953                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              2326506                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts             267978293                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts              67258020                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts           3113881                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles               17011563                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                  523331                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                253149                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts           344775871                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts            305918                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts              89685413                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts             33120690                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts               1684                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                 166880                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                 32620                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents         305871                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect        1304049                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect      1033069                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts              2337118                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts             268044549                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts              67281784                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts           3128840                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                     90379162                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                 14791945                       # Number of branches executed
-system.cpu.iew.exec_stores                   23121142                       # Number of stores executed
-system.cpu.iew.exec_rate                     1.524846                       # Inst execution rate
-system.cpu.iew.wb_sent                      266905236                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                     266017363                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                 214552655                       # num instructions producing a value
-system.cpu.iew.wb_consumers                 504482299                       # num instructions consuming a value
+system.cpu.iew.exec_refs                     90419534                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                 14798772                       # Number of branches executed
+system.cpu.iew.exec_stores                   23137750                       # Number of stores executed
+system.cpu.iew.exec_rate                     1.527395                       # Inst execution rate
+system.cpu.iew.wb_sent                      266978184                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                     266090760                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                 214617061                       # num instructions producing a value
+system.cpu.iew.wb_consumers                 504567875                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       1.513688                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.425293                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       1.516261                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.425348                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      132071227                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps        221363017                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts       123572958                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts      132071192                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        221362960                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts       123521765                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts           2210019                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples    158645981                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     1.395327                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.792270                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts           2217341                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples    158399724                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     1.397496                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.795426                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0     54337756     34.25%     34.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1     60487783     38.13%     72.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2     15594396      9.83%     82.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3     12721179      8.02%     90.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4      4547355      2.87%     93.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5      2966330      1.87%     94.96% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6      2094139      1.32%     96.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7      1239343      0.78%     97.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8      4657700      2.94%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0     54208957     34.22%     34.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1     60399478     38.13%     72.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2     15563923      9.83%     82.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3     12697970      8.02%     90.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4      4547982      2.87%     93.07% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5      2968547      1.87%     94.94% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6      2080222      1.31%     96.25% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7      1235429      0.78%     97.03% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8      4697216      2.97%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total    158645981                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts            132071227                       # Number of instructions committed
-system.cpu.commit.committedOps              221363017                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total    158399724                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts            132071192                       # Number of instructions committed
+system.cpu.commit.committedOps              221362960                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                       77165306                       # Number of memory references committed
-system.cpu.commit.loads                      56649590                       # Number of loads committed
+system.cpu.commit.refs                       77165302                       # Number of memory references committed
+system.cpu.commit.loads                      56649586                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                   12326943                       # Number of branches committed
+system.cpu.commit.branches                   12326938                       # Number of branches committed
 system.cpu.commit.fp_insts                    2162459                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                 220339606                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                 220339549                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events               4657700                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events               4697216                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                    498924256                       # The number of ROB reads
-system.cpu.rob.rob_writes                   706924128                       # The number of ROB writes
-system.cpu.timesIdled                            1775                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           80839                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   132071227                       # Number of Instructions Simulated
-system.cpu.committedOps                     221363017                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total             132071227                       # Number of Instructions Simulated
-system.cpu.cpi                               1.330655                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.330655                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.751510                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.751510                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                657690172                       # number of integer regfile reads
-system.cpu.int_regfile_writes               365563414                       # number of integer regfile writes
-system.cpu.fp_regfile_reads                   3506965                       # number of floating regfile reads
-system.cpu.fp_regfile_writes                  2222676                       # number of floating regfile writes
-system.cpu.misc_regfile_reads               139526646                       # number of misc regfile reads
+system.cpu.rob.rob_reads                    498587233                       # The number of ROB reads
+system.cpu.rob.rob_writes                   706819353                       # The number of ROB writes
+system.cpu.timesIdled                            1778                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           80075                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                   132071192                       # Number of Instructions Simulated
+system.cpu.committedOps                     221362960                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             132071192                       # Number of Instructions Simulated
+system.cpu.cpi                               1.328763                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.328763                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.752579                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.752579                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                657890956                       # number of integer regfile reads
+system.cpu.int_regfile_writes               365630254                       # number of integer regfile writes
+system.cpu.fp_regfile_reads                   3509539                       # number of floating regfile reads
+system.cpu.fp_regfile_writes                  2224150                       # number of floating regfile writes
+system.cpu.misc_regfile_reads               139559443                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    844                       # number of misc regfile writes
-system.cpu.icache.replacements                   5610                       # number of replacements
-system.cpu.icache.tagsinuse               1629.478377                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 25796956                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                   7578                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                3404.190552                       # Average number of references to valid blocks.
+system.cpu.icache.replacements                   5776                       # number of replacements
+system.cpu.icache.tagsinuse               1633.892050                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 25799407                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                   7743                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                3331.965259                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1629.478377                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.795644                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.795644                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst     25796956                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total        25796956                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst      25796956                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total         25796956                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst     25796956                       # number of overall hits
-system.cpu.icache.overall_hits::total        25796956                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst         9079                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total          9079                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst         9079                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total           9079                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst         9079                       # number of overall misses
-system.cpu.icache.overall_misses::total          9079                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    194493000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    194493000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    194493000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    194493000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    194493000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    194493000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst     25806035                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total     25806035                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst     25806035                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total     25806035                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst     25806035                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total     25806035                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000352                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.000352                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.000352                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.000352                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.000352                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.000352                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21422.293204                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21422.293204                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21422.293204                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21422.293204                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21422.293204                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 21422.293204                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1633.892050                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.797799                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.797799                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     25799407                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        25799407                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      25799407                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         25799407                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     25799407                       # number of overall hits
+system.cpu.icache.overall_hits::total        25799407                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         9256                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          9256                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         9256                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           9256                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         9256                       # number of overall misses
+system.cpu.icache.overall_misses::total          9256                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    196263500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    196263500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    196263500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    196263500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    196263500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    196263500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     25808663                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     25808663                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     25808663                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     25808663                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     25808663                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     25808663                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000359                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.000359                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000359                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.000359                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000359                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.000359                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21203.921780                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 21203.921780                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21203.921780                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 21203.921780                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21203.921780                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 21203.921780                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -349,94 +349,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1363                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total         1363                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst         1363                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total         1363                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst         1363                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total         1363                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7716                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total         7716                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst         7716                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total         7716                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst         7716                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total         7716                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    136466500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    136466500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    136466500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    136466500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    136466500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    136466500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000299                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.000299                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000299                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.000299                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17686.171591                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 17686.171591                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17686.171591                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 17686.171591                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1390                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1390                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1390                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1390                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1390                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1390                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         7866                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         7866                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         7866                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         7866                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         7866                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         7866                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    137281500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    137281500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    137281500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    137281500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    137281500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    137281500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000305                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000305                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000305                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.000305                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000305                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.000305                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17452.517162                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17452.517162                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17452.517162                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 17452.517162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17452.517162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 17452.517162                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.replacements                     57                       # number of replacements
-system.cpu.dcache.tagsinuse               1427.277065                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 68700923                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                   1995                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               34436.552882                       # Average number of references to valid blocks.
+system.cpu.dcache.replacements                     56                       # number of replacements
+system.cpu.dcache.tagsinuse               1432.539933                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 68667989                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                   2001                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs               34316.836082                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1427.277065                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.348456                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.348456                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     48186723                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        48186723                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     20514032                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       20514032                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      68700755                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         68700755                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     68700755                       # number of overall hits
-system.cpu.dcache.overall_hits::total        68700755                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          751                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           751                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data         1698                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total         1698                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         2449                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           2449                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         2449                       # number of overall misses
-system.cpu.dcache.overall_misses::total          2449                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     26925000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     26925000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     64818000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     64818000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     91743000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     91743000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     91743000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     91743000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     48187474                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     48187474                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.occ_blocks::cpu.data    1432.539933                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.349741                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.349741                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     48153803                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        48153803                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514043                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514043                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      68667846                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         68667846                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     68667846                       # number of overall hits
+system.cpu.dcache.overall_hits::total        68667846                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          738                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           738                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1687                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1687                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2425                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2425                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2425                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2425                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     26760000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     26760000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     64476000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     64476000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     91236000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     91236000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     91236000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     91236000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     48154541                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     48154541                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     68703204                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     68703204                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     68703204                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     68703204                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000016                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.000016                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000083                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.000083                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.000036                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.000036                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.000036                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.000036                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35852.197071                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35852.197071                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38173.144876                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38173.144876                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37461.412822                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37461.412822                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37461.412822                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37461.412822                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data     68670271                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     68670271                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     68670271                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     68670271                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000015                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.000015                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000082                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.000082                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000035                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.000035                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000035                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.000035                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36260.162602                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36260.162602                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38219.324244                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38219.324244                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37623.092784                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37623.092784                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37623.092784                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37623.092784                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -447,136 +447,136 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
 system.cpu.dcache.writebacks::total                13                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          310                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          310                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          295                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          295                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data            4                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total            4                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          314                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          314                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          314                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          314                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          441                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          441                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1694                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total         1694                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data         2135                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total         2135                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data         2135                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total         2135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     15484500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     15484500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59638500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     59638500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     75123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     75123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     75123000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     75123000                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::cpu.data          299                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          299                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          299                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          299                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          443                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          443                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1683                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1683                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2126                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2126                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2126                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2126                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     15550500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     15550500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     59322000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     59322000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     74872500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     74872500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     74872500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     74872500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000083                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000083                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000082                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000082                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000031                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000031                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000031                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35112.244898                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35112.244898                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35205.726092                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35205.726092                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35186.416862                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 35186.416862                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35186.416862                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 35186.416862                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35102.708804                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35102.708804                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35247.771836                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35247.771836                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35217.544685                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 35217.544685                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35217.544685                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 35217.544685                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2583.556674                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                    4185                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                  3837                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  1.090696                       # Average number of references to valid blocks.
+system.cpu.l2cache.tagsinuse              2579.346605                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                    4342                       # Total number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                  3848                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  1.128378                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::writebacks     1.869475                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   2280.566529                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    301.120670                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::writebacks     0.000057                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.inst     0.069597                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.009189                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.078844                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits::cpu.inst         4151                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data           31                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total           4182                       # number of ReadReq hits
+system.cpu.l2cache.occ_blocks::writebacks     1.813756                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2277.631269                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    299.901579                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000055                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.069508                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.009152                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.078715                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         4307                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           32                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           4339                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
 system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.inst         4151                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data           39                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total            4190                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.inst         4151                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data           39                       # number of overall hits
-system.cpu.l2cache.overall_hits::total           4190                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst         3427                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          409                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total         3836                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data          138                       # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total          138                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data         1549                       # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total         1549                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst         3427                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data         1958                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total          5385                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst         3427                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data         1958                       # number of overall misses
-system.cpu.l2cache.overall_misses::total         5385                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120377000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14853500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total    135230500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     53266000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     53266000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    120377000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     68119500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    188496500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    120377000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     68119500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    188496500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst         7578                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          440                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total         8018                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_hits::cpu.inst         4307                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           40                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            4347                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         4307                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           40                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           4347                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3436                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          410                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3846                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          123                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          123                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1553                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1553                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3436                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1963                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5399                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3436                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1963                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5399                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120547500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14888000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    135435500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     53463500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     53463500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    120547500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     68351500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    188899000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    120547500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     68351500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    188899000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         7743                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          442                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         8185                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.data          138                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::total          138                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.data         1557                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::total         1557                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst         7578                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data         1997                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total         9575                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst         7578                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data         1997                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total         9575                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.452230                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.929545                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.478424                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          123                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          123                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1561                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1561                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         7743                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2003                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         9746                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         7743                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2003                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         9746                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.443756                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.927602                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.469884                       # miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994862                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::total     0.994862                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.452230                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::cpu.data     0.980471                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.562402                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.452230                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::cpu.data     0.980471                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.562402                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35126.057776                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36316.625917                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 35252.997914                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34387.346675                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34387.346675                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35126.057776                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34790.347293                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 35003.992572                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35126.057776                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34790.347293                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 35003.992572                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994875                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::total     0.994875                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.443756                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980030                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::total     0.553971                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.443756                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980030                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::total     0.553971                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35083.672875                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36312.195122                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 35214.638586                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34425.949775                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34425.949775                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35083.672875                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34819.918492                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34987.775514                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35083.672875                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34819.918492                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34987.775514                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -585,58 +585,58 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3427                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          409                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total         3836                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          138                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total          138                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1549                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total         1549                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst         3427                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data         1958                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total         5385                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst         3427                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data         1958                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total         5385                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    109445000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     13559500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total    123004500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      4278000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      4278000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48463000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48463000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    109445000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     62022500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    171467500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    109445000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     62022500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    171467500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.929545                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.478424                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3436                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          410                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3846                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          123                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          123                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1553                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1553                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3436                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1963                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5399                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3436                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1963                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5399                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    109561500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     13591500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    123153000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      3813000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      3813000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48619000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48619000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    109561500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     62210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    171772000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    109561500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     62210500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    171772000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.443756                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.927602                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.469884                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994862                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994862                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980471                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.562402                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.452230                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980471                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.562402                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33152.811736                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32065.823775                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994875                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.994875                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.443756                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980030                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.553971                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.443756                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980030                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.553971                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31886.350407                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        33150                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32021.060842                       # average ReadReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31286.636540                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31286.636540                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31676.455567                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31841.689879                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31936.095711                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31676.455567                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31841.689879                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31306.503542                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31306.503542                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31886.350407                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31691.543556                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31815.521393                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31886.350407                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31691.543556                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31815.521393                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 5b797a4385b47dda8befc01030ae8b2138cb9361..a704c39273db38af59513f634f363394edc8b640 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index f20b231191b864990e7cfb1e0a33a7c1758da95d..7016aa1686dac084157862df0c81458834278b6c 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 16:58:23
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 20:10:43
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
@@ -24,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 131393100000 because target called exit()
+122 123 124 Exiting @ tick 131393067000 because target called exit()
index 52d17f26ba193ea6a3dbe432f082411c79675666..3993acb05f6cd0f548932bd350f8176c8586a528 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.131393                       # Number of seconds simulated
-sim_ticks                                131393100000                       # Number of ticks simulated
-final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                131393067000                       # Number of ticks simulated
+final_tick                               131393067000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1290267                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2162601                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1283641901                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223844                       # Number of bytes of host memory used
-host_seconds                                   102.36                       # Real time elapsed on the host
-sim_insts                                   132071228                       # Number of instructions simulated
-sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst        1387955288                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data         310423754                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1698379042                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst   1387955288                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1387955288                       # Number of instructions bytes read from this memory
+host_inst_rate                                1300121                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2179118                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1293445391                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231396                       # Number of bytes of host memory used
+host_seconds                                   101.58                       # Real time elapsed on the host
+sim_insts                                   132071193                       # Number of instructions simulated
+sim_ops                                     221362961                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst        1387954936                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data         310423750                       # Number of bytes read from this memory
+system.physmem.bytes_read::total           1698378686                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst   1387954936                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1387954936                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data       99822189                       # Number of bytes written to this memory
 system.physmem.bytes_written::total          99822189                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst          173494411                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data           56682008                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             230176419                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst          173494367                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data           56682004                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             230176371                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data          20515730                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total             20515730                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst          10563380330                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2362557501                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             12925937831                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst     10563380330                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total        10563380330                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data           759721698                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total              759721698                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst         10563380330                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3122279199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            13685659529                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst          10563380304                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2362558064                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             12925938368                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst     10563380304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total        10563380304                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data           759721889                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total              759721889                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst         10563380304                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3122279953                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            13685660256                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        262786201                       # number of cpu cycles simulated
+system.cpu.numCycles                        262786135                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   132071228                       # Number of instructions committed
-system.cpu.committedOps                     221363018                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.committedInsts                   132071193                       # Number of instructions committed
+system.cpu.committedOps                     221362961                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             220339550                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    220339550                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           705008823                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          318312586                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           705008645                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          318312494                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      77165306                       # number of memory refs
-system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_mem_refs                      77165302                       # number of memory refs
+system.cpu.num_load_insts                    56649586                       # Number of load instructions
 system.cpu.num_store_insts                   20515716                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  262786201                       # Number of busy cycles
+system.cpu.num_busy_cycles                  262786135                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 1ebce5cb8d72e189d42c55271555ceb3ca5d3e1c..6a05638c8495fcf3ebb15c34a5bba3bc4e70ec02 100644 (file)
@@ -179,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
+cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 2dfefd0be8b47d4bfce1752520f3ca666133948c..54930ae6e299f10440c72740a6fc57ac8cc92f5f 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 14:50:18
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 20:12:35
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
@@ -24,4 +24,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 250981042000 because target called exit()
+122 123 124 Exiting @ tick 250980994000 because target called exit()
index f0166c804e4663fb09f800443881e192aa82fd5e..b04007fc911fc32e26bef01abd7958a412f27d17 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.250981                       # Number of seconds simulated
-sim_ticks                                250981042000                       # Number of ticks simulated
-final_tick                               250981042000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                250980994000                       # Number of ticks simulated
+final_tick                               250980994000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 522050                       # Simulator instruction rate (inst/s)
-host_op_rate                                   875003                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              992076486                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235972                       # Number of bytes of host memory used
-host_seconds                                   252.99                       # Real time elapsed on the host
-sim_insts                                   132071228                       # Number of instructions simulated
-sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 746540                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1251266                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1418683559                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 239848                       # Number of bytes of host memory used
+host_seconds                                   176.91                       # Real time elapsed on the host
+sim_insts                                   132071193                       # Number of instructions simulated
+sim_ops                                     221362961                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            181760                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            121280                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               303040                       # Number of bytes read from this memory
@@ -28,43 +28,43 @@ system.physmem.bw_total::cpu.inst              724198                       # To
 system.physmem.bw_total::cpu.data              483224                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                1207422                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.numCycles                        501962084                       # number of cpu cycles simulated
+system.cpu.numCycles                        501961988                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                   132071228                       # Number of instructions committed
-system.cpu.committedOps                     221363018                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
+system.cpu.committedInsts                   132071193                       # Number of instructions committed
+system.cpu.committedOps                     221362961                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses             220339550                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts      8268471                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                    220339607                       # number of integer instructions
+system.cpu.num_conditional_control_insts      8268466                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                    220339550                       # number of integer instructions
 system.cpu.num_fp_insts                       2162459                       # number of float instructions
-system.cpu.num_int_register_reads           705008823                       # number of times the integer registers were read
-system.cpu.num_int_register_writes          318312586                       # number of times the integer registers were written
+system.cpu.num_int_register_reads           705008645                       # number of times the integer registers were read
+system.cpu.num_int_register_writes          318312494                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads              3037165                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes             1831403                       # number of times the floating registers were written
-system.cpu.num_mem_refs                      77165306                       # number of memory refs
-system.cpu.num_load_insts                    56649590                       # Number of load instructions
+system.cpu.num_mem_refs                      77165302                       # number of memory refs
+system.cpu.num_load_insts                    56649586                       # Number of load instructions
 system.cpu.num_store_insts                   20515716                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                  501962084                       # Number of busy cycles
+system.cpu.num_busy_cycles                  501961988                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                   2836                       # number of replacements
-system.cpu.icache.tagsinuse               1455.271683                       # Cycle average of tags in use
-system.cpu.icache.total_refs                173489718                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse               1455.271959                       # Cycle average of tags in use
+system.cpu.icache.total_refs                173489674                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs               36959.888794                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs               36959.879421                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst    1455.271683                       # Average occupied blocks per requestor
+system.cpu.icache.occ_blocks::cpu.inst    1455.271959                       # Average occupied blocks per requestor
 system.cpu.icache.occ_percent::cpu.inst      0.710582                       # Average percentage of cache occupancy
 system.cpu.icache.occ_percent::total         0.710582                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst    173489718                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total       173489718                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst     173489718                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total        173489718                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst    173489718                       # number of overall hits
-system.cpu.icache.overall_hits::total       173489718                       # number of overall hits
+system.cpu.icache.ReadReq_hits::cpu.inst    173489674                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       173489674                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     173489674                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        173489674                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    173489674                       # number of overall hits
+system.cpu.icache.overall_hits::total       173489674                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst         4694                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total          4694                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst         4694                       # number of demand (read+write) misses
@@ -77,12 +77,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst    185042500
 system.cpu.icache.demand_miss_latency::total    185042500                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst    185042500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total    185042500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst    173494412                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total    173494412                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst    173494412                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total    173494412                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst    173494412                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total    173494412                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst    173494368                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    173494368                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    173494368                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    173494368                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    173494368                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    173494368                       # number of overall (read+write) accesses
 system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_miss_rate::total     0.000027                       # miss rate for ReadReq accesses
 system.cpu.icache.demand_miss_rate::cpu.inst     0.000027                       # miss rate for demand accesses
@@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.358756
 system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.358756                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     41                       # number of replacements
-system.cpu.dcache.tagsinuse               1363.438791                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 77195833                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse               1363.439047                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 77195829                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs               40522.746982                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs               40522.744882                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data    1363.438791                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_blocks::cpu.data    1363.439047                       # Average occupied blocks per requestor
 system.cpu.dcache.occ_percent::cpu.data      0.332871                       # Average percentage of cache occupancy
 system.cpu.dcache.occ_percent::total         0.332871                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data     56681681                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        56681681                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     56681677                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        56681677                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20514152                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       20514152                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data      77195833                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         77195833                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     77195833                       # number of overall hits
-system.cpu.dcache.overall_hits::total        77195833                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      77195829                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         77195829                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     77195829                       # number of overall hits
+system.cpu.dcache.overall_hits::total        77195829                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          327                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           327                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data         1578                       # number of WriteReq misses
@@ -161,14 +161,14 @@ system.cpu.dcache.demand_miss_latency::cpu.data    106263000
 system.cpu.dcache.demand_miss_latency::total    106263000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data    106263000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total    106263000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     56682008                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     56682008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     56682004                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     56682004                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     77197738                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     77197738                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     77197738                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     77197738                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     77197734                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     77197734                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     77197734                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     77197734                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000006                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.000006                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000077                       # miss rate for WriteReq accesses
@@ -229,14 +229,14 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.839895
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.839895                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse              2058.146079                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse              2058.146468                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                    1862                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.588496                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.occ_blocks::writebacks     0.021788                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.inst   1829.948431                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    228.175860                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1829.948778                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    228.175901                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.inst     0.055846                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
index e1fc4e09c8f25350e663a921068c30e336f03de1..741def84635b8f8a5810772df08543765cddebf8 100644 (file)
@@ -214,7 +214,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index da63093c15bce65097e0adf4c6e4d694c0d9501e..da760535c94b93d55538c18e3e27ab3e8cf15b9d 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:08:18
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:12
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 21985500 because target called exit()
+Exiting @ tick 21979500 because target called exit()
index b38d65b684d854881645d642fa82bfa7af421eb0..9447623bfaf08fc8b314100997fda8d2b8e713ec 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000022                       # Number of seconds simulated
-sim_ticks                                    21985500                       # Number of ticks simulated
-final_tick                                   21985500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    21979500                       # Number of ticks simulated
+final_tick                                   21979500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65949                       # Simulator instruction rate (inst/s)
-host_op_rate                                    65938                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              226330541                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218192                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  39186                       # Simulator instruction rate (inst/s)
+host_op_rate                                    39182                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              134757534                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222636                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30016                       # Number of bytes read from this memory
@@ -19,30 +19,30 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   469                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            876213868                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            489049601                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1365263469                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       876213868                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          876213868                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           876213868                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           489049601                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1365263469                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            876453059                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            489183102                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1365636161                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       876453059                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          876453059                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           876453059                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           489183102                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1365636161                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1186                       # DTB read hits
+system.cpu.dtb.read_hits                         1184                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1193                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1191                       # DTB read accesses
 system.cpu.dtb.write_hits                         900                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     903                       # DTB write accesses
-system.cpu.dtb.data_hits                         2086                       # DTB hits
+system.cpu.dtb.data_hits                         2084                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2096                       # DTB accesses
+system.cpu.dtb.data_accesses                     2094                       # DTB accesses
 system.cpu.itb.fetch_hits                         908                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
@@ -60,83 +60,83 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            43972                       # number of cpu cycles simulated
+system.cpu.numCycles                            43960                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1607                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted         1126                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect          712                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.lookups              1606                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted         1125                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect          713                       # Number of conditional branches incorrect
 system.cpu.branch_predictor.BTBLookups           1186                       # Number of BTB lookups
 system.cpu.branch_predictor.BTBHits               314                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS               126                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            0                       # Number of incorrect RAS predictions.
 system.cpu.branch_predictor.BTBHitPct       26.475548                       # BTB Hit Percentage
 system.cpu.branch_predictor.predictedTaken          464                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         1143                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5212                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites         4580                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         9792                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.predictedNotTaken         1142                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5205                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites         4567                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         9772                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            8                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            2                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses           10                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           2971                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       2183                       # Number of Address Generations
+system.cpu.regfile_manager.regForwards           2961                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       2181                       # Number of Address Generations
 system.cpu.execution_unit.predictedTakenIncorrect          284                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          367                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted            651                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted               401                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     61.882129                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions             4474                       # Number of Instructions Executed.
+system.cpu.execution_unit.predictedNotTakenIncorrect          368                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted            652                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted               399                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     62.036156                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions             4463                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 1                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         12078                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         12066                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.timesIdled                             536                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           36557                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             7415                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         16.863004                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              1185                       # Number of Load instructions committed
+system.cpu.idleCycles                           36556                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             7404                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         16.842584                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              1183                       # Number of Load instructions committed
 system.cpu.comStores                              865                       # Number of Store instructions committed
-system.cpu.comBranches                           1051                       # Number of Branches instructions committed
+system.cpu.comBranches                           1050                       # Number of Branches instructions committed
 system.cpu.comNops                                 17                       # Number of Nop instructions committed
 system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               3265                       # Number of Integer instructions committed
+system.cpu.comInts                               3254                       # Number of Integer instructions committed
 system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        6404                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          6404                       # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts                        6390                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          6390                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  6404                       # Number of Instructions committed (Total)
-system.cpu.cpi                               6.866334                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total                  6390                       # Number of Instructions committed (Total)
+system.cpu.cpi                               6.879499                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         6.866334                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.145638                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         6.879499                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.145359                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.145638                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    39051                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      4921                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               11.191213                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    40084                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      3888                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                8.841990                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    39791                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      4181                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                9.508323                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    42630                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      1342                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.051942                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    39502                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      4470                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               10.165560                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.145359                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    39048                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      4912                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               11.173794                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    40082                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3878                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                8.821656                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    39789                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      4171                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                9.488171                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    42620                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1340                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                3.048226                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    39501                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      4459                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               10.143312                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                138.644500                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                138.677707                       # Cycle average of tags in use
 system.cpu.icache.total_refs                      557                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    301                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.850498                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     138.644500                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.067698                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.067698                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     138.677707                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.067714                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.067714                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          557                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             557                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           557                       # number of demand (read+write) hits
@@ -213,22 +213,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54614.238411
 system.cpu.icache.overall_avg_mshr_miss_latency::total 54614.238411                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                102.468585                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1702                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.489186                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1700                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  10.130952                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  10.119048                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     102.468585                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025017                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025017                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     102.489186                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025022                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025022                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1086                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1086                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          614                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            614                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1702                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1702                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1702                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1702                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1700                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1700                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1700                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1700                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          251                       # number of WriteReq misses
@@ -245,22 +245,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data     21208000
 system.cpu.dcache.demand_miss_latency::total     21208000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data     21208000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     21208000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081857                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.081857                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2048                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2048                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2048                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2048                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081995                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.081995                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.290173                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.290173                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.169756                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.169756                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.169756                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.169756                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.169922                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.169922                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.169922                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.169922                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61010.309278                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 61010.309278                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60916.334661                       # average WriteReq miss latency
@@ -301,14 +301,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9606000
 system.cpu.dcache.demand_mshr_miss_latency::total      9606000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9606000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      9606000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57994.736842                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57994.736842                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56116.438356                       # average WriteReq mshr miss latency
@@ -319,16 +319,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57178.571429
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 57178.571429                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               194.857279                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               194.900917                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    138.715070                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     56.142209                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004233                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001713                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005947                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    138.748296                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.152621                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004234                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001714                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005948                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
index fb11f0585d9478be44be34ff4fbf7b6b78cfa294..3f0b5bf4d57a6158ac3a6feba93a73de7f9c7300 100644 (file)
@@ -512,7 +512,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 8091027933ec7bdd10ece5262fc30c6cfdc7a081..a77141c3dc9bccfdff20d0ac33d5319f806719b2 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:08:18
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:12
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 12811000 because target called exit()
+Exiting @ tick 12735500 because target called exit()
index 37f1f46b0bb7fc3b597f37cb140c3f5b4429e329..a5b8857d36f87c609660ab9a5cacc7c014435174 100644 (file)
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    12811000                       # Number of ticks simulated
-final_tick                                   12811000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12735500                       # Number of ticks simulated
+final_tick                                   12735500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  61639                       # Simulator instruction rate (inst/s)
-host_op_rate                                    61622                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              123585600                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219212                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        6386                       # Number of instructions simulated
-sim_ops                                          6386                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             20096                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11200                       # Number of bytes read from this memory
+host_inst_rate                                  33074                       # Simulator instruction rate (inst/s)
+host_op_rate                                    33071                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               66088952                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223664                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
+sim_insts                                        6372                       # Number of instructions simulated
+sim_ops                                          6372                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             20032                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             11264                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                31296                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        20096                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           20096                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                314                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                175                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        20032                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           20032                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                313                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                176                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   489                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1568651940                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            874248693                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2442900632                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1568651940                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1568651940                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1568651940                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           874248693                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2442900632                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1572926073                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            884456833                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2457382906                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1572926073                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1572926073                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1572926073                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           884456833                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2457382906                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1966                       # DTB read hits
-system.cpu.dtb.read_misses                         45                       # DTB read misses
+system.cpu.dtb.read_hits                         1978                       # DTB read hits
+system.cpu.dtb.read_misses                         55                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     2011                       # DTB read accesses
-system.cpu.dtb.write_hits                        1059                       # DTB write hits
-system.cpu.dtb.write_misses                        28                       # DTB write misses
+system.cpu.dtb.read_accesses                     2033                       # DTB read accesses
+system.cpu.dtb.write_hits                        1077                       # DTB write hits
+system.cpu.dtb.write_misses                        31                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    1087                       # DTB write accesses
-system.cpu.dtb.data_hits                         3025                       # DTB hits
-system.cpu.dtb.data_misses                         73                       # DTB misses
+system.cpu.dtb.write_accesses                    1108                       # DTB write accesses
+system.cpu.dtb.data_hits                         3055                       # DTB hits
+system.cpu.dtb.data_misses                         86                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     3098                       # DTB accesses
-system.cpu.itb.fetch_hits                        2254                       # ITB hits
-system.cpu.itb.fetch_misses                        39                       # ITB misses
+system.cpu.dtb.data_accesses                     3141                       # DTB accesses
+system.cpu.itb.fetch_hits                        2292                       # ITB hits
+system.cpu.itb.fetch_misses                        40                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    2293                       # ITB accesses
+system.cpu.itb.fetch_accesses                    2332                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,320 +60,320 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            25623                       # number of cpu cycles simulated
+system.cpu.numCycles                            25472                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2750                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1591                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                527                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2077                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      748                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2810                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1639                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                544                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2127                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      764                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      402                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                  69                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               8523                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          15693                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2750                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1150                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2817                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1761                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    996                       # Number of cycles fetch has spent blocked
+system.cpu.BPredUnit.usedRAS                      400                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                  76                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               8490                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          16101                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2810                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1164                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2877                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1816                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    977                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                   25                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           745                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      2254                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   361                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              14299                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.097489                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.491166                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.PendingTrapStallCycles           757                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      2292                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   368                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              14359                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.121318                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.516372                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    11482     80.30%     80.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      287      2.01%     82.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      235      1.64%     83.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      221      1.55%     85.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      257      1.80%     87.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      195      1.36%     88.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      267      1.87%     90.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      172      1.20%     91.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1183      8.27%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    11482     79.96%     79.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      290      2.02%     81.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      231      1.61%     83.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      230      1.60%     85.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      264      1.84%     87.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      193      1.34%     88.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      266      1.85%     90.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      182      1.27%     91.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1221      8.50%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                14299                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.107325                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.612458                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9448                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1035                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2627                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    79                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1110                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  255                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    87                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  14531                       # Number of instructions handled by decode
+system.cpu.fetch.rateDist::total                14359                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.110317                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.632106                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     9433                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1012                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2694                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    70                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1150                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  257                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    88                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  14902                       # Number of instructions handled by decode
 system.cpu.decode.SquashedInsts                   236                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   1110                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9647                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     356                       # Number of cycles rename is blocking
+system.cpu.rename.SquashCycles                   1150                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     9643                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     342                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            379                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2494                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   313                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  13871                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                      7                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   268                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10378                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 17349                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            17332                       # Number of integer rename lookups
+system.cpu.rename.RunCycles                      2542                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   303                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  14192                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                      8                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   256                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               10635                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 17782                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            17765                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                17                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  4583                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5795                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 32                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             26                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       762                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2605                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1307                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                 5                       # Number of conflicting loads.
+system.cpu.rename.CommittedMaps                  4570                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     6065                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 33                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             27                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       736                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2623                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1340                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                 8                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      12446                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      12668                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  30                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     10341                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                37                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            5740                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         3350                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     10483                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                45                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            5989                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         3489                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             13                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         14299                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.723197                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.354818                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         14359                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.730065                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.362537                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                9905     69.27%     69.27% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1622     11.34%     80.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1176      8.22%     88.84% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 704      4.92%     93.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 444      3.11%     96.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 263      1.84%     98.71% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 141      0.99%     99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  34      0.24%     99.93% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  10      0.07%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                9920     69.09%     69.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1630     11.35%     80.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1188      8.27%     88.71% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 708      4.93%     93.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 458      3.19%     96.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 268      1.87%     98.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 142      0.99%     99.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  31      0.22%     99.90% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  14      0.10%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           14299                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           14359                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       8      7.27%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.27% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     65     59.09%     66.36% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    37     33.64%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       8      7.21%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      7.21% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     64     57.66%     64.86% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    39     35.14%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7000     67.69%     67.71% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.72% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.74% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2210     21.37%     89.11% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1126     10.89%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7098     67.71%     67.73% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.74% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2226     21.23%     88.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1154     11.01%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10341                       # Type of FU issued
-system.cpu.iq.rate                           0.403583                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         110                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010637                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              35107                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             18223                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         9409                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  10483                       # Type of FU issued
+system.cpu.iq.rate                           0.411550                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         111                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010589                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              35460                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             18693                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         9514                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  21                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 10                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           10                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  10438                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  10581                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      11                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               72                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1420                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1440                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           19                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          442                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           18                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          475                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1110                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                      39                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                     1                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               12564                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               188                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2605                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1307                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                   1150                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                      28                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                     4                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               12786                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               202                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2623                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1340                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 30                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      0                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                      3                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             19                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            139                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          385                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  524                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  9796                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2022                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               545                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents             18                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            149                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          397                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  546                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  9926                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2044                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               557                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                            88                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3112                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1595                       # Number of branches executed
-system.cpu.iew.exec_stores                       1090                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.382313                       # Inst execution rate
-system.cpu.iew.wb_sent                           9558                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          9419                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4945                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6634                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3155                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1608                       # Number of branches executed
+system.cpu.iew.exec_stores                       1111                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.389683                       # Inst execution rate
+system.cpu.iew.wb_sent                           9680                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          9524                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      5005                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6736                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.367599                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.745402                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.373901                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.743023                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           6403                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps             6403                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            6160                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts           6389                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             6389                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            6396                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               444                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13189                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.485480                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.291478                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               461                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        13209                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.483685                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.282622                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10357     78.53%     78.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1540     11.68%     90.20% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          523      3.97%     94.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          223      1.69%     95.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          163      1.24%     97.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          109      0.83%     97.92% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          106      0.80%     98.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           29      0.22%     98.95% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          139      1.05%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10366     78.48%     78.48% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1544     11.69%     90.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          533      4.04%     94.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          227      1.72%     95.92% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          164      1.24%     97.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          106      0.80%     97.96% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          105      0.79%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           30      0.23%     98.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          134      1.01%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13189                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 6403                       # Number of instructions committed
-system.cpu.commit.committedOps                   6403                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        13209                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                 6389                       # Number of instructions committed
+system.cpu.commit.committedOps                   6389                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2050                       # Number of memory references committed
-system.cpu.commit.loads                          1185                       # Number of loads committed
+system.cpu.commit.refs                           2048                       # Number of memory references committed
+system.cpu.commit.loads                          1183                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       1051                       # Number of branches committed
+system.cpu.commit.branches                       1050                       # Number of branches committed
 system.cpu.commit.fp_insts                         10                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      6321                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      6307                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  127                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   139                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   134                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        25262                       # The number of ROB reads
-system.cpu.rob.rob_writes                       26244                       # The number of ROB writes
-system.cpu.timesIdled                             278                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11324                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        6386                       # Number of Instructions Simulated
-system.cpu.committedOps                          6386                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                  6386                       # Number of Instructions Simulated
-system.cpu.cpi                               4.012371                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.012371                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.249229                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.249229                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    12434                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7077                       # number of integer regfile writes
+system.cpu.rob.rob_reads                        25509                       # The number of ROB reads
+system.cpu.rob.rob_writes                       26731                       # The number of ROB writes
+system.cpu.timesIdled                             274                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           11113                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        6372                       # Number of Instructions Simulated
+system.cpu.committedOps                          6372                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  6372                       # Number of Instructions Simulated
+system.cpu.cpi                               3.997489                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         3.997489                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.250157                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.250157                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    12615                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7161                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         8                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       1                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                      1                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                159.968477                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1800                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    315                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.714286                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                158.802415                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1839                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    314                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   5.856688                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     159.968477                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.078110                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.078110                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1800                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1800                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1800                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1800                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1800                       # number of overall hits
-system.cpu.icache.overall_hits::total            1800                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          454                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           454                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          454                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            454                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          454                       # number of overall misses
-system.cpu.icache.overall_misses::total           454                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16294000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16294000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16294000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16294000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16294000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16294000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2254                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2254                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2254                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2254                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2254                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2254                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.201420                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.201420                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.201420                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.201420                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.201420                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.201420                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35889.867841                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35889.867841                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     158.802415                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.077540                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.077540                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1839                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1839                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1839                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1839                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1839                       # number of overall hits
+system.cpu.icache.overall_hits::total            1839                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          453                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           453                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          453                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            453                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          453                       # number of overall misses
+system.cpu.icache.overall_misses::total           453                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16260000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16260000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16260000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16260000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16260000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16260000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2292                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2292                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2292                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2292                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2292                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2292                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.197644                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.197644                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.197644                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.197644                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.197644                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.197644                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35894.039735                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35894.039735                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35894.039735                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35894.039735                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35894.039735                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35894.039735                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -388,88 +388,88 @@ system.cpu.icache.demand_mshr_hits::cpu.inst          139
 system.cpu.icache.demand_mshr_hits::total          139                       # number of demand (read+write) MSHR hits
 system.cpu.icache.overall_mshr_hits::cpu.inst          139                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          139                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          315                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          315                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          315                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          315                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          315                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          315                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11617000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     11617000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11617000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     11617000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11617000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     11617000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.139752                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.139752                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.139752                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.139752                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          314                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          314                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          314                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11585500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11585500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11585500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11585500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11585500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11585500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.136998                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.136998                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.136998                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.136998                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.136998                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.136998                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36896.496815                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36896.496815                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36896.496815                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36896.496815                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36896.496815                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36896.496815                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                107.786985                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2240                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    174                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  12.873563                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                107.882695                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2246                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    176                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  12.761364                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     107.786985                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.026315                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.026315                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1734                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1734                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     107.882695                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.026339                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.026339                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1740                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1740                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          506                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            506                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2240                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2240                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2240                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2240                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          161                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           161                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2246                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2246                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2246                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2246                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          165                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           165                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          359                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          359                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          520                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            520                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          520                       # number of overall misses
-system.cpu.dcache.overall_misses::total           520                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      6422000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      6422000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     15048500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     15048500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     21470500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     21470500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     21470500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     21470500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1895                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1895                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          524                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            524                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          524                       # number of overall misses
+system.cpu.dcache.overall_misses::total           524                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      6561000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      6561000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     15048000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     15048000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     21609000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     21609000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     21609000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     21609000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1905                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1905                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2760                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2760                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2760                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2760                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.084960                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.084960                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2770                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2770                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2770                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2770                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.086614                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.086614                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.188406                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.188406                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.188406                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.188406                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41289.423077                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41289.423077                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.189170                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.189170                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.189170                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.189170                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39763.636364                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 39763.636364                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41916.434540                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41916.434540                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41238.549618                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41238.549618                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41238.549618                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41238.549618                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -478,119 +478,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           59                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           62                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           62                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          286                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          286                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          345                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          345                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          345                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          345                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          102                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          348                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          348                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          348                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          103                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          175                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          175                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          175                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          175                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4236500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      4236500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2874500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2874500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7111000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7111000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7111000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7111000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.053826                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.053826                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          176                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          176                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          176                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4311000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2875000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2875000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7186000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7186000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7186000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7186000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.054068                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.054068                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063406                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.063406                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063406                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.063406                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 40634.285714                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40634.285714                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 40634.285714                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.063538                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.063538                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.063538                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.063538                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41854.368932                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41854.368932                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39383.561644                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39383.561644                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40829.545455                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 40829.545455                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40829.545455                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 40829.545455                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               220.452556                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               219.598461                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   415                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002410                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   416                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002404                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    159.940532                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     60.512024                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004881                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001847                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006728                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    158.781999                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     60.816461                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004846                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001856                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006702                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          314                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          102                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          313                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          103                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          416                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          314                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          175                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          313                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          176                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           489                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          314                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          175                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          313                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          176                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          489                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11286500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4103500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     15390000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2793500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2793500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     11286500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      6897000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     18183500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     11286500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      6897000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     18183500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          315                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          102                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11256000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4176500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15432500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2794000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2794000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11256000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6970500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18226500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11256000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6970500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18226500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          314                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          103                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          417                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          315                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          175                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          314                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          176                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          490                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          315                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          175                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          314                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          176                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          490                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996825                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996815                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.997602                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996825                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996815                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997959                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996825                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996815                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997959                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 37185.071575                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 37185.071575                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35961.661342                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40548.543689                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 37097.355769                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38273.972603                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38273.972603                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35961.661342                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39605.113636                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37273.006135                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35961.661342                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39605.113636                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37273.006135                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          314                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          102                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          313                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          103                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          416                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          314                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          175                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          313                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          176                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          489                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          314                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          175                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          313                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          176                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          489                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10285500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3793000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14078500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10253500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3859000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14112500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2567500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2567500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10285500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6360500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16646000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10285500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6360500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16646000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10253500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6426500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10253500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6426500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997602                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997959                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996825                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996815                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997959                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32758.785942                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37466.019417                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33924.278846                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32758.785942                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36514.204545                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34110.429448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32758.785942                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36514.204545                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34110.429448                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 6e91910a0b1bf534f9ac03307347b5333693d9ab..63c93b86fedf86501833b16ae95169616aa88457 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index 1bf93074b1b35b198ed92eca892525cf593edbb7..5f9ceb0b2d19d003e65209a417fc6a3675077ae5 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:50:11
-gem5 started Jun  4 2012 13:46:44
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:12
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 3215000 because target called exit()
+Exiting @ tick 3208000 because target called exit()
index d49eba0fa8d6c014842723af13b0d4e71781b885..e13838fa45851381b5d11bd91190c1018ae9373c 100644 (file)
@@ -1,58 +1,58 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     3215000                       # Number of ticks simulated
-final_tick                                    3215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     3208000                       # Number of ticks simulated
+final_tick                                    3208000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1264163                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1259559                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              630191855                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205200                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_inst_rate                                  57981                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57971                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               29099028                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214184                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7980093313                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           2738413686                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             10718506998                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7980093313                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7980093313                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          2082737170                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             2082737170                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7980093313                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          4821150855                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            12801244168                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7980049875                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           2739401496                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             10719451372                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7980049875                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7980049875                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          2087281796                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             2087281796                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7980049875                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          4826683292                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            12806733167                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6414                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6400                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6431                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6417                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -66,26 +66,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                             6431                       # number of cpu cycles simulated
+system.cpu.numCycles                             6417                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       6431                       # Number of busy cycles
+system.cpu.num_busy_cycles                       6417                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 01a7fc7027792c9e001e8e07bbb92f058455bc79..f5d6aede8165dc40014aba289ae6d36b07e51a21 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 28 2012 11:30:15
-gem5 started Jul 28 2012 11:35:39
+gem5 compiled Aug 13 2012 16:55:16
+gem5 started Aug 13 2012 18:08:58
 gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
index 77b3a189c4c49e614d2958daf76e1b0dafe1783a..1923905554c0ced8af0fc23c44a26add83fe1f8b 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000279                       # Nu
 sim_ticks                                      279353                       # Number of ticks simulated
 final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24063                       # Simulator instruction rate (inst/s)
-host_op_rate                                    24061                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1049533                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  30486                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30483                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1332529                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 233960                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_seconds                                     0.21                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             91840789                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             31515681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               123356470                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        91840789                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           91840789                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             91640326                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             31458406                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               123098732                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        91640326                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           91640326                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            23969673                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               23969673                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            91840789                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            55485354                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              147326143                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            91640326                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            55428078                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              147068404                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           279353                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     279353                       # Number of busy cycles
index 9b7d486031abdf0299f8212b311567871450680c..871e7f56ed93b0e64f3c556e346418f6cfc04744 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 28 2012 11:32:56
-gem5 started Jul 28 2012 11:35:52
+gem5 compiled Aug 13 2012 16:57:01
+gem5 started Aug 13 2012 18:09:22
 gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
index fbea8fc890ed2ca8a8ad84da1e0bb3155f486301..46c57187f512a105a5638cf2305756f40a7aa5ab 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000224                       # Nu
 sim_ticks                                      223694                       # Number of ticks simulated
 final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   2880                       # Simulator instruction rate (inst/s)
-host_op_rate                                     2880                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 100591                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 235160                       # Number of bytes of host memory used
-host_seconds                                     2.22                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_inst_rate                                  29074                       # Simulator instruction rate (inst/s)
+host_op_rate                                    29072                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1017648                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235156                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            114692392                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             39357336                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               154049729                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       114692392                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          114692392                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            114442050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             39285810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               153727860                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       114442050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          114442050                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            29933749                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               29933749                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           114692392                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            69291085                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              183983477                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           114442050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            69219559                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              183661609                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           223694                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     223694                       # Number of busy cycles
index 3bfc669f51e54168369bdf48070802eb785cd35d..4a97d59dd2a0568f647383bf2ec3ecae5592c8e5 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 28 2012 11:35:39
-gem5 started Jul 28 2012 11:35:54
+gem5 compiled Aug 13 2012 16:58:46
+gem5 started Aug 13 2012 18:10:55
 gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
index 872c0358f0fd4f8df9da37c50a2d4932ae184ff1..d46680c6653069814b7a1e2c711a38ea9bb31a23 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000232                       # Nu
 sim_ticks                                      231701                       # Number of ticks simulated
 final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46536                       # Simulator instruction rate (inst/s)
-host_op_rate                                    46530                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1683295                       # Simulator tick rate (ticks/s)
+host_inst_rate                                  37740                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37736                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1368171                       # Simulator tick rate (ticks/s)
 host_mem_usage                                 233016                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_seconds                                     0.17                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            110728914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             37997246                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               148726160                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       110728914                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          110728914                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            110487223                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             37928192                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               148415415                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       110487223                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          110487223                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            28899314                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               28899314                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           110728914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            66896561                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              177625474                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           110487223                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            66827506                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              177314729                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -55,22 +55,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -87,20 +87,20 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           231701                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     231701                       # Number of busy cycles
index 8ab87885974ff3b82122aef9f73bf9045b54d9d0..d96b1791c7396d61ae0c6bf025dd924a53aa97f6 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 28 2012 11:27:37
-gem5 started Jul 28 2012 11:35:39
+gem5 compiled Aug 13 2012 16:53:31
+gem5 started Aug 13 2012 18:06:43
 gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 208400 because target called exit()
+Exiting @ tick 208110 because target called exit()
index 8d2f9d8f80678387568fc15289e3004ad3ee0b7c..02a4e6d9eafa8206ea6030165cba6bb50e30e362 100644 (file)
@@ -1,38 +1,38 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000208                       # Number of seconds simulated
-sim_ticks                                      208400                       # Number of ticks simulated
-final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                      208110                       # Number of ticks simulated
+final_tick                                     208110                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  49772                       # Simulator instruction rate (inst/s)
-host_op_rate                                    49764                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1619227                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 231924                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_inst_rate                                  43199                       # Simulator instruction rate (inst/s)
+host_op_rate                                    43194                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1406596                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231928                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            123109405                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             42245681                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               165355086                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       123109405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          123109405                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data            32130518                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               32130518                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           123109405                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            74376200                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              197485605                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            123011869                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             42227668                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               165239537                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       123011869                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          123011869                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data            32175292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               32175292                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           123011869                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            74402960                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              197414829                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.L1DcacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.L1DcacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -61,22 +61,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -90,26 +90,26 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                           208400                       # number of cpu cycles simulated
+system.cpu.numCycles                           208110                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                     208400                       # Number of busy cycles
+system.cpu.num_busy_cycles                     208110                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 831de2347cc5be7f4d486a61e1921ed29a26c2c5..0ae04efddfbd3509d0160bdad9975a44235f99f2 100644 (file)
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index 4bad01d5ae8c3fcf1bfd4e33cb1ccc206d33926e..d2962a54f292ca1ca191cea51ba55ed67f317442 100755 (executable)
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 16:32:12
-gem5 started Jul 10 2012 17:16:10
-gem5 executing on sc2b0605
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:12
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index 43810423d3368da226f687080c20833a9b1d361d..5041c7f6ade6c8f753a5d2d70bad42dee08088c1 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000343                       # Nu
 sim_ticks                                      342698                       # Number of ticks simulated
 final_tick                                     342698                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38554                       # Simulator instruction rate (inst/s)
-host_op_rate                                    38550                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2062706                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234872                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             25656                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              8804                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                34460                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        25656                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           25656                       # Number of instructions bytes read from this memory
+host_inst_rate                                  30637                       # Simulator instruction rate (inst/s)
+host_op_rate                                    30634                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1642762                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 233644                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             25600                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              8788                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                34388                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        25600                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           25600                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           6696                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              6696                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6414                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1185                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7599                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6400                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1183                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7583                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               865                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  865                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             74864750                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             25690258                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               100555008                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        74864750                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           74864750                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             74701341                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             25643570                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               100344910                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        74701341                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           74701341                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            19539069                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               19539069                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            74864750                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            45229327                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              120094077                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            74701341                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            45182639                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              119883979                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.cacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -43,22 +43,22 @@ system.cpu.dtb.fetch_hits                           0                       # IT
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -75,20 +75,20 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           342698                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     342698                       # Number of busy cycles
index 4b13e207fb933484afd80e088426ef3a3135186b..b5ef1f793454cebd36c86550b4de8294a2c4fd5a 100644 (file)
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 776a435c2c41a846f4c5560a4733949befe4e448..891277ac41096ba87fe20334c6329a2db006669f 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:08:22
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:12
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 34425000 because target called exit()
+Exiting @ tick 34409000 because target called exit()
index a9d405edb3680742ab1ebb27743ae684d3f1b745..6a791ec60d0272c0d66b30411d3368d68596a884 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000034                       # Number of seconds simulated
-sim_ticks                                    34425000                       # Number of ticks simulated
-final_tick                                   34425000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    34409000                       # Number of ticks simulated
+final_tick                                   34409000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   6722                       # Simulator instruction rate (inst/s)
-host_op_rate                                     6722                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               36133024                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217168                       # Number of bytes of host memory used
-host_seconds                                     0.95                       # Real time elapsed on the host
-sim_insts                                        6404                       # Number of instructions simulated
-sim_ops                                          6404                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  55813                       # Simulator instruction rate (inst/s)
+host_op_rate                                    55804                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              300451871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222640                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+sim_insts                                        6390                       # Number of instructions simulated
+sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data             10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
@@ -19,34 +19,34 @@ system.physmem.bytes_inst_read::total           17792                       # Nu
 system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            516833696                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            312331155                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               829164851                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       516833696                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          516833696                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           516833696                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           312331155                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              829164851                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            517074021                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            312476387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               829550408                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       517074021                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          517074021                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           517074021                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           312476387                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              829550408                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         1185                       # DTB read hits
+system.cpu.dtb.read_hits                         1183                       # DTB read hits
 system.cpu.dtb.read_misses                          7                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     1192                       # DTB read accesses
+system.cpu.dtb.read_accesses                     1190                       # DTB read accesses
 system.cpu.dtb.write_hits                         865                       # DTB write hits
 system.cpu.dtb.write_misses                         3                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
 system.cpu.dtb.write_accesses                     868                       # DTB write accesses
-system.cpu.dtb.data_hits                         2050                       # DTB hits
+system.cpu.dtb.data_hits                         2048                       # DTB hits
 system.cpu.dtb.data_misses                         10                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     2060                       # DTB accesses
-system.cpu.itb.fetch_hits                        6415                       # ITB hits
+system.cpu.dtb.data_accesses                     2058                       # DTB accesses
+system.cpu.itb.fetch_hits                        6401                       # ITB hits
 system.cpu.itb.fetch_misses                        17                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    6432                       # ITB accesses
+system.cpu.itb.fetch_accesses                    6418                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -60,43 +60,43 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                   17                       # Number of system calls
-system.cpu.numCycles                            68850                       # number of cpu cycles simulated
+system.cpu.numCycles                            68818                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        6404                       # Number of instructions committed
-system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
+system.cpu.committedInsts                        6390                       # Number of instructions committed
+system.cpu.committedOps                          6390                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  6317                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          750                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         6331                       # number of integer instructions
+system.cpu.num_conditional_control_insts          749                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         6317                       # number of integer instructions
 system.cpu.num_fp_insts                            10                       # number of float instructions
-system.cpu.num_int_register_reads                8304                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4581                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                8285                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4568                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    8                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2060                       # number of memory refs
-system.cpu.num_load_insts                        1192                       # Number of load instructions
+system.cpu.num_mem_refs                          2058                       # number of memory refs
+system.cpu.num_load_insts                        1190                       # Number of load instructions
 system.cpu.num_store_insts                        868                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      68850                       # Number of busy cycles
+system.cpu.num_busy_cycles                      68818                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                128.155444                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     6136                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                128.208060                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     6122                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    279                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  21.992832                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  21.942652                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     128.155444                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.062576                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.062576                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         6136                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6136                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6136                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6136                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6136                       # number of overall hits
-system.cpu.icache.overall_hits::total            6136                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     128.208060                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.062602                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.062602                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         6122                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6122                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6122                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6122                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6122                       # number of overall hits
+system.cpu.icache.overall_hits::total            6122                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           279                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
@@ -109,18 +109,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     15582000
 system.cpu.icache.demand_miss_latency::total     15582000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     15582000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     15582000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6415                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6415                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6415                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6415                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6415                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6415                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043492                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.043492                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.043492                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.043492                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.043492                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.043492                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         6401                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6401                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6401                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6401                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6401                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6401                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043587                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.043587                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043587                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.043587                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043587                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.043587                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 55849.462366                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366                       # average overall miss latency
@@ -147,12 +147,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14745000
 system.cpu.icache.demand_mshr_miss_latency::total     14745000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14745000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     14745000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043492                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.043492                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.043492                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.043587                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.043587                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043587                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.043587                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
@@ -161,22 +161,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                103.856385                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1882                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                103.892123                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1880                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  11.202381                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  11.190476                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     103.856385                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025356                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025356                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1090                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1090                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     103.892123                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025364                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025364                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1882                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1882                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1882                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1882                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1880                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1880                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1880                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1880                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
@@ -193,22 +193,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      9408000
 system.cpu.dcache.demand_miss_latency::total      9408000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      9408000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      9408000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1183                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1183                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080169                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.080169                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2048                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2048                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2048                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2048                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080304                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.080304                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.081951                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.081951                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.081951                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.081951                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.082031                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.082031                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.082031                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.082031                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -241,14 +241,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8904000
 system.cpu.dcache.demand_mshr_miss_latency::total      8904000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8904000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      8904000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080304                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.080304                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.082031                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.082031                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.082031                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -259,16 +259,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               184.699061                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               184.769601                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   373                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002681                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    128.168283                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     56.530778                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003911                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001725                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005637                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    128.220906                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.548695                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003913                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001726                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005639                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
index 3f1b44728f9f1eaf803bf092d962e1d3b6f11bb6..877f80a3c6320a6a4c7969e81faff8bbfa0336f3 100644 (file)
@@ -214,7 +214,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 3e33cecf6783dac3c4a2480c6bf86c709da115f8..893f17599bf39b26538639044a1024ef0009e27d 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:47:33
-gem5 started Jul  2 2012 11:28:42
+gem5 compiled Aug 13 2012 17:00:38
+gem5 started Aug 13 2012 18:11:29
 gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 20520000 because target called exit()
+Exiting @ tick 20518000 because target called exit()
index 615d61bce861521d6fb652c194232477d384e8ba..28611e3d67d0564816eea94b4241cc2e37563a8e 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000021                       # Number of seconds simulated
-sim_ticks                                    20520000                       # Number of ticks simulated
-final_tick                                   20520000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20518000                       # Number of ticks simulated
+final_tick                                   20518000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67788                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67774                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              238625492                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219036                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
-sim_insts                                        5827                       # Number of instructions simulated
-sim_ops                                          5827                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  56112                       # Simulator instruction rate (inst/s)
+host_op_rate                                    56102                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              197957466                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223380                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+sim_insts                                        5814                       # Number of instructions simulated
+sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             20288                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                29120                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           20288                       # Nu
 system.physmem.num_reads::cpu.inst                317                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   455                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            988693957                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            430409357                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1419103314                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       988693957                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          988693957                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           988693957                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           430409357                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1419103314                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            988790330                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            430451311                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1419241641                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       988790330                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          988790330                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           988790330                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           430451311                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1419241641                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,83 +46,83 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            41041                       # number of cpu cycles simulated
+system.cpu.numCycles                            41037                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1151                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted          850                       # Number of conditional branches predicted
+system.cpu.branch_predictor.lookups              1146                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted          844                       # Number of conditional branches predicted
 system.cpu.branch_predictor.condIncorrect          605                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups            866                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits               310                       # Number of BTB hits
+system.cpu.branch_predictor.BTBLookups            861                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits               300                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS                86                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect           32                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       35.796767                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken          403                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken          748                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5102                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites         3408                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         8510                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.BTBHitPct       34.843206                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken          393                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken          753                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5095                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites         3396                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         8491                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            3                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            1                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            4                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           1331                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       2237                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect          262                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          334                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.regfile_manager.regForwards           1321                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       2235                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect          260                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect          336                       # Number of Branches Incorrectly Predicted As Not Taken).
 system.cpu.execution_unit.mispredicted            596                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted               320                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     65.065502                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions             3155                       # Number of Instructions Executed.
+system.cpu.execution_unit.predicted               319                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     65.136612                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions             3144                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 3                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    1                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                          9765                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                          9756                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
 system.cpu.timesIdled                             505                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           35643                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             5398                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         13.152701                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              1164                       # Number of Load instructions committed
+system.cpu.idleCycles                           35650                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             5387                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         13.127178                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              1163                       # Number of Load instructions committed
 system.cpu.comStores                              925                       # Number of Store instructions committed
-system.cpu.comBranches                            916                       # Number of Branches instructions committed
+system.cpu.comBranches                            915                       # Number of Branches instructions committed
 system.cpu.comNops                                657                       # Number of Nop instructions committed
 system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               2155                       # Number of Integer instructions committed
+system.cpu.comInts                               2144                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5827                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts                        5814                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5814                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
-system.cpu.cpi                               7.043247                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total                  5814                       # Number of Instructions committed (Total)
+system.cpu.cpi                               7.058308                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         7.043247                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.141980                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.058308                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141677                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.141980                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    37403                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      3638                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization                8.864306                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    38212                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      2829                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                6.893107                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    38251                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      2790                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                6.798080                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    39798                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      1243                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                3.028679                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    38136                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      2905                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                7.078288                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.141677                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    37412                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      3625                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization                8.833492                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    38215                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      2822                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                6.876721                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    38252                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      2785                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                6.786558                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    39795                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      1242                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                3.026537                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    38135                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      2902                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                7.071667                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                147.235290                       # Cycle average of tags in use
+system.cpu.icache.tagsinuse                147.247157                       # Cycle average of tags in use
 system.cpu.icache.total_refs                      411                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.288401                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     147.235290                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.071892                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.071892                       # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::cpu.inst     147.247157                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.071898                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.071898                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst          411                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total             411                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst           411                       # number of demand (read+write) hits
@@ -135,12 +135,12 @@ system.cpu.icache.demand_misses::cpu.inst          344                       # n
 system.cpu.icache.demand_misses::total            344                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          344                       # number of overall misses
 system.cpu.icache.overall_misses::total           344                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19612500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19612500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19612500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19612500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19612500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19612500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19614000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19614000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19614000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19614000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19614000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19614000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst          755                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total          755                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst          755                       # number of demand (read+write) accesses
@@ -153,12 +153,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.455629
 system.cpu.icache.demand_miss_rate::total     0.455629                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.455629                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.455629                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57013.081395                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 57013.081395                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 57013.081395                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 57013.081395                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 57013.081395                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 57013.081395                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 57017.441860                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 57017.441860                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 57017.441860                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 57017.441860                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 57017.441860                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 57017.441860                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -179,42 +179,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          319
 system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17428000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     17428000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17428000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     17428000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17428000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     17428000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     17429500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     17429500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     17429500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     17429500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     17429500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     17429500                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.422517                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.422517                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.422517                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.422517                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54633.228840                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54633.228840                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54633.228840                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54633.228840                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54637.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54637.931034                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54637.931034                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54637.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54637.931034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54637.931034                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 89.278998                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1835                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 89.284631                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1834                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.297101                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.289855                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      89.278998                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021797                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021797                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1073                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1073                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      89.284631                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021798                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021798                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1072                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1072                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          762                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            762                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1835                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1835                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1835                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1835                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1834                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1834                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1834                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1834                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            91                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          163                       # number of WriteReq misses
@@ -223,38 +223,38 @@ system.cpu.dcache.demand_misses::cpu.data          254                       # n
 system.cpu.dcache.demand_misses::total            254                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          254                       # number of overall misses
 system.cpu.dcache.overall_misses::total           254                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5537000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5537000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5537500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5537500                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data     10150000                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     10150000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     15687000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     15687000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     15687000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     15687000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_miss_latency::cpu.data     15687500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     15687500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     15687500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     15687500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078179                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.078179                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.078246                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.078246                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.176216                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.176216                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.121589                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.121589                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.121589                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.121589                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60846.153846                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 60846.153846                       # average ReadReq miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.121648                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.121648                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.121648                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.121648                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60851.648352                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 60851.648352                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62269.938650                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 62269.938650                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 61759.842520                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 61759.842520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 61759.842520                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 61759.842520                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61761.811024                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61761.811024                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61761.811024                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61761.811024                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1194500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -279,40 +279,40 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          138
 system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5138000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      5138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5138500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5138500                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2913500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2913500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8051500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      8051500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8051500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      8051500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8052000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8052000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8052000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8052000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59057.471264                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59057.471264                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59063.218391                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59063.218391                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57127.450980                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57127.450980                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58344.202899                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 58344.202899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58344.202899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 58344.202899                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58347.826087                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 58347.826087                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58347.826087                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 58347.826087                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               204.292602                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               204.307813                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    148.846889                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     55.445713                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004542                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    148.858961                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     55.448851                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004543                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.001692                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::total        0.006235                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
@@ -332,17 +332,17 @@ system.cpu.l2cache.demand_misses::total           455                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     17060000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5021500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     22081500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     17061000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      5022000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     22083000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2843500                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      2843500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     17060000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7865000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     24925000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     17060000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7865000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     24925000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     17061000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7865500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     24926500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     17061000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7865500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     24926500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
@@ -365,17 +365,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995624                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53817.034700                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57718.390805                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54657.178218                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53820.189274                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57724.137931                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 54660.891089                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55754.901961                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55754.901961                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53817.034700                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56992.753623                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54780.219780                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53817.034700                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56992.753623                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54780.219780                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53820.189274                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56996.376812                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54783.516484                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53820.189274                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56996.376812                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54783.516484                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
index f6f1675ea479aef9801769cdc8883cde10d9532d..33231821662722b635a906cce7061248fad4d321 100644 (file)
@@ -512,7 +512,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index d96fc7f5c0aaf9f024f09d5ba6f61c4d3a199ccb..56b18a79d3556ce58535b6a22bed442bc04f033d 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:47:33
-gem5 started Jul  2 2012 11:28:53
+gem5 compiled Aug 13 2012 17:00:38
+gem5 started Aug 13 2012 18:11:40
 gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 13016500 because target called exit()
+Exiting @ tick 12925500 because target called exit()
index 4a3a21e6cbd5ea13b6480b146056509ea228f8bf..3001351e6b100bba9b045ff2eee4fb4cad132016 100644 (file)
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    13016500                       # Number of ticks simulated
-final_tick                                   13016500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12925500                       # Number of ticks simulated
+final_tick                                   12925500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  54505                       # Simulator instruction rate (inst/s)
-host_op_rate                                    54495                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              137205108                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220060                       # Number of bytes of host memory used
+host_inst_rate                                  52967                       # Simulator instruction rate (inst/s)
+host_op_rate                                    52957                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132735366                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224404                       # Number of bytes of host memory used
 host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        5169                       # Number of instructions simulated
-sim_ops                                          5169                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21760                       # Number of bytes read from this memory
+sim_insts                                        5156                       # Number of instructions simulated
+sim_ops                                          5156                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             21696                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9024                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                30784                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21760                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21760                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                340                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                30720                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21696                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21696                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                339                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                141                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   481                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1671724350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            693273922                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2364998271                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1671724350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1671724350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1671724350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           693273922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2364998271                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   480                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1678542416                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            698154810                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2376697226                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1678542416                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1678542416                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1678542416                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           698154810                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2376697226                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,101 +46,101 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            26034                       # number of cpu cycles simulated
+system.cpu.numCycles                            25852                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2148                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               1448                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                450                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  1662                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      462                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2052                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               1365                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                440                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  1625                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      468                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      263                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      254                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  67                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               8866                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          13061                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2148                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                725                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          3176                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1340                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    826                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               8806                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          12660                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2052                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                722                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          3113                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1287                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    809                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           143                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1948                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   270                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              13893                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              0.940114                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.257377                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1908                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   272                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              13710                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              0.923414                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.233238                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    10717     77.14%     77.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     1298      9.34%     86.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      110      0.79%     87.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      134      0.96%     88.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      300      2.16%     90.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      103      0.74%     91.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      148      1.07%     92.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      126      0.91%     93.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                      957      6.89%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    10597     77.29%     77.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     1289      9.40%     86.70% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      106      0.77%     87.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      138      1.01%     88.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      293      2.14%     90.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                       99      0.72%     91.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      151      1.10%     92.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      124      0.90%     93.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                      913      6.66%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                13893                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.082507                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.501690                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     9037                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                   974                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2996                       # Number of cycles decode is running
+system.cpu.fetch.rateDist::total                13710                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.079375                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.489711                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8966                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                   966                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2934                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                    51                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    835                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  145                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                    47                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12168                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   188                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    835                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     9227                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     288                       # Number of cycles rename is blocking
+system.cpu.decode.SquashCycles                    793                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  143                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                    46                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  11758                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   178                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    793                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     9155                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     277                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles            540                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2860                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   143                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  11638                       # Number of instructions processed by rename
+system.cpu.rename.RunCycles                      2801                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   144                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11265                       # Number of instructions processed by rename
 system.cpu.rename.LSQFullEvents                   129                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands                7046                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 13805                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            13801                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands                6879                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 13414                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            13410                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                 4                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  3410                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     3636                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps                  3398                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     3481                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 16                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             10                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       308                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2447                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1180                       # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts                       314                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2372                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1172                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 1                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                1                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                       9050                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                       8819                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  12                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      8137                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                46                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            3435                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         1984                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                      8008                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                47                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            3225                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         1836                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved              2                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         13893                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.585691                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.249798                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         13710                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.584099                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.244040                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               10352     74.51%     74.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1446     10.41%     84.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 850      6.12%     91.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 537      3.87%     94.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 350      2.52%     97.42% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 226      1.63%     99.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                  89      0.64%     99.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  28      0.20%     99.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  15      0.11%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               10210     74.47%     74.47% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1436     10.47%     84.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 842      6.14%     91.09% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 525      3.83%     94.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 351      2.56%     97.48% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 220      1.60%     99.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                  85      0.62%     99.70% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  29      0.21%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  12      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           13893                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           13710                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntAlu                       3      1.97%      1.97% # attempts to use FU when none available
 system.cpu.iq.fu_full::IntMult                      0      0.00%      1.97% # attempts to use FU when none available
@@ -176,188 +176,188 @@ system.cpu.iq.fu_full::MemWrite                    52     34.21%    100.00% # at
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  4825     59.30%     59.30% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    5      0.06%     59.36% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     59.38% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2212     27.18%     86.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1091     13.41%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  4734     59.12%     59.12% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    5      0.06%     59.18% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     2      0.02%     59.20% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     59.23% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2177     27.19%     86.41% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1088     13.59%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   8137                       # Type of FU issued
-system.cpu.iq.rate                           0.312553                       # Inst issue rate
+system.cpu.iq.FU_type_0::total                   8008                       # Type of FU issued
+system.cpu.iq.rate                           0.309763                       # Inst issue rate
 system.cpu.iq.fu_busy_cnt                         152                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018680                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30361                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             12504                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         7339                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_rate                   0.018981                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              29921                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             12064                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         7226                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   4                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  2                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            2                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   8287                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   8158                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       2                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               60                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1283                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1209                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            5                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation            9                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          255                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           10                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          247                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    835                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     148                       # Number of cycles IEW is blocking
+system.cpu.iew.iewSquashCycles                    793                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     141                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                    16                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               10551                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                78                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2447                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1180                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               10240                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                94                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2372                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1172                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 12                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents              9                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            101                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          378                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  479                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  7784                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  2096                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               353                       # Number of squashed instructions skipped in execute
+system.cpu.iew.memOrderViolationEvents             10                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            103                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          360                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  463                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  7665                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  2061                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               343                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
-system.cpu.iew.exec_nop                          1489                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3163                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1325                       # Number of branches executed
-system.cpu.iew.exec_stores                       1067                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.298994                       # Inst execution rate
-system.cpu.iew.wb_sent                           7431                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          7341                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      2840                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      4066                       # num instructions consuming a value
+system.cpu.iew.exec_nop                          1409                       # number of nop insts executed
+system.cpu.iew.exec_refs                         3123                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1292                       # Number of branches executed
+system.cpu.iew.exec_stores                       1062                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.296495                       # Inst execution rate
+system.cpu.iew.wb_sent                           7314                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          7228                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      2794                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      3985                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.281977                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.698475                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.279592                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.701129                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps             5826                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            4721                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts           5813                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5813                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            4420                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               404                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        13058                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.446163                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.225344                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               395                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        12917                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.450027                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.233846                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        10619     81.32%     81.32% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1036      7.93%     89.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          643      4.92%     94.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          305      2.34%     96.52% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          154      1.18%     97.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5           84      0.64%     98.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           72      0.55%     98.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           39      0.30%     99.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          106      0.81%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        10496     81.26%     81.26% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1026      7.94%     89.20% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          636      4.92%     94.12% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          301      2.33%     96.45% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          148      1.15%     97.60% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5           90      0.70%     98.30% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           76      0.59%     98.89% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           38      0.29%     99.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          106      0.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        13058                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 5826                       # Number of instructions committed
-system.cpu.commit.committedOps                   5826                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        12917                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                 5813                       # Number of instructions committed
+system.cpu.commit.committedOps                   5813                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2089                       # Number of memory references committed
-system.cpu.commit.loads                          1164                       # Number of loads committed
+system.cpu.commit.refs                           2088                       # Number of memory references committed
+system.cpu.commit.loads                          1163                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                        916                       # Number of branches committed
+system.cpu.commit.branches                        915                       # Number of branches committed
 system.cpu.commit.fp_insts                          2                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      5124                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      5111                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                   87                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                   106                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        23486                       # The number of ROB reads
-system.cpu.rob.rob_writes                       21936                       # The number of ROB writes
-system.cpu.timesIdled                             270                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           12141                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
-system.cpu.committedOps                          5169                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
-system.cpu.cpi                               5.036564                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         5.036564                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.198548                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.198548                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    10600                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    5152                       # number of integer regfile writes
+system.cpu.rob.rob_reads                        23031                       # The number of ROB reads
+system.cpu.rob.rob_writes                       21266                       # The number of ROB writes
+system.cpu.timesIdled                             269                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           12142                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        5156                       # Number of Instructions Simulated
+system.cpu.committedOps                          5156                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  5156                       # Number of Instructions Simulated
+system.cpu.cpi                               5.013964                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         5.013964                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.199443                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.199443                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    10440                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    5074                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         3                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        1                       # number of floating regfile writes
-system.cpu.misc_regfile_reads                     155                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                     150                       # number of misc regfile reads
 system.cpu.icache.replacements                     17                       # number of replacements
-system.cpu.icache.tagsinuse                163.172601                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1511                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    343                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.405248                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                161.949608                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1474                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    342                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.309942                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     163.172601                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.079674                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.079674                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1511                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1511                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1511                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1511                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1511                       # number of overall hits
-system.cpu.icache.overall_hits::total            1511                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          437                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           437                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          437                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            437                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          437                       # number of overall misses
-system.cpu.icache.overall_misses::total           437                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     15987000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     15987000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     15987000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     15987000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     15987000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     15987000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1948                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1948                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1948                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1948                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1948                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1948                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.224333                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.224333                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.224333                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.224333                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.224333                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.224333                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 36583.524027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 36583.524027                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     161.949608                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.079077                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.079077                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1474                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1474                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1474                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1474                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1474                       # number of overall hits
+system.cpu.icache.overall_hits::total            1474                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          434                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           434                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          434                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            434                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          434                       # number of overall misses
+system.cpu.icache.overall_misses::total           434                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15909000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15909000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15909000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15909000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15909000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15909000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1908                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1908                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1908                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1908                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1908                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.227463                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.227463                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.227463                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.227463                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.227463                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.227463                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36656.682028                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 36656.682028                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36656.682028                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 36656.682028                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36656.682028                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 36656.682028                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -366,94 +366,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           94                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           94                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           94                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           94                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           94                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           94                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          343                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          343                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          343                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          343                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          343                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12452000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     12452000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12452000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     12452000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12452000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     12452000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.176078                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.176078                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.176078                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.176078                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           92                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           92                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           92                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           92                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           92                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          342                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          342                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          342                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          342                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          342                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          342                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12417500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12417500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12417500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12417500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.179245                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.179245                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.179245                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.179245                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.179245                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.179245                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36308.479532                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36308.479532                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36308.479532                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36308.479532                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36308.479532                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36308.479532                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 91.140441                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2441                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 90.879080                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2407                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  17.312057                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  17.070922                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      91.140441                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.022251                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.022251                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1863                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1863                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data          578                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total            578                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2441                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2441                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2441                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2441                       # number of overall hits
+system.cpu.dcache.occ_blocks::cpu.data      90.879080                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.022187                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.022187                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1830                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1830                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          577                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            577                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2407                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2407                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2407                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2407                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          148                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           148                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data          347                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total          347                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          495                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            495                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          495                       # number of overall misses
-system.cpu.dcache.overall_misses::total           495                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      5658500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      5658500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     13040000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     13040000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     18698500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     18698500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     18698500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     18698500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2011                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2011                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_misses::cpu.data          348                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          348                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          496                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            496                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          496                       # number of overall misses
+system.cpu.dcache.overall_misses::total           496                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5699000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5699000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     13075000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     13075000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18774000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18774000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18774000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18774000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1978                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1978                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2936                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2936                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2936                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2936                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.073595                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.073595                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.375135                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total     0.375135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.168597                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.168597                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.168597                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.168597                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37774.747475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 37774.747475                       # average overall miss latency
+system.cpu.dcache.demand_accesses::cpu.data         2903                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2903                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2903                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2903                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074823                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074823                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.376216                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total     0.376216                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.170858                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.170858                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.170858                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.170858                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38506.756757                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 38506.756757                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37571.839080                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37571.839080                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37850.806452                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37850.806452                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37850.806452                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 37850.806452                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -464,12 +464,12 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.ReadReq_mshr_hits::cpu.data           58                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data          296                       # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total          296                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          354                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          354                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          354                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          354                       # number of overall MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          297                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          297                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          355                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          355                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          355                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          355                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           90                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
@@ -478,103 +478,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          141
 system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3847000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3847000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3832000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3832000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2081000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      2081000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5928000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5928000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.044754                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.044754                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5913000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5913000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5913000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5913000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045501                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.045501                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048025                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.048025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048025                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.048025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42744.444444                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42744.444444                       # average ReadReq mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.048570                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.048570                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.048570                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.048570                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42042.553191                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 42042.553191                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42042.553191                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 42042.553191                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41936.170213                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 41936.170213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41936.170213                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 41936.170213                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               222.725864                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               221.306774                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   430                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.006977                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   429                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.006993                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    165.335127                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     57.390737                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.005046                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001751                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006797                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    164.083724                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     57.223050                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005007                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001746                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006754                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          340                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          339                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           90                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          430                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          429                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          340                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          339                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           481                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          340                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           480                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          339                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          141                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          481                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12086500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3738500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     15825000                       # number of ReadReq miss cycles
+system.cpu.l2cache.overall_misses::total          480                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12053000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3723500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15776500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1998000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      1998000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12086500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      5736500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     17823000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12086500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      5736500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     17823000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          343                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12053000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5721500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     17774500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12053000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5721500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     17774500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          342                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           90                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          433                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          432                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          343                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          342                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          484                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          343                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          483                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          342                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          484                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991254                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total          483                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991228                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.993072                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.993056                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991254                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991228                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.993802                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991254                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.993789                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991228                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.993802                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581                       # average ReadReq miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.993789                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35554.572271                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41372.222222                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36775.058275                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35554.572271                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40578.014184                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37030.208333                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35554.572271                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40578.014184                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37030.208333                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          340                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          339                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           90                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          430                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          429                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          340                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          339                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          481                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          340                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          480                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          339                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          481                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10999000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3463000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14462000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total          480                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10969500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3448000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14417500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1839500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1839500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10999000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5302500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     16301500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10999000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5302500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     16301500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10969500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5287500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10969500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5287500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16257000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991228                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993072                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.993056                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991228                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.993802                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991254                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.993789                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991228                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.993802                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        32350                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38477.777778                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33632.558140                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.993789                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32358.407080                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38311.111111                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33607.226107                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36068.627451                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        32350                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37606.382979                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33890.852391                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        32350                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32358.407080                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        37500                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33868.750000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32358.407080                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        37500                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33868.750000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index bb362afce2549c6dc226fc1828d40bfc1d926741..f99a49f5df209fbd798be442013232f7f5ae1b8b 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index 43669dc214c62ca67ed1e5ef0dc434d0907d800d..9e8404456e603d56403fb069f11960add6c94f24 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:58:11
-gem5 started Jun  4 2012 14:43:38
+gem5 compiled Aug 13 2012 17:00:38
+gem5 started Aug 13 2012 18:11:50
 gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 2913500 because target called exit()
+Exiting @ tick 2907000 because target called exit()
index fa97a6f4798c93e29f9c84d7399b63b123262f8a..2c73dba58c97c249df410c2f6f5b49bcb9355c7f 100644 (file)
@@ -1,38 +1,38 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2913500                       # Number of ticks simulated
-final_tick                                    2913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2907000                       # Number of ticks simulated
+final_tick                                    2907000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1277439                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1267147                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              631162418                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206236                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
-sim_insts                                        5827                       # Number of instructions simulated
-sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             23312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              4375                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                27687                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23312                       # Number of instructions bytes read from this memory
+host_inst_rate                                 264545                       # Simulator instruction rate (inst/s)
+host_op_rate                                   264338                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              132069950                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214924                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+sim_insts                                        5814                       # Number of instructions simulated
+sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             23260                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4374                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27634                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23260                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23260                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           3658                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              3658                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5828                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6992                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5815                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6978                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               925                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  925                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           8001372919                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1501630342                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9503003261                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      8001372919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         8001372919                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1255534580                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1255534580                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          8001372919                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2757164922                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10758537841                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           8001375989                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1504643963                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9506019952                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001375989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001375989                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1258341933                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1258341933                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001375989                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2762985896                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10764361885                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -52,26 +52,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                             5828                       # number of cpu cycles simulated
+system.cpu.numCycles                             5815                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5827                       # Number of instructions committed
-system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.committedInsts                        5814                       # Number of instructions committed
+system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         5113                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7300                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2089                       # number of memory refs
+system.cpu.num_load_insts                        1163                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5828                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5815                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 5e5dbf165ffedfbda16fc4d79ddcda7312e01237..42e36b24c3f74404d30dbd7952b44a365ad6b9d8 100644 (file)
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index f843b6bdc50e7ebf388654f5bbfc158c59548ee6..7d7a57a702486dbeea0279f57dfa27324e5e8a9f 100755 (executable)
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:55:32
-gem5 started Jul 10 2012 17:56:04
-gem5 executing on sc2b0605
+gem5 compiled Aug 13 2012 17:00:38
+gem5 started Aug 13 2012 18:12:12
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index 656b52217b387b130127d87a0d364c565a866eed..a8b1b136abf8e2dffdf8a11f8aafd932ca8e1171 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000293                       # Nu
 sim_ticks                                      292960                       # Number of ticks simulated
 final_tick                                     292960                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  39535                       # Simulator instruction rate (inst/s)
-host_op_rate                                    39530                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1987220                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 236468                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-sim_insts                                        5827                       # Number of instructions simulated
-sim_ops                                          5827                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             23312                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              4375                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                27687                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23312                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23312                       # Number of instructions bytes read from this memory
+host_inst_rate                                  57090                       # Simulator instruction rate (inst/s)
+host_op_rate                                    57080                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2875747                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 235412                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+sim_insts                                        5814                       # Number of instructions simulated
+sim_ops                                          5814                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             23260                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4374                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                27634                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23260                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23260                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           3658                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              3658                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5828                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1164                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6992                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5815                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1163                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6978                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               925                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  925                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             79574003                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             14933779                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                94507783                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        79574003                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           79574003                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             79396505                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             14930366                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                94326871                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        79396505                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           79396505                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            12486346                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               12486346                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            79574003                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            27420126                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              106994129                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            79396505                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            27416712                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              106813217                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.cacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -61,20 +61,20 @@ system.cpu.workload.num_syscalls                    8                       # Nu
 system.cpu.numCycles                           292960                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5827                       # Number of instructions committed
-system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.committedInsts                        5814                       # Number of instructions committed
+system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         5113                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7300                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2089                       # number of memory refs
+system.cpu.num_load_insts                        1163                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     292960                       # Number of busy cycles
index 1e54677abc9efb908c6a412a11b8ce6b62bedb50..67b7a624d20d9a10959cb24e9df296022f819691 100644 (file)
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 3ee3fb92330b8d9004836c590e3c59512bd61cbd..15c5cb118f96619920cac303dfaf10cd321f2abd 100755 (executable)
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:47:33
-gem5 started Jul  2 2012 11:29:16
+gem5 compiled Aug 13 2012 17:00:38
+gem5 started Aug 13 2012 18:12:01
 gem5 executing on zizzer
-command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 33413000 because target called exit()
+Exiting @ tick 33399000 because target called exit()
index eb8915cb4b3a80fc05f732a0cdc966af35c3bfe2..654ee7d3bc96e87ca6c5b353461b557a6e88ee2a 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000033                       # Number of seconds simulated
-sim_ticks                                    33413000                       # Number of ticks simulated
-final_tick                                   33413000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    33399000                       # Number of ticks simulated
+final_tick                                   33399000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 168189                       # Simulator instruction rate (inst/s)
-host_op_rate                                   168105                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              963489284                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219036                       # Number of bytes of host memory used
+host_inst_rate                                 212162                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212025                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1217250605                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223376                       # Number of bytes of host memory used
 host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                        5827                       # Number of instructions simulated
-sim_ops                                          5827                       # Number of ops (including micro ops) simulated
+sim_insts                                        5814                       # Number of instructions simulated
+sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28096                       # Number of bytes read from this memory
@@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total           19264                       # Nu
 system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   439                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            576542064                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            264328255                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               840870320                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       576542064                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          576542064                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           576542064                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           264328255                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              840870320                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            576783736                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            264439055                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               841222791                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       576783736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          576783736                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           576783736                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           264439055                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              841222791                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,43 +46,43 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    8                       # Number of system calls
-system.cpu.numCycles                            66826                       # number of cpu cycles simulated
+system.cpu.numCycles                            66798                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5827                       # Number of instructions committed
-system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
+system.cpu.committedInsts                        5814                       # Number of instructions committed
+system.cpu.committedOps                          5814                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  5113                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          677                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5126                       # number of integer instructions
+system.cpu.num_conditional_control_insts          676                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         5113                       # number of integer instructions
 system.cpu.num_fp_insts                             2                       # number of float instructions
-system.cpu.num_int_register_reads                7300                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               3409                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                7284                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               3397                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    3                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   1                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2090                       # number of memory refs
-system.cpu.num_load_insts                        1164                       # Number of load instructions
+system.cpu.num_mem_refs                          2089                       # number of memory refs
+system.cpu.num_load_insts                        1163                       # Number of load instructions
 system.cpu.num_store_insts                        926                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      66826                       # Number of busy cycles
+system.cpu.num_busy_cycles                      66798                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                     13                       # number of replacements
-system.cpu.icache.tagsinuse                133.092783                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     5526                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                133.141027                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     5513                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  18.237624                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  18.194719                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     133.092783                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.064987                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.064987                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         5526                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5526                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5526                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5526                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5526                       # number of overall hits
-system.cpu.icache.overall_hits::total            5526                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     133.141027                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.065010                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.065010                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5513                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5513                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5513                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5513                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5513                       # number of overall hits
+system.cpu.icache.overall_hits::total            5513                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          303                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           303                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          303                       # number of demand (read+write) misses
@@ -95,18 +95,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     16884000
 system.cpu.icache.demand_miss_latency::total     16884000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     16884000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     16884000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5829                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5829                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5829                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5829                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.051981                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.051981                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.051981                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.051981                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.051981                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.051981                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         5816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5816                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5816                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5816                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5816                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5816                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052098                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.052098                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.052098                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.052098                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.052098                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.052098                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
@@ -133,12 +133,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15975000
 system.cpu.icache.demand_mshr_miss_latency::total     15975000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15975000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     15975000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.051981                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.051981                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.051981                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.052098                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.052098                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052098                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.052098                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
@@ -147,22 +147,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 87.717237                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1951                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 87.742269                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1950                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  14.137681                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  14.130435                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      87.717237                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.021415                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.021415                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1077                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1077                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      87.742269                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021421                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021421                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1076                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1076                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1951                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1951                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1951                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1951                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1950                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1950                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1950                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1950                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
@@ -179,22 +179,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7728000
 system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1163                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1163                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074742                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.074742                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2088                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2088                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074807                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.074807                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.066060                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.066060                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.066060                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.066060                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.066092                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.066092                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.066092                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -227,14 +227,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000
 system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074807                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.074807                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.066092                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066092                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.066092                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -245,16 +245,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               188.818071                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               188.881290                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    134.446837                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     54.371234                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004103                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001659                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005762                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    134.495649                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.385641                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004104                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001660                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005764                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
index fe01ee3c1ff9c85e73d8ae7dec55c5b00d4e4593..0b8702da21dd9629a49175361b9df043396cb252 100644 (file)
@@ -513,7 +513,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 4c16f50ba877dee2b3acd43c26fb6e722431fbb7..4f1d93bdfcee934f3b31c18aab7a37e90ebea648 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:50:36
-gem5 started Jul  2 2012 11:29:39
+gem5 compiled Aug 13 2012 17:02:09
+gem5 started Aug 13 2012 18:12:24
 gem5 executing on zizzer
-command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
+command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 11812000 because target called exit()
+Exiting @ tick 11763500 because target called exit()
index 0b8cd16eafda62c21fe05690f1ed49a0c1bf2431..a60091c974ef9b34b2d442566a3f73e7121d9af5 100644 (file)
@@ -1,32 +1,32 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000012                       # Number of seconds simulated
-sim_ticks                                    11812000                       # Number of ticks simulated
-final_tick                                   11812000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    11763500                       # Number of ticks simulated
+final_tick                                   11763500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  59914                       # Simulator instruction rate (inst/s)
-host_op_rate                                    59903                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              121974515                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216016                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
-sim_insts                                        5800                       # Number of instructions simulated
-sim_ops                                          5800                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             22528                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              6400                       # Number of bytes read from this memory
+host_inst_rate                                  53396                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53387                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              108411505                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219412                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
+sim_insts                                        5792                       # Number of instructions simulated
+sim_ops                                          5792                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             22464                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              6464                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                28928                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        22528                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           22528                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                352                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                100                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        22464                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           22464                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                351                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                101                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   452                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1907213004                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            541821876                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2449034880                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1907213004                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1907213004                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1907213004                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           541821876                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2449034880                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1909635738                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            549496323                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2459132061                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1909635738                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1909635738                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1909635738                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           549496323                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2459132061                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -46,317 +46,317 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                            23625                       # number of cpu cycles simulated
+system.cpu.numCycles                            23528                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     2490                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               2041                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                460                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2061                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      629                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     2457                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               2014                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                452                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2037                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      618                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      162                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.usedRAS                      160                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                  30                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               7441                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14561                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        2490                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                791                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          2421                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1432                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                    932                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.icacheStallCycles               7380                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          14306                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        2457                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                778                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          2377                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1402                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                    936                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    1                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      1897                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   321                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              11761                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.238075                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.668941                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      1859                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   319                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              11638                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.229249                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.662964                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                     9340     79.42%     79.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      172      1.46%     80.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      167      1.42%     82.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      146      1.24%     83.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      197      1.68%     85.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      155      1.32%     86.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      255      2.17%     88.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      108      0.92%     89.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1221     10.38%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                     9261     79.58%     79.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      173      1.49%     81.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      162      1.39%     82.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      137      1.18%     83.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      198      1.70%     85.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      148      1.27%     86.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      250      2.15%     88.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      106      0.91%     89.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1203     10.34%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                11761                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.105397                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.616339                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     7565                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  1069                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      2256                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                    64                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                    807                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  361                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   160                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  12930                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   452                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                    807                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     7781                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                     440                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            384                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      2100                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   249                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  12283                       # Number of instructions processed by rename
-system.cpu.rename.IQFullEvents                     13                       # Number of times rename has blocked due to IQ full
+system.cpu.fetch.rateDist::total                11638                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.104429                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.608041                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     7505                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  1074                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      2213                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                    62                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                    784                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  351                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   161                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  12646                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   460                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                    784                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     7717                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                     446                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            386                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      2059                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   246                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  11999                       # Number of instructions processed by rename
+system.cpu.rename.IQFullEvents                     10                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                   203                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               10602                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 20025                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            19970                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               10316                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 19600                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            19545                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                55                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  5007                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                     5595                       # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts                 26                       # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts             26                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                       552                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2098                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1917                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                63                       # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores               31                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      11001                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  65                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                      9282                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               167                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            4968                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         4343                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             49                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         11761                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.789219                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.523023                       # Number of insts issued each cycle
+system.cpu.rename.CommittedMaps                  4998                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                     5318                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts                 28                       # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts             28                       # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts                       543                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2051                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1909                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                56                       # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores               30                       # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded                      10820                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  64                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                      9196                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               160                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            4794                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         4145                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             48                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         11638                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.790170                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.525459                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0                8303     70.60%     70.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1127      9.58%     80.18% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                 767      6.52%     86.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 536      4.56%     91.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 478      4.06%     95.32% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 324      2.75%     98.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 139      1.18%     99.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  49      0.42%     99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  38      0.32%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0                8215     70.59%     70.59% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1109      9.53%     80.12% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                 778      6.68%     86.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 515      4.43%     91.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 472      4.06%     95.28% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 322      2.77%     98.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 140      1.20%     99.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  48      0.41%     99.66% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  39      0.34%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           11761                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           11638                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       5      2.87%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.87% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     78     44.83%     47.70% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    91     52.30%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                       4      2.34%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.34% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     75     43.86%     46.20% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    92     53.80%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  5709     61.51%     61.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.53% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1861     20.05%     81.58% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1710     18.42%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  5661     61.56%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     61.56% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     61.58% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1833     19.93%     81.51% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1700     18.49%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                   9282                       # Type of FU issued
-system.cpu.iq.rate                           0.392889                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         174                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.018746                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              30604                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             16005                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses         8374                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                   9196                       # Type of FU issued
+system.cpu.iq.rate                           0.390853                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         171                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.018595                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              30299                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             15649                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses         8318                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  62                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 36                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           27                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                   9422                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                   9333                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      34                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               70                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               65                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1136                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1090                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            1                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation            7                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          871                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          863                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                    807                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     227                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    22                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               11066                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               108                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2098                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1917                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                    784                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     229                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    24                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               10884                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               101                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2051                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1909                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 54                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      9                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIQFullEvents                     11                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     3                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents              7                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             78                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          309                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  387                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                  8779                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1716                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               503                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             77                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          302                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  379                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                  8699                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1698                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts               497                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3289                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1382                       # Number of branches executed
-system.cpu.iew.exec_stores                       1573                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.371598                       # Inst execution rate
-system.cpu.iew.wb_sent                           8575                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                          8401                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      4358                       # num instructions producing a value
-system.cpu.iew.wb_consumers                      6997                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3253                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1376                       # Number of branches executed
+system.cpu.iew.exec_stores                       1555                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.369730                       # Inst execution rate
+system.cpu.iew.wb_sent                           8502                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                          8345                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      4327                       # num instructions producing a value
+system.cpu.iew.wb_consumers                      6939                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.355598                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.622838                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.354684                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.623577                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           5800                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps             5800                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            5275                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts           5792                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5792                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            5101                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               301                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        10954                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.529487                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.308345                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               292                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        10854                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.533628                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.316329                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0         8509     77.68%     77.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1052      9.60%     87.28% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          645      5.89%     93.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          263      2.40%     95.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          183      1.67%     97.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          104      0.95%     98.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6           63      0.58%     98.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           41      0.37%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           94      0.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0         8424     77.61%     77.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1042      9.60%     87.21% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          639      5.89%     93.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          261      2.40%     95.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          182      1.68%     97.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          104      0.96%     98.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6           67      0.62%     98.76% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           41      0.38%     99.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           94      0.87%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        10954                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 5800                       # Number of instructions committed
-system.cpu.commit.committedOps                   5800                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        10854                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                 5792                       # Number of instructions committed
+system.cpu.commit.committedOps                   5792                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           2008                       # Number of memory references committed
-system.cpu.commit.loads                           962                       # Number of loads committed
+system.cpu.commit.refs                           2007                       # Number of memory references committed
+system.cpu.commit.loads                           961                       # Number of loads committed
 system.cpu.commit.membars                           7                       # Number of memory barriers committed
-system.cpu.commit.branches                       1038                       # Number of branches committed
+system.cpu.commit.branches                       1037                       # Number of branches committed
 system.cpu.commit.fp_insts                         22                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      5706                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      5698                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  103                       # Number of function calls committed.
 system.cpu.commit.bw_lim_events                    94                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        21935                       # The number of ROB reads
-system.cpu.rob.rob_writes                       22958                       # The number of ROB writes
-system.cpu.timesIdled                             232                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           11864                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        5800                       # Number of Instructions Simulated
-system.cpu.committedOps                          5800                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                  5800                       # Number of Instructions Simulated
-system.cpu.cpi                               4.073276                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.073276                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.245503                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.245503                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    13900                       # number of integer regfile reads
-system.cpu.int_regfile_writes                    7266                       # number of integer regfile writes
+system.cpu.rob.rob_reads                        21653                       # The number of ROB reads
+system.cpu.rob.rob_writes                       22571                       # The number of ROB writes
+system.cpu.timesIdled                             234                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           11890                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        5792                       # Number of Instructions Simulated
+system.cpu.committedOps                          5792                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  5792                       # Number of Instructions Simulated
+system.cpu.cpi                               4.062155                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.062155                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.246175                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.246175                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    13809                       # number of integer regfile reads
+system.cpu.int_regfile_writes                    7224                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        25                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        2                       # number of floating regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                172.776641                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1462                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    357                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   4.095238                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                172.502715                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1427                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    356                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   4.008427                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     172.776641                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.084364                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.084364                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1462                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1462                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1462                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1462                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1462                       # number of overall hits
-system.cpu.icache.overall_hits::total            1462                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          435                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           435                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          435                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            435                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          435                       # number of overall misses
-system.cpu.icache.overall_misses::total           435                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16386000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16386000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16386000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16386000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16386000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16386000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1897                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1897                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1897                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1897                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1897                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.229309                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.229309                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.229309                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.229309                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.229309                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.229309                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37668.965517                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 37668.965517                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 37668.965517                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 37668.965517                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 37668.965517                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 37668.965517                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     172.502715                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.084230                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.084230                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1427                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1427                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1427                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1427                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1427                       # number of overall hits
+system.cpu.icache.overall_hits::total            1427                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          432                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           432                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          432                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            432                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          432                       # number of overall misses
+system.cpu.icache.overall_misses::total           432                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16299000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16299000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16299000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16299000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16299000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16299000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1859                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1859                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1859                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1859                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1859                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1859                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.232383                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.232383                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.232383                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.232383                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.232383                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.232383                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37729.166667                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37729.166667                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37729.166667                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37729.166667                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37729.166667                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37729.166667                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -365,94 +365,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           78                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           78                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           78                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           78                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           78                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          357                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          357                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          357                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          357                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          357                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          357                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13154500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     13154500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13154500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     13154500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13154500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     13154500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.188192                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.188192                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188192                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.188192                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36847.338936                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36847.338936                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36847.338936                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36847.338936                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           76                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           76                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           76                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           76                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           76                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           76                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          356                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          356                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          356                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          356                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          356                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          356                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13111000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13111000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13111000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13111000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13111000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13111000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.191501                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.191501                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.191501                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.191501                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.191501                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.191501                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36828.651685                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36828.651685                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36828.651685                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36828.651685                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36828.651685                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36828.651685                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 63.298936                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2197                       # Total number of references to valid blocks.
-system.cpu.dcache.sampled_refs                    100                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  21.970000                       # Average number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 63.218136                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2196                       # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs                    101                       # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs                  21.742574                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      63.298936                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.015454                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.015454                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1480                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1480                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      63.218136                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.015434                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.015434                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1479                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1479                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          717                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            717                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2197                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2197                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2197                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2197                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data           92                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total            92                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2196                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2196                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2196                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2196                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            91                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          329                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          329                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          421                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            421                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          421                       # number of overall misses
-system.cpu.dcache.overall_misses::total           421                       # number of overall misses
+system.cpu.dcache.demand_misses::cpu.data          420                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            420                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          420                       # number of overall misses
+system.cpu.dcache.overall_misses::total           420                       # number of overall misses
 system.cpu.dcache.ReadReq_miss_latency::cpu.data      3732500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total      3732500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     12822500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     12822500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     16555000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     16555000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     16555000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     16555000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1572                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1572                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     12824500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     12824500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16557000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16557000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16557000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16557000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1570                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1570                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2618                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2618                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2618                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2618                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.058524                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.058524                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2616                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2616                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2616                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2616                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.057962                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.057962                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.314532                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.314532                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.160810                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.160810                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.160810                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.160810                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40570.652174                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 40570.652174                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38974.164134                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38974.164134                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39323.040380                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39323.040380                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39323.040380                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39323.040380                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.160550                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.160550                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.160550                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.160550                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41016.483516                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 41016.483516                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38980.243161                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 38980.243161                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 39421.428571                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 39421.428571                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 39421.428571                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 39421.428571                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -461,119 +461,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           39                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           39                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           37                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           37                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          282                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          282                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          321                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          321                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          321                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          321                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          319                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          319                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           47                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total           47                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          100                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          100                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          100                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          100                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2119000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2119000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2085000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2085000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4204000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      4204000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4204000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      4204000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.033715                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.033715                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          101                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          101                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2168500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2168500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2086000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2086000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      4254500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4254500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      4254500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.034395                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.034395                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.044933                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.044933                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038197                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.038197                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038197                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.038197                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39981.132075                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39981.132075                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44361.702128                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44361.702128                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        42040                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total        42040                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        42040                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total        42040                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.038609                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.038609                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.038609                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.038609                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40157.407407                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40157.407407                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44382.978723                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44382.978723                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42123.762376                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 42123.762376                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42123.762376                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 42123.762376                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               203.410235                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               203.045072                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       5                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   405                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.012346                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    171.891736                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.518500                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.005246                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000962                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.006208                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    171.614713                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.430359                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005237                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000959                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006196                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              5                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            5                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               5                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            5                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              5                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          352                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          351                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           54                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          405                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           47                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           47                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          352                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          100                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          351                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          101                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           452                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          352                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          100                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          351                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          101                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          452                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12780500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2060500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     14841000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2028000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2028000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     12780500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      4088500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     16869000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     12780500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      4088500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     16869000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          357                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     12737500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2108500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14846000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2028500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2028500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     12737500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4137000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16874500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     12737500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4137000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16874500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          356                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          410                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           47                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           47                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          357                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          100                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          356                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          101                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          357                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          100                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          356                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          101                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985994                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.985955                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.987805                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985994                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.985955                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.989059                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985994                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.985955                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.989059                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36308.238636                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38877.358491                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 36644.444444                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43148.936170                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43148.936170                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36308.238636                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data        40885                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 37320.796460                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36308.238636                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data        40885                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 37320.796460                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36289.173789                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 39046.296296                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36656.790123                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43159.574468                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43159.574468                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36289.173789                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40960.396040                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 37332.964602                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36289.173789                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40960.396040                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 37332.964602                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -582,50 +582,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          352                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          351                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          405                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           47                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           47                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          352                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          100                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          351                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          101                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          452                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          352                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          100                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          351                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          101                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          452                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11653500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1896000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13549500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1881500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1881500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11653500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3777500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     15431000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11653500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3777500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     15431000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11613500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1942500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13556000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1882000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1882000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11613500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3824500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15438000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11613500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3824500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15438000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.985955                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.987805                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.985955                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.989059                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985994                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.985955                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.989059                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35773.584906                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33455.555556                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40031.914894                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40031.914894                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        37775                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34139.380531                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33106.534091                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        37775                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34139.380531                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33086.894587                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35972.222222                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33471.604938                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40042.553191                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40042.553191                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33086.894587                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37866.336634                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34154.867257                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33086.894587                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37866.336634                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34154.867257                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index aaab5c18bc80d4ce6042610d560d146ebea3ae26..4d595ae508cb9fbf00c565619885f54d18b8c13a 100644 (file)
@@ -100,8 +100,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index b409adbd26d95a559274121e0e548c8760d53e92..0d5c52051a06b31bb363f309c4a5e7188e1557d6 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 11:59:33
-gem5 started Jun  4 2012 14:44:21
+gem5 compiled Aug 13 2012 17:02:09
+gem5 started Aug 13 2012 18:12:35
 gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 2900000 because target called exit()
+Exiting @ tick 2896000 because target called exit()
index c355893c5341f379a0461d31618588ca6c177828..626b229dbaa6c1ec0649f8ad26e1d610c251ffec 100644 (file)
@@ -1,38 +1,38 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2900000                       # Number of ticks simulated
-final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2896000                       # Number of ticks simulated
+final_tick                                    2896000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1223636                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1219143                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              607261041                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 202160                       # Number of bytes of host memory used
-host_seconds                                     0.00                       # Real time elapsed on the host
-sim_insts                                        5801                       # Number of instructions simulated
-sim_ops                                          5801                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             23204                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              3721                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26925                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        23204                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           23204                       # Number of instructions bytes read from this memory
+host_inst_rate                                 332855                       # Simulator instruction rate (inst/s)
+host_op_rate                                   332536                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              166086520                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209936                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+sim_insts                                        5793                       # Number of instructions simulated
+sim_ops                                          5793                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             23172                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              3720                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26892                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        23172                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           23172                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           4209                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              4209                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5801                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                962                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6763                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5793                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                961                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6754                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data              1046                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                 1046                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           8001379310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1283103448                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9284482759                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      8001379310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         8001379310                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1451379310                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1451379310                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          8001379310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2734482759                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10735862069                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           8001381215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1284530387                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9285911602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      8001381215                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         8001381215                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1453383978                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1453383978                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          8001381215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2737914365                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10739295580                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -52,26 +52,26 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                    9                       # Number of system calls
-system.cpu.numCycles                             5801                       # number of cpu cycles simulated
+system.cpu.numCycles                             5793                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5801                       # Number of instructions committed
-system.cpu.committedOps                          5801                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  5706                       # Number of integer alu accesses
+system.cpu.committedInsts                        5793                       # Number of instructions committed
+system.cpu.committedOps                          5793                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  5698                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
 system.cpu.num_func_calls                         200                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          896                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         5706                       # number of integer instructions
+system.cpu.num_conditional_control_insts          895                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         5698                       # number of integer instructions
 system.cpu.num_fp_insts                            22                       # number of float instructions
-system.cpu.num_int_register_reads                9541                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               5005                       # number of times the integer registers were written
+system.cpu.num_int_register_reads                9529                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4996                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                   20                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   2                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          2008                       # number of memory refs
-system.cpu.num_load_insts                         962                       # Number of load instructions
+system.cpu.num_mem_refs                          2007                       # number of memory refs
+system.cpu.num_load_insts                         961                       # Number of load instructions
 system.cpu.num_store_insts                       1046                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5801                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5793                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index dd53d4220dc781b793725d8dc37bea22d226a54f..9d387b483dda0a9689f9cd5e3ca8d80b054f060b 100644 (file)
@@ -214,7 +214,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index a234b881df57d969d6219fdd030fa2b512870a10..c486c847c0564971b3e4fbbaa476e8df9846ef93 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:30:03
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:12:48
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 18885500 because target called exit()
+Hello World!Exiting @ tick 18878500 because target called exit()
index fa8b51b5a53695c2063d018bddb5d7f170eebfeb..00104c1c9104e6033065c9f8806e43b12ad2dc02 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000019                       # Number of seconds simulated
-sim_ticks                                    18885500                       # Number of ticks simulated
-final_tick                                   18885500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    18878500                       # Number of ticks simulated
+final_tick                                   18878500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37135                       # Simulator instruction rate (inst/s)
-host_op_rate                                    37131                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              131302803                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220012                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-sim_insts                                        5340                       # Number of instructions simulated
-sim_ops                                          5340                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  36734                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36730                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              130153209                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229488                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
+sim_insts                                        5327                       # Number of instructions simulated
+sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             18496                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                27072                       # Number of bytes read from this memory
@@ -19,134 +19,134 @@ system.physmem.bytes_inst_read::total           18496                       # Nu
 system.physmem.num_reads::cpu.inst                289                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   423                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            979375712                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            454105001                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1433480713                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       979375712                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          979375712                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           979375712                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           454105001                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1433480713                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            979738856                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            454273380                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1434012236                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       979738856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          979738856                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           979738856                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           454273380                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1434012236                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            37772                       # number of cpu cycles simulated
+system.cpu.numCycles                            37758                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              1615                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted         1022                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect          899                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           1170                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits               435                       # Number of BTB hits
+system.cpu.branch_predictor.lookups              1630                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted         1036                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect          901                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups           1165                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits               438                       # Number of BTB hits
 system.cpu.branch_predictor.usedRAS                67                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            4                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       37.179487                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken          502                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         1113                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads         5634                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites         4000                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses         9634                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.BTBHitPct       37.596567                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken          505                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken         1125                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads         5623                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites         3988                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses         9611                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           1686                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       1487                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect          319                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect          517                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted            836                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.predicted               280                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     74.910394                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions             3979                       # Number of Instructions Executed.
+system.cpu.regfile_manager.regForwards           1685                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       1483                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect          334                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect          504                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted            838                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.predicted               277                       # Number of Branches Incorrectly Predicted
+system.cpu.execution_unit.mispredictPct     75.156951                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions             3966                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
-system.cpu.threadCycles                         10178                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.threadCycles                         10163                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             501                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           31527                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                             6245                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         16.533411                       # Percentage of cycles cpu is active
-system.cpu.comLoads                               716                       # Number of Load instructions committed
+system.cpu.timesIdled                             500                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           31528                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                             6230                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         16.499815                       # Percentage of cycles cpu is active
+system.cpu.comLoads                               715                       # Number of Load instructions committed
 system.cpu.comStores                              673                       # Number of Store instructions committed
-system.cpu.comBranches                           1116                       # Number of Branches instructions committed
+system.cpu.comBranches                           1115                       # Number of Branches instructions committed
 system.cpu.comNops                                173                       # Number of Nop instructions committed
 system.cpu.comNonSpec                             106                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               2537                       # Number of Integer instructions committed
+system.cpu.comInts                               2526                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5340                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                          5340                       # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts                        5327                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5327                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                  5340                       # Number of Instructions committed (Total)
-system.cpu.cpi                               7.073408                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total                  5327                       # Number of Instructions committed (Total)
+system.cpu.cpi                               7.088042                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         7.073408                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.141375                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         7.088042                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.141083                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.141375                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    33203                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                      4569                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               12.096262                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    34575                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      3197                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization                8.463942                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    34722                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      3050                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization                8.074764                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    36789                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                       983                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                2.602457                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    34600                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      3172                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization                8.397755                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.141083                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    33195                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                      4563                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               12.084856                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    34564                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      3194                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization                8.459134                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    34714                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      3044                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization                8.061868                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    36776                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                       982                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                2.600773                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    34592                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      3166                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization                8.384978                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                136.494329                       # Cycle average of tags in use
-system.cpu.icache.total_refs                      825                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                136.498326                       # Cycle average of tags in use
+system.cpu.icache.total_refs                      829                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    291                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   2.835052                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   2.848797                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     136.494329                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.066648                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.066648                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst          825                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total             825                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst           825                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total              825                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst          825                       # number of overall hits
-system.cpu.icache.overall_hits::total             825                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     136.498326                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.066650                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.066650                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          829                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             829                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           829                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              829                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          829                       # number of overall hits
+system.cpu.icache.overall_hits::total             829                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          350                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           350                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          350                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            350                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          350                       # number of overall misses
 system.cpu.icache.overall_misses::total           350                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     19647000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     19647000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     19647000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     19647000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     19647000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     19647000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1175                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1175                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1175                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1175                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1175                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1175                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.297872                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.297872                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.297872                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.297872                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.297872                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.297872                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56134.285714                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 56134.285714                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 56134.285714                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 56134.285714                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 56134.285714                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 56134.285714                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19654500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19654500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19654500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19654500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19654500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19654500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1179                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1179                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1179                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1179                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1179                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.296862                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.296862                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.296862                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.296862                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.296862                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.296862                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56155.714286                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 56155.714286                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56155.714286                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 56155.714286                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56155.714286                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 56155.714286                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets       106000                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_targets       109000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_targets               3                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles::no_targets 36333.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.ReadReq_mshr_hits::cpu.inst           59                       # number of ReadReq MSHR hits
@@ -161,42 +161,42 @@ system.cpu.icache.demand_mshr_misses::cpu.inst          291
 system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15992500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     15992500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15992500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     15992500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15992500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     15992500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.247660                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.247660                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.247660                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.247660                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54957.044674                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54957.044674                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54957.044674                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54957.044674                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15991000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15991000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15991000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15991000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15991000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15991000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.246819                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.246819                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.246819                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.246819                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.246819                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.246819                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54951.890034                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54951.890034                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54951.890034                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54951.890034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54951.890034                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54951.890034                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.670041                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1046                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 82.673308                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1045                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   7.748148                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   7.740741                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.670041                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020183                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020183                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data          655                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             655                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      82.673308                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020184                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020184                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          654                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             654                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          391                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            391                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1046                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1046                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1046                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1046                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1045                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1045                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1045                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1045                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            61                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          282                       # number of WriteReq misses
@@ -205,38 +205,38 @@ system.cpu.dcache.demand_misses::cpu.data          343                       # n
 system.cpu.dcache.demand_misses::total            343                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data          343                       # number of overall misses
 system.cpu.dcache.overall_misses::total           343                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      3569500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      3569500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     17306500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     17306500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     20876000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     20876000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     20876000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     20876000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          716                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3569000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3569000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     17304500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     17304500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     20873500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     20873500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     20873500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     20873500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         1389                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         1389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085196                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.085196                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         1388                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1388                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1388                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1388                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085315                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.085315                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.419019                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.419019                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.246940                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.246940                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.246940                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.246940                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58516.393443                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58516.393443                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.567376                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.567376                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60862.973761                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60862.973761                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60862.973761                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60862.973761                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.247118                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.247118                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.247118                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.247118                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58508.196721                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58508.196721                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61363.475177                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 61363.475177                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 60855.685131                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 60855.685131                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 60855.685131                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 60855.685131                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      2306500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -261,42 +261,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          135
 system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3065000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      3065000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4526000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      4526000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7591000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      7591000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7591000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      7591000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3064500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3064500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4525000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4525000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7589500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7589500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56759.259259                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56759.259259                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55876.543210                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55876.543210                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56229.629630                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 56229.629630                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56229.629630                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 56229.629630                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        56750                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        56750                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55864.197531                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 55864.197531                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56218.518519                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 56218.518519                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56218.518519                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 56218.518519                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               162.084916                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               162.089529                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.008772                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    136.002391                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     26.082525                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004150                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    136.006338                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.083191                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004151                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000796                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004946                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004947                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
@@ -317,17 +317,17 @@ system.cpu.l2cache.demand_misses::total           423                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15656000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2985500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18641500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4434500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      4434500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15656000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      7420000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23076000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15656000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      7420000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23076000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15654000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2985000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18639000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4433500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4433500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15654000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7418500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23072500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15654000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7418500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23072500                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
@@ -350,17 +350,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.992958                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.992958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54173.010381                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56330.188679                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 54507.309942                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54746.913580                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54746.913580                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54173.010381                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55373.134328                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 54553.191489                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54173.010381                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55373.134328                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 54553.191489                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54166.089965                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56320.754717                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total        54500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54734.567901                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54734.567901                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54166.089965                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55361.940299                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 54544.917258                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54166.089965                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55361.940299                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 54544.917258                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -380,17 +380,17 @@ system.cpu.l2cache.demand_mshr_misses::total          423
 system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12139500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2343500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14483000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12139000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2343000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14482000                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3454500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3454500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12139500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5798000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     17937500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12139500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5798000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     17937500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12139000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5797500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17936500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12139000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5797500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17936500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.991304                       # mshr miss rate for ReadReq accesses
@@ -402,17 +402,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.992958
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.992958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44216.981132                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42347.953216                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42003.460208                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 44207.547170                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42345.029240                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42648.148148                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42648.148148                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43268.656716                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42405.437352                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42005.190311                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43268.656716                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42405.437352                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42003.460208                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43264.925373                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42403.073286                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42003.460208                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43264.925373                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42403.073286                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 9462bf4605909c3fc0a5e408bce54c6c60f084d3..69d80e31f6d26aacbbb436ad2f4096342e069af6 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index a096c270559b291f25436f520e843bd88293398a..3e672ef034da6a7cfb66367a7be66f381dd8dc12 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:44:41
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:12:59
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 2701000 because target called exit()
+Hello World!Exiting @ tick 2694500 because target called exit()
index c78599e754eb22d78960208264ce5ffc567d7051..9a9c3bf5691ecf65f8024276b8b280cc68960a89 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000003                       # Number of seconds simulated
-sim_ticks                                     2701000                       # Number of ticks simulated
-final_tick                                    2701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     2694500                       # Number of ticks simulated
+final_tick                                    2694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 947128                       # Simulator instruction rate (inst/s)
-host_op_rate                                   944143                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              476131381                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212364                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        5340                       # Number of instructions simulated
-sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21532                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              4603                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26135                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21532                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21532                       # Number of instructions bytes read from this memory
+host_inst_rate                                 126208                       # Simulator instruction rate (inst/s)
+host_op_rate                                   126157                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63788253                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221040                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+sim_insts                                        5327                       # Number of instructions simulated
+sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             21480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4602                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26082                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21480                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           5065                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              5065                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                716                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6099                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5370                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                715                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6085                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               673                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  673                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7971862273                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1704183636                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9676045909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7971862273                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7971862273                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1875231396                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1875231396                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7971862273                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          3579415031                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            11551277305                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7971794396                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1707923548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9679717944                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7971794396                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7971794396                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1879755057                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1879755057                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7971794396                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          3587678605                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            11559473001                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                             5403                       # number of cpu cycles simulated
+system.cpu.numCycles                             5390                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5340                       # Number of instructions committed
-system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.committedInsts                        5327                       # Number of instructions committed
+system.cpu.committedOps                          5327                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4505                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          774                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_conditional_control_insts          773                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4505                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4859                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               10598                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4846                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1401                       # number of memory refs
+system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                       5403                       # Number of busy cycles
+system.cpu.num_busy_cycles                       5390                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 671f9029614e85543a81fbb33cec04174dc1b8ef..631d050da4d2898a00989ca811c4d15e90dde4eb 100644 (file)
@@ -78,7 +78,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index f8d1a8b44274fe52474c560503530f2c62b71dc0..b90476d27b2304325eb5a533eb5c4b23e15d97e7 100755 (executable)
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:56:55
-gem5 started Jul 10 2012 17:57:35
-gem5 executing on sc2b0605
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:09
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index 4bb30bdf1e16e4781847560f49668a7977c80eba..4125da946b60fdf7af16bbff5e0438628d4500f3 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000253                       # Nu
 sim_ticks                                      253364                       # Number of ticks simulated
 final_tick                                     253364                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  42932                       # Simulator instruction rate (inst/s)
-host_op_rate                                    42926                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                2036393                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 243564                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-sim_insts                                        5340                       # Number of instructions simulated
-sim_ops                                          5340                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             21532                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              4603                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                26135                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        21532                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           21532                       # Number of instructions bytes read from this memory
+host_inst_rate                                  38246                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38242                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1818652                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240496                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
+sim_insts                                        5327                       # Number of instructions simulated
+sim_ops                                          5327                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             21480                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              4602                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                26082                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        21480                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           21480                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           5065                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              5065                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               5383                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                716                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  6099                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               5370                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                715                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  6085                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               673                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  673                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst             84984449                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             18167538                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               103151987                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst        84984449                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           84984449                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst             84779211                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             18163591                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               102942802                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst        84779211                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           84779211                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            19991001                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               19991001                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst            84984449                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38158539                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              123142988                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst            84779211                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38154592                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              122933803                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.cacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -43,20 +43,20 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5340                       # Number of instructions committed
-system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.committedInsts                        5327                       # Number of instructions committed
+system.cpu.committedOps                          5327                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4505                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          774                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_conditional_control_insts          773                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4505                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               10598                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4845                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1401                       # number of memory refs
+system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     253364                       # Number of busy cycles
index 53f402a63c12d51644e6d637d88cac18cc1d76d9..62c147fd52f972c26b147bfa21d6bcded04185ee 100644 (file)
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 81bff15c43fc765b3ac258b9157545f2a49e8f7e..2fc16fb0fac4a7e50ec83fe80480a2b37aebc17a 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:30:26
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:07
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 29541000 because target called exit()
+Hello World!Exiting @ tick 29527000 because target called exit()
index d0e2c9d973868ce7991bad31a7a4ffddf70f116d..3eb56a69e7820442a5d83aff940b3277af36a50f 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29541000                       # Number of ticks simulated
-final_tick                                   29541000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    29527000                       # Number of ticks simulated
+final_tick                                   29527000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  73924                       # Simulator instruction rate (inst/s)
-host_op_rate                                    73907                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              408761366                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220016                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
-sim_insts                                        5340                       # Number of instructions simulated
-sim_ops                                          5340                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  69145                       # Simulator instruction rate (inst/s)
+host_op_rate                                    69130                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              383102769                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229488                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
+sim_insts                                        5327                       # Number of instructions simulated
+sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             16320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                24896                       # Number of bytes read from this memory
@@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total           16320                       # Nu
 system.physmem.num_reads::cpu.inst                255                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   389                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            552452524                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            290308385                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               842760909                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       552452524                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          552452524                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           552452524                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           290308385                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              842760909                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            552714465                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            290446032                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               843160497                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       552714465                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          552714465                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           552714465                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           290446032                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              843160497                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            59082                       # number of cpu cycles simulated
+system.cpu.numCycles                            59054                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5340                       # Number of instructions committed
-system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
+system.cpu.committedInsts                        5327                       # Number of instructions committed
+system.cpu.committedOps                          5327                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  4505                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          774                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         4517                       # number of integer instructions
+system.cpu.num_conditional_control_insts          773                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         4505                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               10620                       # number of times the integer registers were read
-system.cpu.num_int_register_writes               4858                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               10598                       # number of times the integer registers were read
+system.cpu.num_int_register_writes               4845                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1402                       # number of memory refs
-system.cpu.num_load_insts                         724                       # Number of load instructions
+system.cpu.num_mem_refs                          1401                       # number of memory refs
+system.cpu.num_load_insts                         723                       # Number of load instructions
 system.cpu.num_store_insts                        678                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      59082                       # Number of busy cycles
+system.cpu.num_busy_cycles                      59054                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                117.079183                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     5127                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                117.127109                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     5114                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  19.949416                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  19.898833                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     117.079183                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.057168                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.057168                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         5127                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5127                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5127                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5127                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5127                       # number of overall hits
-system.cpu.icache.overall_hits::total            5127                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     117.127109                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.057191                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.057191                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5114                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5114                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5114                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5114                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5114                       # number of overall hits
+system.cpu.icache.overall_hits::total            5114                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          257                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           257                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          257                       # number of demand (read+write) misses
@@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     14308000
 system.cpu.icache.demand_miss_latency::total     14308000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     14308000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     14308000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5384                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5384                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5384                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5384                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5384                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5384                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.047734                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.047734                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.047734                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.047734                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.047734                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.047734                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         5371                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5371                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5371                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5371                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5371                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5371                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.047850                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.047850                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.047850                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.047850                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.047850                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.047850                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 55673.151751                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
@@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13537000
 system.cpu.icache.demand_mshr_miss_latency::total     13537000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13537000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     13537000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.047734                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.047734                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.047734                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.047850                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.047850                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047850                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.047850                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
@@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 82.107175                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1254                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 82.138993                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1253                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                   9.288889                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   9.281481                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      82.107175                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020046                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020046                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data          662                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total             662                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      82.138993                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020053                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020053                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          661                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             661                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            592                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1254                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1254                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1254                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1254                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1253                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1253                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1253                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1253                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           54                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            54                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
@@ -161,22 +161,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7518000
 system.cpu.dcache.demand_miss_latency::total      7518000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7518000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7518000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data          716                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data          715                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          715                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         1389                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         1389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075419                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.075419                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         1388                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1388                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1388                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1388                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075524                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.075524                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.120357                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.120357                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.097192                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.097192                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.097192                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.097192                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.097262                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.097262                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.097262                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.097262                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 55222.222222                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7113000
 system.cpu.dcache.demand_mshr_miss_latency::total      7113000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7113000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7113000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075524                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.075524                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.120357                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.097262                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097262                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.097262                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               142.223187                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               142.279716                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       3                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    116.548564                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     25.674623                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003557                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    116.596239                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     25.683477                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003558                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000784                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004340                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004342                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
index 73bd7007935bec80b238810d4d7e218bb1ac97e7..5085616c4ee24bea59b1fe09a6a622620f711a6d 100644 (file)
@@ -533,7 +533,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index 3bef840f70cb0a96d3575ae38aa502e3adf4c5d0..f4d9273f51bc875af30bb9fb7b717c1412bac6f8 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 12:38:36
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:22:30
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 12803000 because target called exit()
+Exiting @ tick 12789500 because target called exit()
index d0e4f2a1604d18633aadda30c5637723e7fe12b0..89fb2bf275f05790d73e7db6fdead3a4819a59e2 100644 (file)
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000013                       # Number of seconds simulated
-sim_ticks                                    12803000                       # Number of ticks simulated
-final_tick                                   12803000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    12789500                       # Number of ticks simulated
+final_tick                                   12789500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24032                       # Simulator instruction rate (inst/s)
-host_op_rate                                    43521                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               56800152                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227452                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
-sim_insts                                        5416                       # Number of instructions simulated
-sim_ops                                          9809                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             19264                       # Number of bytes read from this memory
+host_inst_rate                                  20973                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37987                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               49851854                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 232356                       # Number of bytes of host memory used
+host_seconds                                     0.26                       # Real time elapsed on the host
+sim_insts                                        5380                       # Number of instructions simulated
+sim_ops                                          9745                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             19456                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9280                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                28544                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        19264                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           19264                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                301                       # Number of read requests responded to by this memory
+system.physmem.bytes_read::total                28736                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        19456                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           19456                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                304                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                145                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   446                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1504647348                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            724830118                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              2229477466                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1504647348                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1504647348                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1504647348                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           724830118                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             2229477466                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   449                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu.inst           1521247899                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            725595215                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              2246843113                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1521247899                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1521247899                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1521247899                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           725595215                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             2246843113                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            25607                       # number of cpu cycles simulated
+system.cpu.numCycles                            25580                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     3125                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3125                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect                558                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  2605                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      830                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     3138                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3138                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect                562                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  2607                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      814                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                        0                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                   0                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               8034                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          14981                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        3125                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches                830                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          4070                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    2483                       # Number of cycles fetch has spent squashing
-system.cpu.fetch.BlockedCycles                   3408                       # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles                   41                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles           244                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      1957                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   281                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              17679                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.502687                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.975668                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles               8037                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          15123                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        3138                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches                814                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          4093                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    2492                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.BlockedCycles                   3369                       # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles                   27                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles           178                       # Number of stall cycles due to pending traps
+system.cpu.fetch.CacheLines                      1950                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   284                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              17601                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.521504                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.991998                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    13710     77.55%     77.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      177      1.00%     78.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      164      0.93%     79.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      211      1.19%     80.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      170      0.96%     81.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      182      1.03%     82.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      260      1.47%     84.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      162      0.92%     85.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2643     14.95%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    13611     77.33%     77.33% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      183      1.04%     78.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      154      0.87%     79.25% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      201      1.14%     80.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      179      1.02%     81.40% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      174      0.99%     82.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      262      1.49%     83.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      168      0.95%     84.84% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2669     15.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                17679                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.122037                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.585035                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                     8588                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  3390                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      3692                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   127                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1882                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  25327                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1882                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                     8910                       # Number of cycles rename is idle
+system.cpu.fetch.rateDist::total                17601                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.122674                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.591204                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                     8517                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  3363                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      3698                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   126                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   1897                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  25566                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1897                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                     8847                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                    2031                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            505                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      3461                       # Number of cycles rename is running
-system.cpu.rename.UnblockCycles                   890                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  23802                       # Number of instructions processed by rename
+system.cpu.rename.serializeStallCycles            471                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      3459                       # Number of cycles rename is running
+system.cpu.rename.UnblockCycles                   896                       # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts                  24019                       # Number of instructions processed by rename
 system.cpu.rename.ROBFullEvents                     3                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                     47                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                   747                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.IQFullEvents                     44                       # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents                   760                       # Number of times rename has blocked due to LSQ full
 system.cpu.rename.FullRegisterEvents                1                       # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands               34224                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 68607                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            68591                       # Number of integer rename lookups
+system.cpu.rename.RenamedOperands               34373                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 69151                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            69135                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                16                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                 14707                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    19517                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps                 14595                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                    19778                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 35                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             35                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      1875                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2306                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1775                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                      1918                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2391                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1803                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                14                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                4                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      21232                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded                  40                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     17582                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued                92                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           10865                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined        19620                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved             27                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         17679                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.994513                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.826049                       # Number of insts issued each cycle
+system.cpu.iq.iqInstsAdded                      21439                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded                  41                       # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued                     17729                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                95                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11045                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined        19872                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved             28                       # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples         17601                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         1.007272                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.841273                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               12114     68.52%     68.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                1582      8.95%     77.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                1012      5.72%     83.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                 689      3.90%     87.09% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 696      3.94%     91.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 692      3.91%     94.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 627      3.55%     98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                 233      1.32%     99.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  34      0.19%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               12034     68.37%     68.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                1562      8.87%     77.25% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                1007      5.72%     82.97% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                 685      3.89%     86.86% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 692      3.93%     90.79% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 711      4.04%     94.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 630      3.58%     98.41% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                 245      1.39%     99.80% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  35      0.20%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           17679                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           17601                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                     133     73.08%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     73.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     29     15.93%     89.01% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    20     10.99%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                     137     74.46%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     74.46% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     28     15.22%     89.67% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    19     10.33%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 14185     80.68%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.70% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 1924     10.94%     91.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1469      8.36%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 14250     80.38%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     80.40% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 1990     11.22%     91.62% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1485      8.38%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  17582                       # Type of FU issued
-system.cpu.iq.rate                           0.686609                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         182                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.010351                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              53109                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             32144                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        16183                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  17729                       # Type of FU issued
+system.cpu.iq.rate                           0.693081                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         184                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.010378                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              53330                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32532                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        16277                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   8                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  4                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            4                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  17756                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  17905                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       4                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads              148                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads              157                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1250                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses           14                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1339                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses           20                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           11                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          841                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores          869                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1882                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                    1425                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    33                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               21272                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts                46                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  2306                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 1775                       # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts                 36                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                      4                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles                   1897                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                    1429                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    34                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               21480                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts                37                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  2391                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 1803                       # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts                 37                       # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents                      5                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             11                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect             65                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          640                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                  705                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 16602                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  1794                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts               980                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect             68                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          631                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                  699                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 16697                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  1851                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1032                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                             0                       # number of nop insts executed
-system.cpu.iew.exec_refs                         3144                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     1642                       # Number of branches executed
-system.cpu.iew.exec_stores                       1350                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.648338                       # Inst execution rate
-system.cpu.iew.wb_sent                          16384                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         16187                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                     10480                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     24095                       # num instructions consuming a value
+system.cpu.iew.exec_refs                         3217                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     1636                       # Number of branches executed
+system.cpu.iew.exec_stores                       1366                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.652737                       # Inst execution rate
+system.cpu.iew.wb_sent                          16474                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         16281                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                     10466                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     23993                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.632132                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.434945                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.636474                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.436211                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           5416                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps             9809                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           11462                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts           5380                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             9745                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts           11734                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts               589                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        15797                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.620941                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.463366                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts               583                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        15704                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.620543                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.459156                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        12065     76.38%     76.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         1534      9.71%     86.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2          576      3.65%     89.73% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          731      4.63%     94.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          367      2.32%     96.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          129      0.82%     97.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          134      0.85%     98.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           75      0.47%     98.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          186      1.18%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        11988     76.34%     76.34% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         1532      9.76%     86.09% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2          562      3.58%     89.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          734      4.67%     94.35% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          373      2.38%     96.72% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          129      0.82%     97.54% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          134      0.85%     98.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           70      0.45%     98.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          182      1.16%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        15797                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                 5416                       # Number of instructions committed
-system.cpu.commit.committedOps                   9809                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        15704                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                 5380                       # Number of instructions committed
+system.cpu.commit.committedOps                   9745                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           1990                       # Number of memory references committed
-system.cpu.commit.loads                          1056                       # Number of loads committed
+system.cpu.commit.refs                           1986                       # Number of memory references committed
+system.cpu.commit.loads                          1052                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       1214                       # Number of branches committed
+system.cpu.commit.branches                       1208                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                      9714                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                      9650                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                    0                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   186                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   182                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        36882                       # The number of ROB reads
-system.cpu.rob.rob_writes                       44457                       # The number of ROB writes
-system.cpu.timesIdled                             153                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            7928                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        5416                       # Number of Instructions Simulated
-system.cpu.committedOps                          9809                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                  5416                       # Number of Instructions Simulated
-system.cpu.cpi                               4.728028                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         4.728028                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.211505                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.211505                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    35136                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   21832                       # number of integer regfile writes
+system.cpu.rob.rob_reads                        37001                       # The number of ROB reads
+system.cpu.rob.rob_writes                       44889                       # The number of ROB writes
+system.cpu.timesIdled                             154                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            7979                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                        5380                       # Number of Instructions Simulated
+system.cpu.committedOps                          9745                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  5380                       # Number of Instructions Simulated
+system.cpu.cpi                               4.754647                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.754647                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.210321                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.210321                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    35250                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   21824                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
-system.cpu.misc_regfile_reads                    7303                       # number of misc regfile reads
+system.cpu.misc_regfile_reads                    7352                       # number of misc regfile reads
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                144.987593                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     1569                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    302                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   5.195364                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                145.590340                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     1562                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    305                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   5.121311                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     144.987593                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.070795                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.070795                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         1569                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            1569                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          1569                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             1569                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         1569                       # number of overall hits
-system.cpu.icache.overall_hits::total            1569                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     145.590340                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.071089                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.071089                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1562                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1562                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1562                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1562                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1562                       # number of overall hits
+system.cpu.icache.overall_hits::total            1562                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          388                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           388                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          388                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total            388                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst          388                       # number of overall misses
 system.cpu.icache.overall_misses::total           388                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     14367500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     14367500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     14367500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     14367500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     14367500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     14367500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         1957                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         1957                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         1957                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         1957                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         1957                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         1957                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.198263                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.198263                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.198263                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.198263                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.198263                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.198263                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37029.639175                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 37029.639175                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 37029.639175                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 37029.639175                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 37029.639175                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     14396500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     14396500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     14396500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     14396500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     14396500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     14396500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1950                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1950                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1950                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1950                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1950                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1950                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.198974                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.198974                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.198974                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.198974                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.198974                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.198974                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37104.381443                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 37104.381443                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37104.381443                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 37104.381443                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37104.381443                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 37104.381443                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -347,94 +347,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           86                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           86                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           86                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           86                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           86                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           86                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          302                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11138000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     11138000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11138000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     11138000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11138000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     11138000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.154318                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.154318                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.154318                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.154318                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36880.794702                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36880.794702                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 36880.794702                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           83                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           83                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           83                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           83                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           83                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           83                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          305                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          305                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          305                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          305                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          305                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          305                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11253500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11253500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11253500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11253500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11253500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11253500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.156410                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.156410                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.156410                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.156410                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.156410                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.156410                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36896.721311                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36896.721311                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36896.721311                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 36896.721311                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36896.721311                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 36896.721311                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 83.196834                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     2330                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 83.110838                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     2373                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    144                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  16.180556                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  16.479167                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      83.196834                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.020312                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.020312                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1472                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1472                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      83.110838                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020291                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020291                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1515                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1515                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          2330                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             2330                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         2330                       # number of overall hits
-system.cpu.dcache.overall_hits::total            2330                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          112                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           112                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          2373                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2373                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2373                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2373                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data          188                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total            188                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data          188                       # number of overall misses
-system.cpu.dcache.overall_misses::total           188                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data      4401500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total      4401500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data      3078500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total      3078500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data      7480000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total      7480000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data      7480000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total      7480000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1584                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1584                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data          190                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            190                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          190                       # number of overall misses
+system.cpu.dcache.overall_misses::total           190                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4446000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4446000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      3078000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      3078000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7524000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7524000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7524000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7524000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1629                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1629                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         2518                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         2518                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         2518                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         2518                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070707                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.070707                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         2563                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2563                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2563                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2563                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.069982                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.069982                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.081370                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.074662                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.074662                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.074662                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.074662                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39299.107143                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 39299.107143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40506.578947                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 40506.578947                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 39787.234043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 39787.234043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 39787.234043                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074132                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.074132                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074132                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.074132                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        39000                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total        39000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        40500                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total        40500                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        39600                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total        39600                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        39600                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total        39600                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -443,12 +443,12 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data           43                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total           43                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data           43                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total           43                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data           43                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total           43                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           45                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           45                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           45                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           45                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           45                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           45                       # number of overall MSHR hits
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total           69                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
@@ -457,103 +457,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data          145
 system.cpu.dcache.demand_mshr_misses::total          145                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          145                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2699500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      2699500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2850500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      2850500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5550000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total      5550000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5550000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total      5550000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.043561                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.043561                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2719000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2719000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2850000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2850000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5569000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5569000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5569000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5569000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.042357                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.042357                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.081370                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.057585                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.057585                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.057585                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39123.188406                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39123.188406                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37506.578947                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37506.578947                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38275.862069                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 38275.862069                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.056574                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.056574                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.056574                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.056574                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39405.797101                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39405.797101                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        37500                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total        37500                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 38406.896552                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 38406.896552                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 38406.896552                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 38406.896552                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               177.887385                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               178.404292                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   369                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002710                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   372                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002688                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    144.949907                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     32.937478                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004424                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.001005                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005429                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    145.559104                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     32.845188                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004442                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001002                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005444                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          304                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.data           69                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total          370                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          373                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          304                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.data          145                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
+system.cpu.l2cache.demand_misses::total           449                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          304                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          145                       # number of overall misses
-system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10831500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2627000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     13458500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2772000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      2772000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     10831500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data      5399000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     16230500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     10831500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data      5399000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     16230500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.overall_misses::total          449                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10944000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2646000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13590000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2771500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2771500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     10944000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5417500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16361500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     10944000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5417500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16361500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          305                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           69                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::total          371                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          374                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          302                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          305                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.data          145                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          302                       # number of overall (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          450                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          305                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.data          145                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996689                       # miss rate for ReadReq accesses
+system.cpu.l2cache.overall_accesses::total          450                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996721                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_miss_rate::total     0.997305                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::total     0.997326                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996689                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996721                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
-system.cpu.l2cache.demand_miss_rate::total     0.997763                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
+system.cpu.l2cache.demand_miss_rate::total     0.997778                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996721                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
-system.cpu.l2cache.overall_miss_rate::total     0.997763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35985.049834                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38072.463768                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 36374.324324                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36473.684211                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36473.684211                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 36391.255605                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35985.049834                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37234.482759                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 36391.255605                       # average overall miss latency
+system.cpu.l2cache.overall_miss_rate::total     0.997778                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        36000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38347.826087                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 36434.316354                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 36467.105263                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 36467.105263                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        36000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37362.068966                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 36439.866370                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        36000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37362.068966                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 36439.866370                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -562,50 +562,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          304                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           69                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total          370                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          373                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          304                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.data          145                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          449                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          304                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data          145                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9877000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2416500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12293500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.overall_mshr_misses::total          449                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9981000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2435500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12416500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2541500                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2541500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9877000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4958000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     14835000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9877000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4958000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     14835000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9981000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4977000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14958000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9981000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4977000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14958000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996721                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997305                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997326                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996721                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997763                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total     0.997778                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996721                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35021.739130                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33225.675676                       # average ReadReq mshr miss latency
+system.cpu.l2cache.overall_mshr_miss_rate::total     0.997778                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32832.236842                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35297.101449                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33288.203753                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33440.789474                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33440.789474                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32813.953488                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34193.103448                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33262.331839                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32832.236842                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34324.137931                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33314.031180                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32832.236842                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34324.137931                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33314.031180                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3367142fe4e434d3a10767a860ab5702f1847750..1c047bcde2681754e0ea25075c8351a9dd0faf35 100644 (file)
@@ -120,8 +120,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+width=8
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
 
 [system.physmem]
index 85d4b3244a78d23398436b6905c32938142ce63b..2878f37c1cafe4bcfe27870935704c100c16a663 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 13:44:28
-gem5 started Jun  4 2012 15:04:09
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:22:41
 gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 5651000 because target called exit()
+Exiting @ tick 5614000 because target called exit()
index 97160757402505b29ed200520c7866f85ecd1dc3..288f81674a46a1bd84c9c876fe801ac6ef0369b9 100644 (file)
@@ -1,59 +1,59 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000006                       # Number of seconds simulated
-sim_ticks                                     5651000                       # Number of ticks simulated
-final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     5614000                       # Number of ticks simulated
+final_tick                                    5614000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 420667                       # Simulator instruction rate (inst/s)
-host_op_rate                                   760787                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              437668419                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214072                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
-sim_insts                                        5417                       # Number of instructions simulated
-sim_ops                                          9810                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             55280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              7068                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62348                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        55280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           55280                       # Number of instructions bytes read from this memory
+host_inst_rate                                  93021                       # Simulator instruction rate (inst/s)
+host_op_rate                                   168430                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               96993365                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222752                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+sim_insts                                        5381                       # Number of instructions simulated
+sim_ops                                          9746                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             54912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                61976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        54912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           54912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           7110                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              7110                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1056                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7966                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6864                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7916                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               934                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  934                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst           9782339409                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1250752079                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total             11033091488                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      9782339409                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         9782339409                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1258184392                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1258184392                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          9782339409                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2508936471                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            12291275880                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           9781261133                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1258282864                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total             11039543997                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      9781261133                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         9781261133                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1266476665                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1266476665                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          9781261133                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2524759530                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            12306020663                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            11303                       # number of cpu cycles simulated
+system.cpu.numCycles                            11229                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5417                       # Number of instructions committed
-system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.committedInsts                        5381                       # Number of instructions committed
+system.cpu.committedOps                          9746                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  9651                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         9651                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29744                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14595                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1986                       # number of memory refs
+system.cpu.num_load_insts                        1052                       # Number of load instructions
 system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      11303                       # Number of busy cycles
+system.cpu.num_busy_cycles                      11229                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 59420f599af142060da0ec6c79324af3976a1708..2a819a3dd0b8735a547cb9132c690258faf27c1a 100644 (file)
@@ -99,7 +99,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index 64f5cd1a7f090c371bdcc32a2b171dfc216a664e..f0077f0d525a8697c9e13cb306606ff7678e8ca0 100755 (executable)
@@ -1,9 +1,9 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul 10 2012 17:58:36
-gem5 started Jul 10 2012 17:59:21
-gem5 executing on sc2b0605
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:23:02
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index e50c5939b59e1df3b19f4a7fd3d3d560808cee84..c455548e3aebedfcb5213601ff8e7b89f4397b5b 100644 (file)
@@ -4,35 +4,35 @@ sim_seconds                                  0.000276                       # Nu
 sim_ticks                                      276484                       # Number of ticks simulated
 final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  37105                       # Simulator instruction rate (inst/s)
-host_op_rate                                    67187                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                1893389                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 244968                       # Number of bytes of host memory used
-host_seconds                                     0.15                       # Real time elapsed on the host
-sim_insts                                        5417                       # Number of instructions simulated
-sim_ops                                          9810                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             55280                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data              7068                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                62348                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        55280                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           55280                       # Number of instructions bytes read from this memory
+host_inst_rate                                  51763                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93738                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2658830                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 243356                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
+sim_insts                                        5381                       # Number of instructions simulated
+sim_ops                                          9746                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             54912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data              7064                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                61976                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        54912                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           54912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           7110                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              7110                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst               6910                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               1056                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                  7966                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst               6864                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               1052                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                  7916                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data               934                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                  934                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst            199939237                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             25563866                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               225503103                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       199939237                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          199939237                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            198608238                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             25549399                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               224157637                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       198608238                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          198608238                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu.data            25715774                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               25715774                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           199939237                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            51279640                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              251218877                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           198608238                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            51265173                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              249873410                       # Total bandwidth to/from this memory (bytes/s)
 system.l1_cntrl0.cacheMemory.num_data_array_reads            0                       # number of data array reads
 system.l1_cntrl0.cacheMemory.num_data_array_writes            0                       # number of data array writes
 system.l1_cntrl0.cacheMemory.num_tag_array_reads            0                       # number of tag array reads
@@ -43,20 +43,20 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5417                       # Number of instructions committed
-system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.committedInsts                        5381                       # Number of instructions committed
+system.cpu.committedOps                          9746                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  9651                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         9651                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29744                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14595                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1986                       # number of memory refs
+system.cpu.num_load_insts                        1052                       # Number of load instructions
 system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
 system.cpu.num_busy_cycles                     276484                       # Number of busy cycles
index 75df56c4d6d0aa3fbd6569db45504dabd7b79433..3f04b065a6c892fd06b7ce94cc5931205e3dc12f 100644 (file)
@@ -202,7 +202,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0] system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
 slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
 
 [system.physmem]
index c1b9925b1f7fbffc7a19d162c83ac343ff7615d3..4ca1a9d261038220567dc316637574f05c777338 100755 (executable)
@@ -1,11 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:58:39
-gem5 started Jul  2 2012 12:38:59
+gem5 compiled Aug 13 2012 17:08:22
+gem5 started Aug 13 2012 18:22:51
 gem5 executing on zizzer
-command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing
+command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 29726000 because target called exit()
+Exiting @ tick 29676000 because target called exit()
index 4b1ad61d2e243ce2de2c70860784620174aa3857..c890207463ecbb94bd88858049551fa87f9eb86c 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000030                       # Number of seconds simulated
-sim_ticks                                    29726000                       # Number of ticks simulated
-final_tick                                   29726000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    29676000                       # Number of ticks simulated
+final_tick                                   29676000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107097                       # Simulator instruction rate (inst/s)
-host_op_rate                                   193883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              587308683                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226300                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
-sim_insts                                        5417                       # Number of instructions simulated
-sim_ops                                          9810                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 192246                       # Simulator instruction rate (inst/s)
+host_op_rate                                   347982                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1058982197                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231200                       # Number of bytes of host memory used
+host_seconds                                     0.03                       # Real time elapsed on the host
+sim_insts                                        5381                       # Number of instructions simulated
+sim_ops                                          9746                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             14528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8576                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                23104                       # Number of bytes read from this memory
@@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total           14528                       # Nu
 system.physmem.num_reads::cpu.inst                227                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                134                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   361                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            488730404                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            288501648                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               777232053                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       488730404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          488730404                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           488730404                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           288501648                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              777232053                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            489553848                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            288987734                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               778541582                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       489553848                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          489553848                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           489553848                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           288987734                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              778541582                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
-system.cpu.numCycles                            59452                       # number of cpu cycles simulated
+system.cpu.numCycles                            59352                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                        5417                       # Number of instructions committed
-system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
+system.cpu.committedInsts                        5381                       # Number of instructions committed
+system.cpu.committedOps                          9746                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                  9651                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts          904                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                         9715                       # number of integer instructions
+system.cpu.num_conditional_control_insts          899                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                         9651                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29934                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              14707                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29744                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              14595                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          1990                       # number of memory refs
-system.cpu.num_load_insts                        1056                       # Number of load instructions
+system.cpu.num_mem_refs                          1986                       # number of memory refs
+system.cpu.num_load_insts                        1052                       # Number of load instructions
 system.cpu.num_store_insts                        934                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      59452                       # Number of busy cycles
+system.cpu.num_busy_cycles                      59352                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                105.590396                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     6683                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                105.746399                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     6637                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  29.311404                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  29.109649                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     105.590396                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.051558                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.051558                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         6683                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            6683                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          6683                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             6683                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         6683                       # number of overall hits
-system.cpu.icache.overall_hits::total            6683                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     105.746399                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.051634                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.051634                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         6637                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6637                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6637                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6637                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6637                       # number of overall hits
+system.cpu.icache.overall_hits::total            6637                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          228                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           228                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          228                       # number of demand (read+write) misses
@@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     12726000
 system.cpu.icache.demand_miss_latency::total     12726000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     12726000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     12726000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         6911                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         6911                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         6911                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         6911                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         6911                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         6911                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.032991                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.032991                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.032991                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.032991                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.032991                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.032991                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst         6865                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6865                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6865                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6865                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6865                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6865                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.033212                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.033212                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.033212                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.033212                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.033212                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.033212                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total 55815.789474                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
@@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12042000
 system.cpu.icache.demand_mshr_miss_latency::total     12042000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12042000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12042000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.032991                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.032991                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.032991                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.033212                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.033212                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.033212                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.033212                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
@@ -129,22 +129,22 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474
 system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 80.767478                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     1856                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 80.866493                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     1852                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.850746                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.820896                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      80.767478                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.019719                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.019719                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         1001                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            1001                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      80.866493                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.019743                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.019743                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          997                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             997                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data          855                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total            855                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          1856                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             1856                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         1856                       # number of overall hits
-system.cpu.dcache.overall_hits::total            1856                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          1852                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1852                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1852                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1852                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           79                       # number of WriteReq misses
@@ -161,22 +161,22 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7504000
 system.cpu.dcache.demand_miss_latency::total      7504000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7504000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7504000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         1056                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         1056                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         1052                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1052                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         1990                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         1990                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         1990                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         1990                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052083                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.052083                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         1986                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1986                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1986                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1986                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052281                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.052281                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084582                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.084582                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.067337                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.067337                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.067337                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.067337                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.067472                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.067472                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.067472                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.067472                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -209,14 +209,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7102000
 system.cpu.dcache.demand_mshr_miss_latency::total      7102000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7102000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7102000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052083                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052083                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052281                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052281                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084582                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084582                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.067337                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.067337                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067472                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.067472                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067472                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.067472                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -227,16 +227,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               134.079161                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               134.266314                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       1                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    105.593760                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     28.485401                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.003222                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.000869                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.004092                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    105.749768                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.516546                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003227                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000870                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004097                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
index 856b4f64ddc8bf434593bab8ea91ada8d9a665dc..c8fd946394ef7a9daeaa4f45d5f08aa2be14fc91 100644 (file)
@@ -531,7 +531,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 94c9ff95a68acf213df6f10b101f83a64be4c883..b2c42f9a90636d65238373a055279ba55ca4f35a 100755 (executable)
@@ -1,14 +1,14 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:30:56
-gem5 started Jul  2 2012 09:08:40
+gem5 compiled Aug 13 2012 16:51:51
+gem5 started Aug 13 2012 17:17:24
 gem5 executing on zizzer
-command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 15041500 because target called exit()
+Exiting @ tick 14993500 because target called exit()
index a5109fa39c461df81ade3db218cd235b451a572e..412d761af697bbe12d469d7fb0bab9a97fcc254d 100644 (file)
@@ -1,52 +1,52 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000015                       # Number of seconds simulated
-sim_ticks                                    15041500                       # Number of ticks simulated
-final_tick                                   15041500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    14993500                       # Number of ticks simulated
+final_tick                                   14993500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102152                       # Simulator instruction rate (inst/s)
-host_op_rate                                   102138                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              120262580                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219804                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
-sim_insts                                       12773                       # Number of instructions simulated
-sim_ops                                         12773                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             39936                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             22400                       # Number of bytes read from this memory
+host_inst_rate                                  32330                       # Simulator instruction rate (inst/s)
+host_op_rate                                    32329                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               38030689                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224252                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
+sim_insts                                       12745                       # Number of instructions simulated
+sim_ops                                         12745                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             39872                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             22464                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                62336                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        39936                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           39936                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst                624                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data                350                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu.inst        39872                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           39872                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu.inst                623                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data                351                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   974                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           2655054350                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1489213177                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              4144267527                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      2655054350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         2655054350                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          2655054350                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          1489213177                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             4144267527                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           2659285690                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1498249241                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              4157534932                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      2659285690                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         2659285690                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          2659285690                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          1498249241                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             4157534932                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
 system.cpu.dtb.fetch_accesses                       0                       # ITB accesses
-system.cpu.dtb.read_hits                         4063                       # DTB read hits
-system.cpu.dtb.read_misses                         99                       # DTB read misses
+system.cpu.dtb.read_hits                         4043                       # DTB read hits
+system.cpu.dtb.read_misses                        104                       # DTB read misses
 system.cpu.dtb.read_acv                             0                       # DTB read access violations
-system.cpu.dtb.read_accesses                     4162                       # DTB read accesses
-system.cpu.dtb.write_hits                        2079                       # DTB write hits
-system.cpu.dtb.write_misses                        66                       # DTB write misses
+system.cpu.dtb.read_accesses                     4147                       # DTB read accesses
+system.cpu.dtb.write_hits                        2093                       # DTB write hits
+system.cpu.dtb.write_misses                        65                       # DTB write misses
 system.cpu.dtb.write_acv                            0                       # DTB write access violations
-system.cpu.dtb.write_accesses                    2145                       # DTB write accesses
-system.cpu.dtb.data_hits                         6142                       # DTB hits
-system.cpu.dtb.data_misses                        165                       # DTB misses
+system.cpu.dtb.write_accesses                    2158                       # DTB write accesses
+system.cpu.dtb.data_hits                         6136                       # DTB hits
+system.cpu.dtb.data_misses                        169                       # DTB misses
 system.cpu.dtb.data_acv                             0                       # DTB access violations
-system.cpu.dtb.data_accesses                     6307                       # DTB accesses
-system.cpu.itb.fetch_hits                        4998                       # ITB hits
-system.cpu.itb.fetch_misses                        64                       # ITB misses
+system.cpu.dtb.data_accesses                     6305                       # DTB accesses
+system.cpu.itb.fetch_hits                        5063                       # ITB hits
+system.cpu.itb.fetch_misses                        68                       # ITB misses
 system.cpu.itb.fetch_acv                            0                       # ITB acv
-system.cpu.itb.fetch_accesses                    5062                       # ITB accesses
+system.cpu.itb.fetch_accesses                    5131                       # ITB accesses
 system.cpu.itb.read_hits                            0                       # DTB read hits
 system.cpu.itb.read_misses                          0                       # DTB read misses
 system.cpu.itb.read_acv                             0                       # DTB read access violations
@@ -61,412 +61,411 @@ system.cpu.itb.data_acv                             0                       # DT
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload0.num_syscalls                  17                       # Number of system calls
 system.cpu.workload1.num_syscalls                  17                       # Number of system calls
-system.cpu.numCycles                            30084                       # number of cpu cycles simulated
+system.cpu.numCycles                            29988                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     6210                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               3535                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect               1700                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  4700                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                      759                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     6234                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               3551                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect               1730                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  4726                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                      792                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.usedRAS                      825                       # Number of times the RAS was used to get a target.
-system.cpu.BPredUnit.RASInCorrect                 175                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles               1535                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          34626                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6210                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               1584                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          5789                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    1776                       # Number of cycles fetch has spent squashing
+system.cpu.BPredUnit.usedRAS                      829                       # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.RASInCorrect                 185                       # Number of incorrect RAS predictions.
+system.cpu.fetch.icacheStallCycles               1565                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          34888                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6234                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               1621                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          5843                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    1806                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.MiscStallCycles                   48                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines                      4998                       # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes                   745                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              24259                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.427347                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.816880                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.CacheLines                      5063                       # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes                   763                       # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples              24485                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.424872                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.811431                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    18470     76.14%     76.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                      464      1.91%     78.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      348      1.43%     79.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      447      1.84%     81.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      403      1.66%     82.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      343      1.41%     84.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      469      1.93%     86.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      536      2.21%     88.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     2779     11.46%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    18642     76.14%     76.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                      463      1.89%     78.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      348      1.42%     79.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      451      1.84%     81.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      433      1.77%     83.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      338      1.38%     84.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      497      2.03%     86.47% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      532      2.17%     88.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     2781     11.36%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                24259                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.206422                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        1.150977                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    34703                       # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles                  5701                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      4994                       # Number of cycles decode is running
-system.cpu.decode.UnblockCycles                   517                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   2387                       # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved                  655                       # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred                   440                       # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts                  30483                       # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts                   727                       # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles                   2387                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    35405                       # Number of cycles rename is idle
-system.cpu.rename.BlockCycles                    2859                       # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles            908                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      4714                       # Number of cycles rename is running
+system.cpu.fetch.rateDist::total                24485                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.207883                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        1.163399                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    35160                       # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles                  5629                       # Number of cycles decode is blocked
+system.cpu.decode.RunCycles                      5043                       # Number of cycles decode is running
+system.cpu.decode.UnblockCycles                   481                       # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles                   2441                       # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved                  657                       # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred                   429                       # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts                  30497                       # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts                   762                       # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles                   2441                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    35832                       # Number of cycles rename is idle
+system.cpu.rename.BlockCycles                    2821                       # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles            862                       # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles                      4769                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                  2029                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  28166                       # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents                    11                       # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents                      1                       # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents                  2057                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               21169                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 35183                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            35149                       # Number of integer rename lookups
+system.cpu.rename.RenamedInsts                  28347                       # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents                     5                       # Number of times rename has blocked due to ROB full
+system.cpu.rename.LSQFullEvents                  2069                       # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RenamedOperands               21319                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 35425                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            35391                       # Number of integer rename lookups
 system.cpu.rename.fp_rename_lookups                34                       # Number of floating rename lookups
-system.cpu.rename.CommittedMaps                  9166                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    12003                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.CommittedMaps                  9140                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                    12179                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                 54                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts             42                       # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts                      5549                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 2568                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                1287                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads                11                       # Number of conflicting loads.
+system.cpu.rename.skidInsts                      5554                       # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads                 2631                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                1322                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads                13                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads                 2598                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores                1301                       # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads                17                       # Number of conflicting loads.
+system.cpu.memDep1.insertedLoads                 2538                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores                1270                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads                13                       # Number of conflicting loads.
 system.cpu.memDep1.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      25020                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      25174                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                  51                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21261                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               104                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined           11085                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         6273                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     21355                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued                82                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined           11204                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         6343                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved             17                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         24259                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.876417                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.449361                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         24485                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.872167                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.446196                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               15324     63.17%     63.17% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3188     13.14%     76.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2404      9.91%     86.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1484      6.12%     92.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 963      3.97%     96.31% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 553      2.28%     98.59% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 233      0.96%     99.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  82      0.34%     99.88% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8                  28      0.12%    100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               15521     63.39%     63.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3217     13.14%     76.53% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2370      9.68%     86.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1453      5.93%     92.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                1034      4.22%     96.37% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 556      2.27%     98.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 237      0.97%     99.60% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  75      0.31%     99.91% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8                  22      0.09%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           24259                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           24485                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                       5      2.69%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      2.69% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                    116     62.37%     65.05% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                    65     34.95%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      11      6.18%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%      6.18% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                    104     58.43%     64.61% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                    63     35.39%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                  7259     68.24%     68.26% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    1      0.01%     68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     68.27% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     68.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 2247     21.12%     89.41% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                1126     10.59%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                  7361     67.94%     67.96% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    1      0.01%     67.97% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     67.97% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   2      0.02%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     67.99% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 2308     21.30%     89.29% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                1160     10.71%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  10637                       # Type of FU issued
+system.cpu.iq.FU_type_0::total                  10834                       # Type of FU issued
 system.cpu.iq.FU_type_1::No_OpClass                 2      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu                  7177     67.55%     67.57% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult                    1      0.01%     67.58% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     67.58% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     67.60% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead                 2282     21.48%     89.08% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite                1160     10.92%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_1::IntAlu                  7172     68.17%     68.19% # Type of FU issued
+system.cpu.iq.FU_type_1::IntMult                    1      0.01%     68.20% # Type of FU issued
+system.cpu.iq.FU_type_1::IntDiv                     0      0.00%     68.20% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatAdd                   2      0.02%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCmp                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatCvt                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatMult                  0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatDiv                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::FloatSqrt                  0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAdd                    0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAddAcc                 0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdAlu                    0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCmp                    0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdCvt                    0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMisc                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMult                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdMultAcc                0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShift                  0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdShiftAcc               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdSqrt                   0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAdd               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatAlu               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCmp               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatCvt               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatDiv               0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMisc              0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMult              0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatMultAcc            0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::SimdFloatSqrt              0      0.00%     68.22% # Type of FU issued
+system.cpu.iq.FU_type_1::MemRead                 2223     21.13%     89.35% # Type of FU issued
+system.cpu.iq.FU_type_1::MemWrite                1121     10.65%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_1::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total                  10624                       # Type of FU issued
+system.cpu.iq.FU_type_1::total                  10521                       # Type of FU issued
 system.cpu.iq.FU_type::No_OpClass                   4      0.02%      0.02% # Type of FU issued
-system.cpu.iq.FU_type::IntAlu                   14436     67.90%     67.92% # Type of FU issued
-system.cpu.iq.FU_type::IntMult                      2      0.01%     67.93% # Type of FU issued
-system.cpu.iq.FU_type::IntDiv                       0      0.00%     67.93% # Type of FU issued
-system.cpu.iq.FU_type::FloatAdd                     4      0.02%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::FloatCmp                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::FloatCvt                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::FloatMult                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::FloatDiv                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdAdd                      0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdAlu                      0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdCmp                      0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdCvt                      0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdMisc                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdMult                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdShift                    0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     67.95% # Type of FU issued
-system.cpu.iq.FU_type::MemRead                   4529     21.30%     89.25% # Type of FU issued
-system.cpu.iq.FU_type::MemWrite                  2286     10.75%    100.00% # Type of FU issued
+system.cpu.iq.FU_type::IntAlu                   14533     68.05%     68.07% # Type of FU issued
+system.cpu.iq.FU_type::IntMult                      2      0.01%     68.08% # Type of FU issued
+system.cpu.iq.FU_type::IntDiv                       0      0.00%     68.08% # Type of FU issued
+system.cpu.iq.FU_type::FloatAdd                     4      0.02%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::FloatCmp                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::FloatCvt                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::FloatMult                    0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::FloatDiv                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::FloatSqrt                    0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdAdd                      0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdAddAcc                   0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdAlu                      0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdCmp                      0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdCvt                      0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdMisc                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdMult                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdMultAcc                  0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdShift                    0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdShiftAcc                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdSqrt                     0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAdd                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatAlu                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCmp                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatCvt                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatDiv                 0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMisc                0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMult                0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatMultAcc             0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::SimdFloatSqrt                0      0.00%     68.10% # Type of FU issued
+system.cpu.iq.FU_type::MemRead                   4531     21.22%     89.32% # Type of FU issued
+system.cpu.iq.FU_type::MemWrite                  2281     10.68%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::IprAccess                    0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type::InstPrefetch                 0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type::total                    21261                       # Type of FU issued
-system.cpu.iq.rate                           0.706721                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0                       86                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1                      100                       # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total                  186                       # FU busy when requested
-system.cpu.iq.fu_busy_rate::0                0.004045                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1                0.004703                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total            0.008748                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              67029                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             36163                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19051                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type::total                    21355                       # Type of FU issued
+system.cpu.iq.rate                           0.712118                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt::0                       95                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::1                       83                       # FU busy when requested
+system.cpu.iq.fu_busy_cnt::total                  178                       # FU busy when requested
+system.cpu.iq.fu_busy_rate::0                0.004449                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::1                0.003887                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.fu_busy_rate::total            0.008335                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              67413                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             36435                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19171                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                  42                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                 20                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses           20                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21421                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21507                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                      22                       # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads               47                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads               59                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1383                       # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation           14                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores          422                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1448                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses            9                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation           15                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores          457                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads               65                       # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread1.forwLoads               64                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread1.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads         1413                       # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation           16                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores          436                       # Number of stores squashed
+system.cpu.iew.lsq.thread1.squashedLoads         1355                       # Number of loads squashed
+system.cpu.iew.lsq.thread1.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread1.memOrderViolation           14                       # Number of memory ordering violations
+system.cpu.iew.lsq.thread1.squashedStores          405                       # Number of stores squashed
 system.cpu.iew.lsq.thread1.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread1.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread1.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread1.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   2387                       # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles                     608                       # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles                    48                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               25214                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               623                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  5166                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2588                       # Number of dispatched store instructions
+system.cpu.iew.iewSquashCycles                   2441                       # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles                     573                       # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles                    39                       # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts               25387                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               653                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  5169                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2592                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                 51                       # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents                     40                       # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents                     1                       # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents             30                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            252                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect         1229                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1481                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 19905                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0               2053                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1               2121                       # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total           4174                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1356                       # Number of squashed instructions skipped in execute
+system.cpu.iew.iewIQFullEvents                     24                       # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents                    10                       # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents             29                       # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect            262                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect         1220                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1482                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20001                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts::0               2104                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::1               2055                       # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts::total           4159                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1354                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp::0                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::1                          0                       # number of swp insts executed
 system.cpu.iew.exec_swp::total                      0                       # number of swp insts executed
-system.cpu.iew.exec_nop::0                         70                       # number of nop insts executed
-system.cpu.iew.exec_nop::1                         73                       # number of nop insts executed
-system.cpu.iew.exec_nop::total                    143                       # number of nop insts executed
-system.cpu.iew.exec_refs::0                      3144                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::1                      3199                       # number of memory reference insts executed
-system.cpu.iew.exec_refs::total                  6343                       # number of memory reference insts executed
-system.cpu.iew.exec_branches::0                  1633                       # Number of branches executed
-system.cpu.iew.exec_branches::1                  1644                       # Number of branches executed
-system.cpu.iew.exec_branches::total              3277                       # Number of branches executed
-system.cpu.iew.exec_stores::0                    1091                       # Number of stores executed
-system.cpu.iew.exec_stores::1                    1078                       # Number of stores executed
-system.cpu.iew.exec_stores::total                2169                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.661647                       # Inst execution rate
-system.cpu.iew.wb_sent::0                        9696                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1                        9663                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total                   19359                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0                       9565                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::1                       9506                       # cumulative count of insts written-back
-system.cpu.iew.wb_count::total                  19071                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0                   4909                       # num instructions producing a value
-system.cpu.iew.wb_producers::1                   4894                       # num instructions producing a value
-system.cpu.iew.wb_producers::total               9803                       # num instructions producing a value
-system.cpu.iew.wb_consumers::0                   6387                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::1                   6353                       # num instructions consuming a value
-system.cpu.iew.wb_consumers::total              12740                       # num instructions consuming a value
+system.cpu.iew.exec_nop::0                         84                       # number of nop insts executed
+system.cpu.iew.exec_nop::1                         78                       # number of nop insts executed
+system.cpu.iew.exec_nop::total                    162                       # number of nop insts executed
+system.cpu.iew.exec_refs::0                      3212                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::1                      3127                       # number of memory reference insts executed
+system.cpu.iew.exec_refs::total                  6339                       # number of memory reference insts executed
+system.cpu.iew.exec_branches::0                  1650                       # Number of branches executed
+system.cpu.iew.exec_branches::1                  1625                       # Number of branches executed
+system.cpu.iew.exec_branches::total              3275                       # Number of branches executed
+system.cpu.iew.exec_stores::0                    1108                       # Number of stores executed
+system.cpu.iew.exec_stores::1                    1072                       # Number of stores executed
+system.cpu.iew.exec_stores::total                2180                       # Number of stores executed
+system.cpu.iew.exec_rate                     0.666967                       # Inst execution rate
+system.cpu.iew.wb_sent::0                        9882                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::1                        9596                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent::total                   19478                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count::0                       9755                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::1                       9436                       # cumulative count of insts written-back
+system.cpu.iew.wb_count::total                  19191                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers::0                   5007                       # num instructions producing a value
+system.cpu.iew.wb_producers::1                   4861                       # num instructions producing a value
+system.cpu.iew.wb_producers::total               9868                       # num instructions producing a value
+system.cpu.iew.wb_consumers::0                   6484                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::1                   6279                       # num instructions consuming a value
+system.cpu.iew.wb_consumers::total              12763                       # num instructions consuming a value
 system.cpu.iew.wb_penalized::0                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::1                      0                       # number of instrctions required to write to 'other' IQ
 system.cpu.iew.wb_penalized::total                  0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate::0                    0.317943                       # insts written-back per cycle
-system.cpu.iew.wb_rate::1                    0.315982                       # insts written-back per cycle
-system.cpu.iew.wb_rate::total                0.633925                       # insts written-back per cycle
-system.cpu.iew.wb_fanout::0                  0.768592                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::1                  0.770345                       # average fanout of values written-back
-system.cpu.iew.wb_fanout::total              0.769466                       # average fanout of values written-back
+system.cpu.iew.wb_rate::0                    0.325297                       # insts written-back per cycle
+system.cpu.iew.wb_rate::1                    0.314659                       # insts written-back per cycle
+system.cpu.iew.wb_rate::total                0.639956                       # insts written-back per cycle
+system.cpu.iew.wb_fanout::0                  0.772209                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::1                  0.774168                       # average fanout of values written-back
+system.cpu.iew.wb_fanout::total              0.773172                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate::0                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts          12807                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps            12807                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts           12383                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts          12779                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps            12779                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts           12568                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1285                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        24193                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.529368                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.313270                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1309                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        24431                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.523065                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.302863                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        18560     76.72%     76.72% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         2866     11.85%     88.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1184      4.89%     93.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          489      2.02%     95.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          363      1.50%     96.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          239      0.99%     97.97% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6          192      0.79%     98.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7           93      0.38%     99.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8          207      0.86%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        18816     77.02%     77.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         2827     11.57%     88.59% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1198      4.90%     93.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          508      2.08%     95.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          350      1.43%     97.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          244      1.00%     98.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6          205      0.84%     98.84% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7           82      0.34%     99.18% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8          201      0.82%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        24193                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts::0              6403                       # Number of instructions committed
-system.cpu.commit.committedInsts::1              6404                       # Number of instructions committed
-system.cpu.commit.committedInsts::total         12807                       # Number of instructions committed
-system.cpu.commit.committedOps::0                6403                       # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1                6404                       # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::total           12807                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        24431                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts::0              6389                       # Number of instructions committed
+system.cpu.commit.committedInsts::1              6390                       # Number of instructions committed
+system.cpu.commit.committedInsts::total         12779                       # Number of instructions committed
+system.cpu.commit.committedOps::0                6389                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1                6390                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::total           12779                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
-system.cpu.commit.refs::0                        2050                       # Number of memory references committed
-system.cpu.commit.refs::1                        2050                       # Number of memory references committed
-system.cpu.commit.refs::total                    4100                       # Number of memory references committed
-system.cpu.commit.loads::0                       1185                       # Number of loads committed
-system.cpu.commit.loads::1                       1185                       # Number of loads committed
-system.cpu.commit.loads::total                   2370                       # Number of loads committed
+system.cpu.commit.refs::0                        2048                       # Number of memory references committed
+system.cpu.commit.refs::1                        2048                       # Number of memory references committed
+system.cpu.commit.refs::total                    4096                       # Number of memory references committed
+system.cpu.commit.loads::0                       1183                       # Number of loads committed
+system.cpu.commit.loads::1                       1183                       # Number of loads committed
+system.cpu.commit.loads::total                   2366                       # Number of loads committed
 system.cpu.commit.membars::0                        0                       # Number of memory barriers committed
 system.cpu.commit.membars::1                        0                       # Number of memory barriers committed
 system.cpu.commit.membars::total                    0                       # Number of memory barriers committed
-system.cpu.commit.branches::0                    1051                       # Number of branches committed
-system.cpu.commit.branches::1                    1051                       # Number of branches committed
-system.cpu.commit.branches::total                2102                       # Number of branches committed
+system.cpu.commit.branches::0                    1050                       # Number of branches committed
+system.cpu.commit.branches::1                    1050                       # Number of branches committed
+system.cpu.commit.branches::total                2100                       # Number of branches committed
 system.cpu.commit.fp_insts::0                      10                       # Number of committed floating point instructions.
 system.cpu.commit.fp_insts::1                      10                       # Number of committed floating point instructions.
 system.cpu.commit.fp_insts::total                  20                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts::0                   6321                       # Number of committed integer instructions.
-system.cpu.commit.int_insts::1                   6321                       # Number of committed integer instructions.
-system.cpu.commit.int_insts::total              12642                       # Number of committed integer instructions.
+system.cpu.commit.int_insts::0                   6307                       # Number of committed integer instructions.
+system.cpu.commit.int_insts::1                   6307                       # Number of committed integer instructions.
+system.cpu.commit.int_insts::total              12614                       # Number of committed integer instructions.
 system.cpu.commit.function_calls::0               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::1               127                       # Number of function calls committed.
 system.cpu.commit.function_calls::total           254                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                   207                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                   201                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited::0                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::1                     0                       # number of insts not committed due to BW limits
 system.cpu.commit.bw_limited::total                 0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                       116646                       # The number of ROB reads
-system.cpu.rob.rob_writes                       52783                       # The number of ROB writes
-system.cpu.timesIdled                             298                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            5825                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0                     6386                       # Number of Instructions Simulated
-system.cpu.committedInsts::1                     6387                       # Number of Instructions Simulated
-system.cpu.committedOps::0                       6386                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1                       6387                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                 12773                       # Number of Instructions Simulated
-system.cpu.cpi::0                            4.710930                       # CPI: Cycles Per Instruction
-system.cpu.cpi::1                            4.710193                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.355281                       # CPI: Total CPI of All Threads
-system.cpu.ipc::0                            0.212272                       # IPC: Instructions Per Cycle
-system.cpu.ipc::1                            0.212306                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.424578                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    25165                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   14392                       # number of integer regfile writes
+system.cpu.rob.rob_reads                       117663                       # The number of ROB reads
+system.cpu.rob.rob_writes                       53150                       # The number of ROB writes
+system.cpu.timesIdled                             296                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                            5503                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts::0                     6372                       # Number of Instructions Simulated
+system.cpu.committedInsts::1                     6373                       # Number of Instructions Simulated
+system.cpu.committedOps::0                       6372                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1                       6373                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                 12745                       # Number of Instructions Simulated
+system.cpu.cpi::0                            4.706215                       # CPI: Cycles Per Instruction
+system.cpu.cpi::1                            4.705476                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.352923                       # CPI: Total CPI of All Threads
+system.cpu.ipc::0                            0.212485                       # IPC: Instructions Per Cycle
+system.cpu.ipc::1                            0.212518                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.425003                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    25299                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   14501                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
 system.cpu.fp_regfile_writes                        4                       # number of floating regfile writes
 system.cpu.misc_regfile_reads                       2                       # number of misc regfile reads
@@ -474,50 +473,50 @@ system.cpu.misc_regfile_writes                      2                       # nu
 system.cpu.icache.replacements::0                   6                       # number of replacements
 system.cpu.icache.replacements::1                   0                       # number of replacements
 system.cpu.icache.replacements::total               6                       # number of replacements
-system.cpu.icache.tagsinuse                315.592215                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     4122                       # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs                    626                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   6.584665                       # Average number of references to valid blocks.
+system.cpu.icache.tagsinuse                314.927989                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     4192                       # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs                    625                       # Sample count of references to valid blocks.
+system.cpu.icache.avg_refs                   6.707200                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     315.592215                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.154098                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.154098                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         4122                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            4122                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          4122                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             4122                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         4122                       # number of overall hits
-system.cpu.icache.overall_hits::total            4122                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          876                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           876                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          876                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            876                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          876                       # number of overall misses
-system.cpu.icache.overall_misses::total           876                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     34427000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     34427000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     34427000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     34427000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     34427000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     34427000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         4998                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         4998                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         4998                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         4998                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         4998                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         4998                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.175270                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.175270                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.175270                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.175270                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.175270                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.175270                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39300.228311                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39300.228311                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39300.228311                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39300.228311                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39300.228311                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39300.228311                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     314.927989                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.153773                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.153773                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         4192                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4192                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4192                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4192                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4192                       # number of overall hits
+system.cpu.icache.overall_hits::total            4192                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          871                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           871                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          871                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            871                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          871                       # number of overall misses
+system.cpu.icache.overall_misses::total           871                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34167000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34167000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34167000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34167000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34167000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34167000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5063                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5063                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5063                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5063                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5063                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5063                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.172032                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.172032                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.172032                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.172032                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.172032                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.172032                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39227.324914                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 39227.324914                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39227.324914                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 39227.324914                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39227.324914                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 39227.324914                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -526,96 +525,96 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          250                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          250                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          250                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          250                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          250                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          250                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst          626                       # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total          626                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst          626                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total          626                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst          626                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total          626                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25017500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     25017500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25017500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     25017500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25017500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     25017500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.125250                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.125250                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.125250                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.125250                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39964.057508                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39964.057508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39964.057508                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39964.057508                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          246                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          246                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          246                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          246                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          246                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          246                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          625                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          625                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          625                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          625                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          625                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          625                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24783500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24783500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24783500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24783500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24783500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24783500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.123445                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.123445                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.123445                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.123445                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.123445                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.123445                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39653.600000                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39653.600000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39653.600000                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 39653.600000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39653.600000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 39653.600000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements::0                   0                       # number of replacements
 system.cpu.dcache.replacements::1                   0                       # number of replacements
 system.cpu.dcache.replacements::total               0                       # number of replacements
-system.cpu.dcache.tagsinuse                216.324578                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     4646                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                215.917106                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     4606                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    350                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  13.274286                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  13.160000                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     216.324578                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.052814                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.052814                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         3634                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3634                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     215.917106                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.052714                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.052714                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         3594                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3594                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1012                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1012                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data          4646                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4646                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4646                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4646                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data          315                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total           315                       # number of ReadReq misses
+system.cpu.dcache.demand_hits::cpu.data          4606                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4606                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4606                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4606                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          324                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           324                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          718                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total          718                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data         1033                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total           1033                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data         1033                       # number of overall misses
-system.cpu.dcache.overall_misses::total          1033                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     14081500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     14081500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     28681000                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     28681000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data     42762500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total     42762500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data     42762500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total     42762500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3949                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3949                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.demand_misses::cpu.data         1042                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1042                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1042                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1042                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     14022500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     14022500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     28872500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     28872500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     42895000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     42895000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     42895000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     42895000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         3918                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3918                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         5679                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         5679                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         5679                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         5679                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.079767                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.079767                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         5648                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5648                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5648                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5648                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082695                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.082695                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.415029                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.415029                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.181898                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.181898                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.181898                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.181898                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44703.174603                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 44703.174603                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39945.682451                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 39945.682451                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 41396.418199                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 41396.418199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 41396.418199                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 41396.418199                       # average overall miss latency
+system.cpu.dcache.demand_miss_rate::cpu.data     0.184490                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.184490                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.184490                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.184490                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43279.320988                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 43279.320988                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40212.395543                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 40212.395543                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 41166.026871                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 41166.026871                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 41166.026871                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 41166.026871                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -624,173 +623,173 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data          111                       # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total          111                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          119                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          119                       # number of ReadReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::cpu.data          572                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          572                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data          683                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total          683                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data          683                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total          683                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total          204                       # number of ReadReq MSHR misses
+system.cpu.dcache.demand_mshr_hits::cpu.data          691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          691                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          691                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          691                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          205                       # number of ReadReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total          350                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9596500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total      9596500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6268000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total      6268000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15864500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total     15864500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15864500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total     15864500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.051659                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.051659                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      9453500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      9453500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      6369000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      6369000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     15822500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     15822500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     15822500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     15822500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052323                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.052323                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.061631                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.061631                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.061631                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.061631                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47041.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47041.666667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42931.506849                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42931.506849                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45327.142857                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 45327.142857                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45327.142857                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 45327.142857                       # average overall mshr miss latency
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.062146                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.062146                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.062146                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.062146                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46114.634146                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46114.634146                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43623.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43623.287671                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45078.347578                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 45078.347578                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45078.347578                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 45078.347578                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements::0                  0                       # number of replacements
 system.cpu.l2cache.replacements::1                  0                       # number of replacements
 system.cpu.l2cache.replacements::total              0                       # number of replacements
-system.cpu.l2cache.tagsinuse               437.003550                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               435.815079                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
-system.cpu.l2cache.sampled_refs                   828                       # Sample count of references to valid blocks.
-system.cpu.l2cache.avg_refs                  0.002415                       # Average number of references to valid blocks.
+system.cpu.l2cache.sampled_refs                   827                       # Sample count of references to valid blocks.
+system.cpu.l2cache.avg_refs                  0.002418                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    315.880086                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data    121.123464                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.009640                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::cpu.data     0.003696                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.013336                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    315.212279                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    120.602800                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.009620                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.003681                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.013300                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
 system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.inst          624                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data          204                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.inst          623                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          205                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::total          828                       # number of ReadReq misses
 system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
 system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.inst          624                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.data          350                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst          623                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          351                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total           974                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses::cpu.inst          624                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.data          350                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.inst          623                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          351                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          974                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24336000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.data      9337500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     33673500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6106000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total      6106000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     24336000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data     15443500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     39779500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     24336000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data     15443500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     39779500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses::cpu.inst          626                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.data          204                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24119500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      9201500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     33321000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      6205000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      6205000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24119500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     15406500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     39526000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24119500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     15406500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     39526000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          625                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          205                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          830                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses::cpu.inst          626                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.data          350                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.inst          625                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          351                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::total          976                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.inst          626                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_accesses::cpu.data          350                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          625                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          351                       # number of overall (read+write) accesses
 system.cpu.l2cache.overall_accesses::total          976                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996800                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_miss_rate::total     0.997590                       # miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_miss_rate::total            1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996800                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
 system.cpu.l2cache.demand_miss_rate::total     0.997951                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996800                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.997951                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        39000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45772.058824                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 40668.478261                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 41821.917808                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 41821.917808                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        39000                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 44124.285714                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 40841.375770                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        39000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 44124.285714                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 40841.375770                       # average overall miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 38715.088283                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 44885.365854                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 40242.753623                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        42500                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total        42500                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 38715.088283                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 43893.162393                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 40581.108830                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 38715.088283                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 43893.162393                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 40581.108830                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs                9                       # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs               10                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs  4166.666667                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs         3750                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          624                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          204                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          623                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          205                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          828                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst          624                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data          350                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          623                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          351                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          974                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst          624                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data          350                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          623                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          351                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          974                       # number of overall MSHR misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22375000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8716000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total     31091000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5649500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5649500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22375000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     14365500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total     36740500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22375000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     14365500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total     36740500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22168000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8579500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     30747500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      5752000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      5752000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22168000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     14331500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     36499500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22168000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     14331500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     36499500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997590                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.997951                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996800                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.997951                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42725.490196                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37549.516908                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38695.205479                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38695.205479                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41044.285714                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37721.252567                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35857.371795                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41044.285714                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37721.252567                       # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35582.664526                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41851.219512                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37134.661836                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39397.260274                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39397.260274                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35582.664526                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40830.484330                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37473.819302                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35582.664526                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40830.484330                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37473.819302                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 09d24317c5339d02593bd0d624869c6960fb06e5..122f72766dddaacbe49a82c487be0d8dbd675317 100644 (file)
@@ -214,7 +214,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 6fbf990e1f3a3f0a8ad5f50fe80f6358e8e17f73..e5fdf01a97b5c686e93611b32336f2e26d69edd4 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:30:48
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:17
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -18,4 +18,4 @@ LDTX:         Passed
 LDTW:          Passed
 STTW:          Passed
 Done
-Exiting @ tick 25615500 because target called exit()
+Exiting @ tick 25614500 because target called exit()
index c2589ee2d420ad7d5a7b5b5c29aba46738d1d35c..2b7ec11ceec0c37699649c96caac4e7e269f77d8 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000026                       # Number of seconds simulated
-sim_ticks                                    25615500                       # Number of ticks simulated
-final_tick                                   25615500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    25614500                       # Number of ticks simulated
+final_tick                                   25614500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  51797                       # Simulator instruction rate (inst/s)
-host_op_rate                                    51795                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               87424707                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219936                       # Number of bytes of host memory used
-host_seconds                                     0.29                       # Real time elapsed on the host
-sim_insts                                       15175                       # Number of instructions simulated
-sim_ops                                         15175                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  72825                       # Simulator instruction rate (inst/s)
+host_op_rate                                    72819                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              123010334                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229416                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
+sim_insts                                       15162                       # Number of instructions simulated
+sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             19072                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                27904                       # Number of bytes read from this memory
@@ -19,128 +19,128 @@ system.physmem.bytes_inst_read::total           19072                       # Nu
 system.physmem.num_reads::cpu.inst                298                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   436                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            744549199                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            344791240                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1089340438                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       744549199                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          744549199                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           744549199                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           344791240                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1089340438                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            744578266                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            344804700                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1089382967                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       744578266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          744578266                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           744578266                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           344804700                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1089382967                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            51232                       # number of cpu cycles simulated
+system.cpu.numCycles                            51230                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.branch_predictor.lookups              5014                       # Number of BP lookups
-system.cpu.branch_predictor.condPredicted         3353                       # Number of conditional branches predicted
-system.cpu.branch_predictor.condIncorrect         2379                       # Number of conditional branches incorrect
-system.cpu.branch_predictor.BTBLookups           3331                       # Number of BTB lookups
-system.cpu.branch_predictor.BTBHits              2040                       # Number of BTB hits
-system.cpu.branch_predictor.usedRAS               174                       # Number of times the RAS was used to get a target.
+system.cpu.branch_predictor.lookups              5020                       # Number of BP lookups
+system.cpu.branch_predictor.condPredicted         3412                       # Number of conditional branches predicted
+system.cpu.branch_predictor.condIncorrect         2378                       # Number of conditional branches incorrect
+system.cpu.branch_predictor.BTBLookups           3517                       # Number of BTB lookups
+system.cpu.branch_predictor.BTBHits              2141                       # Number of BTB hits
+system.cpu.branch_predictor.usedRAS               176                       # Number of times the RAS was used to get a target.
 system.cpu.branch_predictor.RASInCorrect            5                       # Number of incorrect RAS predictions.
-system.cpu.branch_predictor.BTBHitPct       61.242870                       # BTB Hit Percentage
-system.cpu.branch_predictor.predictedTaken         2214                       # Number of Branches Predicted As Taken (True).
-system.cpu.branch_predictor.predictedNotTaken         2800                       # Number of Branches Predicted As Not Taken (False).
-system.cpu.regfile_manager.intRegFileReads        14401                       # Number of Reads from Int. Register File
-system.cpu.regfile_manager.intRegFileWrites        11111                       # Number of Writes to Int. Register File
-system.cpu.regfile_manager.intRegFileAccesses        25512                       # Total Accesses (Read+Write) to the Int. Register File
+system.cpu.branch_predictor.BTBHitPct       60.875746                       # BTB Hit Percentage
+system.cpu.branch_predictor.predictedTaken         2317                       # Number of Branches Predicted As Taken (True).
+system.cpu.branch_predictor.predictedNotTaken         2703                       # Number of Branches Predicted As Not Taken (False).
+system.cpu.regfile_manager.intRegFileReads        14367                       # Number of Reads from Int. Register File
+system.cpu.regfile_manager.intRegFileWrites        11099                       # Number of Writes to Int. Register File
+system.cpu.regfile_manager.intRegFileAccesses        25466                       # Total Accesses (Read+Write) to the Int. Register File
 system.cpu.regfile_manager.floatRegFileReads            0                       # Number of Reads from FP Register File
 system.cpu.regfile_manager.floatRegFileWrites            0                       # Number of Writes to FP Register File
 system.cpu.regfile_manager.floatRegFileAccesses            0                       # Total Accesses (Read+Write) to the FP Register File
-system.cpu.regfile_manager.regForwards           4991                       # Number of Registers Read Through Forwarding Logic
-system.cpu.agen_unit.agens                       3950                       # Number of Address Generations
-system.cpu.execution_unit.predictedTakenIncorrect         1316                       # Number of Branches Incorrectly Predicted As Taken.
-system.cpu.execution_unit.predictedNotTakenIncorrect         1000                       # Number of Branches Incorrectly Predicted As Not Taken).
-system.cpu.execution_unit.mispredicted           2316                       # Number of Branches Incorrectly Predicted
+system.cpu.regfile_manager.regForwards           5027                       # Number of Registers Read Through Forwarding Logic
+system.cpu.agen_unit.agens                       3931                       # Number of Address Generations
+system.cpu.execution_unit.predictedTakenIncorrect         1367                       # Number of Branches Incorrectly Predicted As Taken.
+system.cpu.execution_unit.predictedNotTakenIncorrect          948                       # Number of Branches Incorrectly Predicted As Not Taken).
+system.cpu.execution_unit.mispredicted           2315                       # Number of Branches Incorrectly Predicted
 system.cpu.execution_unit.predicted              1043                       # Number of Branches Incorrectly Predicted
-system.cpu.execution_unit.mispredictPct     68.949092                       # Percentage of Incorrect Branches Predicts
-system.cpu.execution_unit.executions            11084                       # Number of Instructions Executed.
+system.cpu.execution_unit.mispredictPct     68.939845                       # Percentage of Incorrect Branches Predicts
+system.cpu.execution_unit.executions            11058                       # Number of Instructions Executed.
 system.cpu.mult_div_unit.multiplies                 0                       # Number of Multipy Operations Executed
 system.cpu.mult_div_unit.divides                    0                       # Number of Divide Operations Executed
 system.cpu.contextSwitches                          1                       # Number of context switches
 system.cpu.threadCycles                         22262                       # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
 system.cpu.smtCycles                                0                       # Total number of cycles that the CPU was in SMT-mode
-system.cpu.timesIdled                             525                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                           33883                       # Number of cycles cpu's stages were not processed
-system.cpu.runCycles                            17349                       # Number of cycles cpu stages are processed.
-system.cpu.activity                         33.863601                       # Percentage of cycles cpu is active
-system.cpu.comLoads                              2226                       # Number of Load instructions committed
+system.cpu.timesIdled                             524                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles                           33874                       # Number of cycles cpu's stages were not processed
+system.cpu.runCycles                            17356                       # Number of cycles cpu stages are processed.
+system.cpu.activity                         33.878587                       # Percentage of cycles cpu is active
+system.cpu.comLoads                              2225                       # Number of Load instructions committed
 system.cpu.comStores                             1448                       # Number of Store instructions committed
-system.cpu.comBranches                           3359                       # Number of Branches instructions committed
+system.cpu.comBranches                           3358                       # Number of Branches instructions committed
 system.cpu.comNops                                726                       # Number of Nop instructions committed
 system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
-system.cpu.comInts                               7177                       # Number of Integer instructions committed
+system.cpu.comInts                               7166                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                       15175                       # Number of Instructions committed (Per-Thread)
-system.cpu.committedOps                         15175                       # Number of Ops committed (Per-Thread)
+system.cpu.committedInsts                       15162                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                         15162                       # Number of Ops committed (Per-Thread)
 system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
-system.cpu.committedInsts_total                 15175                       # Number of Instructions committed (Total)
-system.cpu.cpi                               3.376079                       # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.committedInsts_total                 15162                       # Number of Instructions committed (Total)
+system.cpu.cpi                               3.378842                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                                nan                       # CPI: Total SMT-CPI
-system.cpu.cpi_total                         3.376079                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.296202                       # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.cpi_total                         3.378842                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.295959                       # IPC: Instructions Per Cycle (Per-Thread)
 system.cpu.smt_ipc                                nan                       # IPC: Total SMT-IPC
-system.cpu.ipc_total                         0.296202                       # IPC: Total IPC of All Threads
-system.cpu.stage0.idleCycles                    38139                       # Number of cycles 0 instructions are processed.
-system.cpu.stage0.runCycles                     13093                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage0.utilization               25.556293                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage1.idleCycles                    42033                       # Number of cycles 0 instructions are processed.
-system.cpu.stage1.runCycles                      9199                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage1.utilization               17.955575                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage2.idleCycles                    42406                       # Number of cycles 0 instructions are processed.
-system.cpu.stage2.runCycles                      8826                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage2.utilization               17.227514                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage3.idleCycles                    48347                       # Number of cycles 0 instructions are processed.
-system.cpu.stage3.runCycles                      2885                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage3.utilization                5.631246                       # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage4.idleCycles                    41905                       # Number of cycles 0 instructions are processed.
-system.cpu.stage4.runCycles                      9327                       # Number of cycles 1+ instructions are processed.
-system.cpu.stage4.utilization               18.205418                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.ipc_total                         0.295959                       # IPC: Total IPC of All Threads
+system.cpu.stage0.idleCycles                    38098                       # Number of cycles 0 instructions are processed.
+system.cpu.stage0.runCycles                     13132                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage0.utilization               25.633418                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage1.idleCycles                    42042                       # Number of cycles 0 instructions are processed.
+system.cpu.stage1.runCycles                      9188                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage1.utilization               17.934804                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage2.idleCycles                    42414                       # Number of cycles 0 instructions are processed.
+system.cpu.stage2.runCycles                      8816                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage2.utilization               17.208667                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage3.idleCycles                    48346                       # Number of cycles 0 instructions are processed.
+system.cpu.stage3.runCycles                      2884                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage3.utilization                5.629514                       # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage4.idleCycles                    41913                       # Number of cycles 0 instructions are processed.
+system.cpu.stage4.runCycles                      9317                       # Number of cycles 1+ instructions are processed.
+system.cpu.stage4.utilization               18.186609                       # Percentage of cycles stage was utilized (processing insts).
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                164.555255                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     2600                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                164.536889                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     2586                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    299                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                   8.695652                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                   8.648829                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     164.555255                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.080349                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.080349                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         2600                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            2600                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          2600                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             2600                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         2600                       # number of overall hits
-system.cpu.icache.overall_hits::total            2600                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          371                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           371                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          371                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            371                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          371                       # number of overall misses
-system.cpu.icache.overall_misses::total           371                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     20687000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     20687000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     20687000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     20687000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     20687000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     20687000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         2971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         2971                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         2971                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         2971                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         2971                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         2971                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124874                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.124874                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.124874                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.124874                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.124874                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.124874                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55760.107817                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 55760.107817                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 55760.107817                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 55760.107817                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 55760.107817                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 55760.107817                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     164.536889                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.080340                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.080340                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         2586                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2586                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2586                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2586                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2586                       # number of overall hits
+system.cpu.icache.overall_hits::total            2586                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          369                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           369                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          369                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            369                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          369                       # number of overall misses
+system.cpu.icache.overall_misses::total           369                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     20585000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     20585000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     20585000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     20585000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     20585000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     20585000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2955                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2955                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2955                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2955                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2955                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2955                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.124873                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.124873                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.124873                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.124873                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.124873                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.124873                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55785.907859                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 55785.907859                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55785.907859                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 55785.907859                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55785.907859                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 55785.907859                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        65500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -149,56 +149,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets        32750                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst           70                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           68                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           68                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           68                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           68                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           68                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           68                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16327000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total     16327000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16327000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total     16327000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16327000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total     16327000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.101313                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.101313                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.101313                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.101313                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54242.524917                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 54242.524917                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54242.524917                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 54242.524917                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16326500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16326500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16326500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16326500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16326500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16326500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.101861                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.101861                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.101861                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.101861                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.101861                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.101861                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54240.863787                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54240.863787                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54240.863787                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 54240.863787                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54240.863787                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 54240.863787                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 96.551113                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     3315                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 96.547387                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3314                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  24.021739                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  24.014493                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      96.551113                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.023572                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.023572                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         2168                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2168                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      96.547387                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023571                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023571                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2167                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2167                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1141                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1141                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3309                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3309                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3309                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3309                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          3308                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3308                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3308                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3308                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          301                       # number of WriteReq misses
@@ -215,24 +215,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data     21946000
 system.cpu.dcache.demand_miss_latency::total     21946000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data     21946000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     21946000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3668                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3668                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3668                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026056                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.026056                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026067                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.026067                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.208738                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.208738                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.097874                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.097874                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.097874                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.097874                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.097900                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.097900                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.097900                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.097900                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60137.931034                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 60137.931034                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61322.259136                       # average WriteReq miss latency
@@ -273,14 +273,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7717500
 system.cpu.dcache.demand_mshr_miss_latency::total      7717500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7717500                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7717500                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037623                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56367.924528                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56367.924528                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 55647.058824                       # average WriteReq mshr miss latency
@@ -291,16 +291,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55923.913043
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 55923.913043                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               195.062761                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               195.042677                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005714                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    163.946873                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.115888                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    163.928542                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.114135                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::cpu.inst     0.005003                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000950                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005953                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005952                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
@@ -318,17 +318,17 @@ system.cpu.l2cache.demand_misses::total           437                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
 system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15990000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15989500                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2926500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::total     18916500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18916000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4635000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      4635000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst     15990000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15989500                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.data      7561500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total     23551500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst     15990000                       # number of overall miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23551000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15989500                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.data      7561500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total     23551500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23551000                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
@@ -351,17 +351,17 @@ system.cpu.l2cache.demand_miss_rate::total     0.995444                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53478.260870                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53476.588629                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55216.981132                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 53740.056818                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::total 53738.636364                       # average ReadReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 54529.411765                       # average ReadExReq miss latency
 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 54529.411765                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53478.260870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53476.588629                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54793.478261                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 53893.592677                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53478.260870                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 53892.448513                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53476.588629                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54793.478261                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 53893.592677                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 53892.448513                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
index f6619bb03d48ffdc5e550866caef7c013099d8b5..c2f5f7c25477afaac57fb88789dbec4562f58b55 100644 (file)
@@ -512,7 +512,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 47b15000f0c3ea7291948cff5a195e7da3b32a8f..d7d566072470133d7e1e114e6d7ce1b25dd1c104 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:30:59
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:20
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -18,4 +18,4 @@ LDTX:         Passed
 LDTW:          Passed
 STTW:          Passed
 Done
-Exiting @ tick 20274500 because target called exit()
+Exiting @ tick 20275500 because target called exit()
index 49a67051ba0e5372d4912e1bd1c92f6b2011deb7..37adfc3c4d10538385a489fbf5212f4ceae92cc1 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000020                       # Number of seconds simulated
-sim_ticks                                    20274500                       # Number of ticks simulated
-final_tick                                   20274500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    20275500                       # Number of ticks simulated
+final_tick                                   20275500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55162                       # Simulator instruction rate (inst/s)
-host_op_rate                                    55159                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               77392529                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220968                       # Number of bytes of host memory used
-host_seconds                                     0.26                       # Real time elapsed on the host
-sim_insts                                       14449                       # Number of instructions simulated
-sim_ops                                         14449                       # Number of ops (including micro ops) simulated
+host_inst_rate                                  60587                       # Simulator instruction rate (inst/s)
+host_op_rate                                    60583                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               85082969                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 230436                       # Number of bytes of host memory used
+host_seconds                                     0.24                       # Real time elapsed on the host
+sim_insts                                       14436                       # Number of instructions simulated
+sim_ops                                         14436                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             21568                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              9344                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                30912                       # Number of bytes read from this memory
@@ -19,323 +19,323 @@ system.physmem.bytes_inst_read::total           21568                       # Nu
 system.physmem.num_reads::cpu.inst                337                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                146                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   483                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst           1063799354                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            460874498                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              1524673851                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      1063799354                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         1063799354                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          1063799354                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           460874498                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total             1524673851                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           1063746887                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            460851767                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              1524598654                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      1063746887                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         1063746887                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          1063746887                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           460851767                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total             1524598654                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            40550                       # number of cpu cycles simulated
+system.cpu.numCycles                            40552                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.BPredUnit.lookups                     6892                       # Number of BP lookups
-system.cpu.BPredUnit.condPredicted               4586                       # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect               1120                       # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups                  5125                       # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits                     2600                       # Number of BTB hits
+system.cpu.BPredUnit.lookups                     6886                       # Number of BP lookups
+system.cpu.BPredUnit.condPredicted               4580                       # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect               1118                       # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups                  5120                       # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits                     2601                       # Number of BTB hits
 system.cpu.BPredUnit.BTBCorrect                     0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu.BPredUnit.usedRAS                      458                       # Number of times the RAS was used to get a target.
 system.cpu.BPredUnit.RASInCorrect                 168                       # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles              12259                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts                          32259                       # Number of instructions fetch has processed
-system.cpu.fetch.Branches                        6892                       # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches               3058                       # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles                          9557                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles                    3181                       # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles              12252                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts                          32221                       # Number of instructions fetch has processed
+system.cpu.fetch.Branches                        6886                       # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches               3059                       # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles                          9555                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles                    3174                       # Number of cycles fetch has spent squashing
 system.cpu.fetch.BlockedCycles                   7365                       # Number of cycles fetch has spent blocked
 system.cpu.fetch.MiscStallCycles                    4                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
 system.cpu.fetch.PendingTrapStallCycles           767                       # Number of stall cycles due to pending traps
-system.cpu.fetch.CacheLines                      5500                       # Number of cache lines fetched
+system.cpu.fetch.CacheLines                      5498                       # Number of cache lines fetched
 system.cpu.fetch.IcacheSquashes                   472                       # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples              31917                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean              1.010715                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev             2.185460                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples              31903                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean              1.009968                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev             2.184021                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0                    22360     70.06%     70.06% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1                     4750     14.88%     84.94% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2                      493      1.54%     86.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3                      436      1.37%     87.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4                      686      2.15%     90.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5                      773      2.42%     92.42% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6                      235      0.74%     93.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7                      276      0.86%     94.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8                     1908      5.98%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0                    22348     70.05%     70.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1                     4753     14.90%     84.95% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2                      493      1.55%     86.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3                      436      1.37%     87.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4                      686      2.15%     90.01% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5                      773      2.42%     92.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6                      236      0.74%     93.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7                      275      0.86%     94.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8                     1903      5.96%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
 system.cpu.fetch.rateDist::max_value                8                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total                31917                       # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate                  0.169963                       # Number of branch fetches per cycle
-system.cpu.fetch.rate                        0.795536                       # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles                    12903                       # Number of cycles decode is idle
+system.cpu.fetch.rateDist::total                31903                       # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate                  0.169807                       # Number of branch fetches per cycle
+system.cpu.fetch.rate                        0.794560                       # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles                    12897                       # Number of cycles decode is idle
 system.cpu.decode.BlockedCycles                  8133                       # Number of cycles decode is blocked
-system.cpu.decode.RunCycles                      8719                       # Number of cycles decode is running
+system.cpu.decode.RunCycles                      8716                       # Number of cycles decode is running
 system.cpu.decode.UnblockCycles                   197                       # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles                   1965                       # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts                  30080                       # Number of instructions handled by decode
-system.cpu.rename.SquashCycles                   1965                       # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles                    13582                       # Number of cycles rename is idle
+system.cpu.decode.SquashCycles                   1960                       # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts                  30041                       # Number of instructions handled by decode
+system.cpu.rename.SquashCycles                   1960                       # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles                    13576                       # Number of cycles rename is idle
 system.cpu.rename.BlockCycles                     285                       # Number of cycles rename is blocking
 system.cpu.rename.serializeStallCycles           7298                       # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles                      8277                       # Number of cycles rename is running
+system.cpu.rename.RunCycles                      8274                       # Number of cycles rename is running
 system.cpu.rename.UnblockCycles                   510                       # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts                  27385                       # Number of instructions processed by rename
+system.cpu.rename.RenamedInsts                  27346                       # Number of instructions processed by rename
 system.cpu.rename.IQFullEvents                     11                       # Number of times rename has blocked due to IQ full
 system.cpu.rename.LSQFullEvents                   172                       # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RenamedOperands               24421                       # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups                 50913                       # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups            50913                       # Number of integer rename lookups
-system.cpu.rename.CommittedMaps                 13832                       # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps                    10589                       # Number of HB maps that are undone due to squashing
+system.cpu.rename.RenamedOperands               24383                       # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups                 50854                       # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups            50854                       # Number of integer rename lookups
+system.cpu.rename.CommittedMaps                 13819                       # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps                    10564                       # Number of HB maps that are undone due to squashing
 system.cpu.rename.serializingInsts                704                       # count of serializing insts renamed
 system.cpu.rename.tempSerializingInsts            706                       # count of temporary serializing insts renamed
 system.cpu.rename.skidInsts                      2903                       # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads                 3640                       # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores                2472                       # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.insertedLoads                 3638                       # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores                2471                       # Number of stores inserted to the mem dependence unit.
 system.cpu.memDep0.conflictingLoads                 4                       # Number of conflicting loads.
 system.cpu.memDep0.conflictingStores                0                       # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded                      23148                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded                      23123                       # Number of instructions added to the IQ (excludes non-spec)
 system.cpu.iq.iqNonSpecInstsAdded                 669                       # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued                     21730                       # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued               108                       # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined            8364                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined         5915                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued                     21711                       # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued               106                       # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined            8357                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined         5906                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu.iq.iqSquashedNonSpecRemoved            194                       # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples         31917                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean         0.680828                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev        1.297413                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples         31903                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean         0.680532                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev        1.296567                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0               22417     70.24%     70.24% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1                3682     11.54%     81.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2                2373      7.43%     89.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3                1722      5.40%     94.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4                 904      2.83%     97.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5                 493      1.54%     98.98% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6                 244      0.76%     99.74% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7                  65      0.20%     99.95% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0               22407     70.23%     70.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1                3681     11.54%     81.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2                2373      7.44%     89.21% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3                1722      5.40%     94.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4                 903      2.83%     97.44% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5                 494      1.55%     98.99% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6                 242      0.76%     99.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7                  64      0.20%     99.95% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::8                  17      0.05%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total           31917                       # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total           31903                       # Number of insts issued each cycle
 system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu                      46     26.59%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult                      0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv                       0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult                    0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.59% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead                     24     13.87%     40.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite                   103     59.54%    100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu                      45     26.16%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult                      0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv                       0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult                    0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd                      0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu                      0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp                      0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt                      0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift                    0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc                0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     26.16% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead                     24     13.95%     40.12% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite                   103     59.88%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
 system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu                 16031     73.77%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.77% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead                 3433     15.80%     89.57% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite                2266     10.43%    100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu                 16013     73.76%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult                    0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc              0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     73.76% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead                 3432     15.81%     89.56% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite                2266     10.44%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
 system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total                  21730                       # Type of FU issued
-system.cpu.iq.rate                           0.535882                       # Inst issue rate
-system.cpu.iq.fu_busy_cnt                         173                       # FU busy when requested
-system.cpu.iq.fu_busy_rate                   0.007961                       # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads              75658                       # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes             32207                       # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses        19957                       # Number of integer instruction queue wakeup accesses
+system.cpu.iq.FU_type_0::total                  21711                       # Type of FU issued
+system.cpu.iq.rate                           0.535387                       # Inst issue rate
+system.cpu.iq.fu_busy_cnt                         172                       # FU busy when requested
+system.cpu.iq.fu_busy_rate                   0.007922                       # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads              75603                       # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes             32175                       # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses        19936                       # Number of integer instruction queue wakeup accesses
 system.cpu.iq.fp_inst_queue_reads                   0                       # Number of floating instruction queue reads
 system.cpu.iq.fp_inst_queue_writes                  0                       # Number of floating instruction queue writes
 system.cpu.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses                  21903                       # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses                  21883                       # Number of integer alu accesses
 system.cpu.iq.fp_alu_accesses                       0                       # Number of floating point alu accesses
 system.cpu.iew.lsq.thread0.forwLoads               26                       # Number of loads that had data forwarded from stores
 system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads         1414                       # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads         1413                       # Number of loads squashed
 system.cpu.iew.lsq.thread0.ignoredResponses            2                       # Number of memory responses ignored because the instruction is squashed
 system.cpu.iew.lsq.thread0.memOrderViolation           27                       # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores         1024                       # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores         1023                       # Number of stores squashed
 system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
 system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu.iew.lsq.thread0.rescheduledLoads            1                       # Number of loads that were rescheduled
 system.cpu.iew.lsq.thread0.cacheBlocked             0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles                   1965                       # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles                   1960                       # Number of cycles IEW is squashing
 system.cpu.iew.iewBlockCycles                      99                       # Number of cycles IEW is blocking
 system.cpu.iew.iewUnblockCycles                     5                       # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts               24982                       # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts               417                       # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts                  3640                       # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts                 2472                       # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts               24957                       # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts               410                       # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts                  3638                       # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts                 2471                       # Number of dispatched store instructions
 system.cpu.iew.iewDispNonSpecInsts                669                       # Number of dispatched non-speculative instructions
 system.cpu.iew.iewIQFullEvents                      2                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                     0                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents             27                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect            291                       # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect          958                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts                 1249                       # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts                 20553                       # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts                  3273                       # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts              1177                       # Number of squashed instructions skipped in execute
+system.cpu.iew.predictedTakenIncorrect            290                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect          957                       # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts                 1247                       # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts                 20532                       # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts                  3272                       # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts              1179                       # Number of squashed instructions skipped in execute
 system.cpu.iew.exec_swp                             0                       # number of swp insts executed
 system.cpu.iew.exec_nop                          1165                       # number of nop insts executed
-system.cpu.iew.exec_refs                         5419                       # number of memory reference insts executed
-system.cpu.iew.exec_branches                     4294                       # Number of branches executed
+system.cpu.iew.exec_refs                         5418                       # number of memory reference insts executed
+system.cpu.iew.exec_branches                     4292                       # Number of branches executed
 system.cpu.iew.exec_stores                       2146                       # Number of stores executed
-system.cpu.iew.exec_rate                     0.506856                       # Inst execution rate
-system.cpu.iew.wb_sent                          20221                       # cumulative count of insts sent to commit
-system.cpu.iew.wb_count                         19957                       # cumulative count of insts written-back
-system.cpu.iew.wb_producers                      9257                       # num instructions producing a value
-system.cpu.iew.wb_consumers                     11359                       # num instructions consuming a value
+system.cpu.iew.exec_rate                     0.506313                       # Inst execution rate
+system.cpu.iew.wb_sent                          20199                       # cumulative count of insts sent to commit
+system.cpu.iew.wb_count                         19936                       # cumulative count of insts written-back
+system.cpu.iew.wb_producers                      9239                       # num instructions producing a value
+system.cpu.iew.wb_consumers                     11338                       # num instructions consuming a value
 system.cpu.iew.wb_penalized                         0                       # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate                       0.492158                       # insts written-back per cycle
-system.cpu.iew.wb_fanout                     0.814948                       # average fanout of values written-back
+system.cpu.iew.wb_rate                       0.491616                       # insts written-back per cycle
+system.cpu.iew.wb_fanout                     0.814870                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts          15175                       # The number of committed instructions
-system.cpu.commit.commitCommittedOps            15175                       # The number of committed instructions
-system.cpu.commit.commitSquashedInsts            9725                       # The number of squashed insts skipped by commit
+system.cpu.commit.commitCommittedInsts          15162                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps            15162                       # The number of committed instructions
+system.cpu.commit.commitSquashedInsts            9713                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts              1120                       # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples        29969                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean     0.506357                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev     1.189037                       # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts              1118                       # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples        29960                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean     0.506075                       # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev     1.188090                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0        22543     75.22%     75.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1         4136     13.80%     89.02% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2         1421      4.74%     93.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3          789      2.63%     96.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4          331      1.10%     97.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5          259      0.86%     98.36% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0        22536     75.22%     75.22% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1         4135     13.80%     89.02% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2         1423      4.75%     93.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3          788      2.63%     96.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4          331      1.10%     97.51% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5          258      0.86%     98.37% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::6          318      1.06%     99.43% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::7           73      0.24%     99.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8           99      0.33%    100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8           98      0.33%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total        29969                       # Number of insts commited each cycle
-system.cpu.commit.committedInsts                15175                       # Number of instructions committed
-system.cpu.commit.committedOps                  15175                       # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total        29960                       # Number of insts commited each cycle
+system.cpu.commit.committedInsts                15162                       # Number of instructions committed
+system.cpu.commit.committedOps                  15162                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
-system.cpu.commit.refs                           3674                       # Number of memory references committed
-system.cpu.commit.loads                          2226                       # Number of loads committed
+system.cpu.commit.refs                           3673                       # Number of memory references committed
+system.cpu.commit.loads                          2225                       # Number of loads committed
 system.cpu.commit.membars                           0                       # Number of memory barriers committed
-system.cpu.commit.branches                       3359                       # Number of branches committed
+system.cpu.commit.branches                       3358                       # Number of branches committed
 system.cpu.commit.fp_insts                          0                       # Number of committed floating point instructions.
-system.cpu.commit.int_insts                     12186                       # Number of committed integer instructions.
+system.cpu.commit.int_insts                     12174                       # Number of committed integer instructions.
 system.cpu.commit.function_calls                  187                       # Number of function calls committed.
-system.cpu.commit.bw_lim_events                    99                       # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events                    98                       # number cycles where commit BW limit reached
 system.cpu.commit.bw_limited                        0                       # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads                        53947                       # The number of ROB reads
-system.cpu.rob.rob_writes                       51773                       # The number of ROB writes
+system.cpu.rob.rob_reads                        53914                       # The number of ROB reads
+system.cpu.rob.rob_writes                       51717                       # The number of ROB writes
 system.cpu.timesIdled                             196                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles                            8633                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                       14449                       # Number of Instructions Simulated
-system.cpu.committedOps                         14449                       # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total                 14449                       # Number of Instructions Simulated
-system.cpu.cpi                               2.806423                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.806423                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.356326                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.356326                       # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads                    32739                       # number of integer regfile reads
-system.cpu.int_regfile_writes                   18191                       # number of integer regfile writes
-system.cpu.misc_regfile_reads                    7070                       # number of misc regfile reads
+system.cpu.idleCycles                            8649                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.committedInsts                       14436                       # Number of Instructions Simulated
+system.cpu.committedOps                         14436                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                 14436                       # Number of Instructions Simulated
+system.cpu.cpi                               2.809088                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         2.809088                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.355987                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.355987                       # IPC: Total IPC of All Threads
+system.cpu.int_regfile_reads                    32709                       # number of integer regfile reads
+system.cpu.int_regfile_writes                   18169                       # number of integer regfile writes
+system.cpu.misc_regfile_reads                    7069                       # number of misc regfile reads
 system.cpu.misc_regfile_writes                    569                       # number of misc regfile writes
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                199.218311                       # Cycle average of tags in use
-system.cpu.icache.total_refs                     5020                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                199.209373                       # Cycle average of tags in use
+system.cpu.icache.total_refs                     5019                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    339                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  14.808260                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  14.805310                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     199.218311                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.097275                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.097275                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst         5020                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total            5020                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst          5020                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total             5020                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst         5020                       # number of overall hits
-system.cpu.icache.overall_hits::total            5020                       # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst          480                       # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total           480                       # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst          480                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total            480                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst          480                       # number of overall misses
-system.cpu.icache.overall_misses::total           480                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst     16877500                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total     16877500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst     16877500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total     16877500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst     16877500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total     16877500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst         5500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total         5500                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst         5500                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total         5500                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst         5500                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total         5500                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.087273                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.087273                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.087273                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.087273                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.087273                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.087273                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.458333                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35161.458333                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.458333                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35161.458333                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.458333                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35161.458333                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     199.209373                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.097270                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.097270                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5019                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5019                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5019                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5019                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5019                       # number of overall hits
+system.cpu.icache.overall_hits::total            5019                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          479                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           479                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          479                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            479                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          479                       # number of overall misses
+system.cpu.icache.overall_misses::total           479                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16863000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16863000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16863000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16863000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16863000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16863000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5498                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5498                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5498                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5498                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5498                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5498                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.087123                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.087123                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.087123                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.087123                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.087123                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.087123                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35204.592902                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35204.592902                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35204.592902                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35204.592902                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35204.592902                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 35204.592902                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -344,12 +344,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst          141                       # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total          141                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst          141                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total          141                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst          141                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total          141                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          140                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          140                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          140                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          140                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          140                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          140                       # number of overall MSHR hits
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst          339                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          339                       # number of ReadReq MSHR misses
 system.cpu.icache.demand_mshr_misses::cpu.inst          339                       # number of demand (read+write) MSHR misses
@@ -362,12 +362,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12213000
 system.cpu.icache.demand_mshr_miss_latency::total     12213000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12213000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     12213000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.061636                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.061636                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.061636                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.061636                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.061659                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.061659                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.061659                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.061659                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.061659                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.061659                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36026.548673                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36026.548673                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36026.548673                       # average overall mshr miss latency
@@ -376,24 +376,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36026.548673
 system.cpu.icache.overall_avg_mshr_miss_latency::total 36026.548673                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                102.764065                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     4075                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                102.759786                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     4074                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  27.910959                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  27.904110                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data     102.764065                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.025089                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.025089                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         3036                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            3036                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     102.759786                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025088                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025088                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         3035                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3035                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1033                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1033                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          4069                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             4069                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         4069                       # number of overall hits
-system.cpu.dcache.overall_hits::total            4069                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          4068                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4068                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4068                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4068                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data          121                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total           121                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data          409                       # number of WriteReq misses
@@ -410,24 +410,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data     22300500
 system.cpu.dcache.demand_miss_latency::total     22300500                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data     22300500                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     22300500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         3157                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         3157                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         3156                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3156                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         4599                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         4599                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         4599                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         4599                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.038328                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.038328                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         4598                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4598                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4598                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4598                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.038340                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.038340                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.283634                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.283634                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.115242                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.115242                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.115242                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.115242                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.115268                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.115268                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.115268                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.115268                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38425.619835                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 38425.619835                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43156.479218                       # average WriteReq miss latency
@@ -468,14 +468,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5811000
 system.cpu.dcache.demand_mshr_miss_latency::total      5811000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5811000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      5811000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019956                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019956                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.019962                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.019962                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031746                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.031746                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031746                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.031746                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031753                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.031753                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031753                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.031753                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39968.253968                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39968.253968                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39674.698795                       # average WriteReq mshr miss latency
@@ -486,13 +486,13 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39801.369863
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 39801.369863                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               234.467813                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               234.457580                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   400                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005000                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    198.479082                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     35.988731                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    198.470180                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     35.987400                       # Average occupied blocks per requestor
 system.cpu.l2cache.occ_percent::cpu.inst     0.006057                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.001098                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::total        0.007155                       # Average percentage of cache occupancy
index 9dd70f31474022835d2c932d70e54a24e0006fe3..2d696d139c6fcb5888656fbe574cd9e9f3b870e5 100644 (file)
@@ -99,8 +99,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 
 [system.physmem]
index 0a6c1bd0d20a782715173f63ab1ba32b84bb7830..ffad57b6be9aebdc15373473876ad7828690838e 100755 (executable)
@@ -1,8 +1,8 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  4 2012 12:01:47
-gem5 started Jun  4 2012 14:45:04
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:25
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
@@ -18,4 +18,4 @@ LDTX:         Passed
 LDTW:          Passed
 STTW:          Passed
 Done
-Exiting @ tick 7618500 because target called exit()
+Exiting @ tick 7612000 because target called exit()
index a62ce7951dfc8353f3025509f570353aab23a4cf..feda286ecd972fc3800be32d601c57aebf40ab88 100644 (file)
@@ -1,61 +1,61 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000008                       # Number of seconds simulated
-sim_ticks                                     7618500                       # Number of ticks simulated
-final_tick                                    7618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                     7612000                       # Number of ticks simulated
+final_tick                                    7612000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 949089                       # Simulator instruction rate (inst/s)
-host_op_rate                                   948034                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              475431989                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212076                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
-sim_insts                                       15175                       # Number of instructions simulated
-sim_ops                                         15175                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu.inst             60880                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data             11343                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                72223                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst        60880                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           60880                       # Number of instructions bytes read from this memory
+host_inst_rate                                1344667                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1342613                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              673049198                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220960                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+sim_insts                                       15162                       # Number of instructions simulated
+sim_ops                                         15162                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu.inst             60828                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data             11342                       # Number of bytes read from this memory
+system.physmem.bytes_read::total                72170                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst        60828                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total           60828                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::cpu.data           9042                       # Number of bytes written to this memory
 system.physmem.bytes_written::total              9042                       # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst              15220                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data               2226                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                 17446                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              15207                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data               2225                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total                 17432                       # Number of read requests responded to by this memory
 system.physmem.num_writes::cpu.data              1442                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                 1442                       # Number of write requests responded to by this memory
 system.physmem.num_other::cpu.data                  6                       # Number of other requests responded to by this memory
 system.physmem.num_other::total                     6                       # Number of other requests responded to by this memory
-system.physmem.bw_read::cpu.inst           7991074358                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data           1488875763                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total              9479950121                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst      7991074358                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total         7991074358                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data          1186847805                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total             1186847805                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst          7991074358                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data          2675723568                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total            10666797926                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst           7991066737                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data           1490015765                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total              9481082501                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst      7991066737                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total         7991066737                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data          1187861272                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total             1187861272                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst          7991066737                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data          2677877036                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total            10668943773                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            15238                       # number of cpu cycles simulated
+system.cpu.numCycles                            15225                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15175                       # Number of instructions committed
-system.cpu.committedOps                         15175                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
+system.cpu.committedInsts                       15162                       # Number of instructions committed
+system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2435                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12231                       # number of integer instructions
+system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                        12219                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13832                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              13819                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3684                       # number of memory refs
-system.cpu.num_load_insts                        2232                       # Number of load instructions
+system.cpu.num_mem_refs                          3683                       # number of memory refs
+system.cpu.num_load_insts                        2231                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      15238                       # Number of busy cycles
+system.cpu.num_busy_cycles                      15225                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 
index 10c1546b59f0f30ec07963cbb9efa46ae18f827c..a7594cb676b64802a60ca4e8f8992d5b6879ca31 100644 (file)
@@ -181,7 +181,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
index 71ca2d641cc1bdbd45311a5920304ead24e0321b..cacf98182c692db2e3c46e17b053d3e13fb0b41b 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:31:22
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:28
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
@@ -18,4 +18,4 @@ LDTX:         Passed
 LDTW:          Passed
 STTW:          Passed
 Done
-Exiting @ tick 43120000 because target called exit()
+Exiting @ tick 43106000 because target called exit()
index 54833842f7dbd7029da05f2777abd1907294fecd..4464561a48e69c9ea691730f5a4ed2931fc70953 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000043                       # Number of seconds simulated
-sim_ticks                                    43120000                       # Number of ticks simulated
-final_tick                                   43120000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    43106000                       # Number of ticks simulated
+final_tick                                   43106000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107758                       # Simulator instruction rate (inst/s)
-host_op_rate                                   107745                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              306125993                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219936                       # Number of bytes of host memory used
-host_seconds                                     0.14                       # Real time elapsed on the host
-sim_insts                                       15175                       # Number of instructions simulated
-sim_ops                                         15175                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 377775                       # Simulator instruction rate (inst/s)
+host_op_rate                                   377609                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1073121241                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229408                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
+sim_insts                                       15162                       # Number of instructions simulated
+sim_ops                                         15162                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst             17792                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data              8832                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                26624                       # Number of bytes read from this memory
@@ -19,52 +19,52 @@ system.physmem.bytes_inst_read::total           17792                       # Nu
 system.physmem.num_reads::cpu.inst                278                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data                138                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   416                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst            412615955                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data            204823748                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               617439703                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst       412615955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          412615955                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst           412615955                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data           204823748                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              617439703                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst            412749965                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data            204890270                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               617640236                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst       412749965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          412749965                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst           412749965                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data           204890270                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              617640236                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.workload.num_syscalls                   18                       # Number of system calls
-system.cpu.numCycles                            86240                       # number of cpu cycles simulated
+system.cpu.numCycles                            86212                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.committedInsts                       15175                       # Number of instructions committed
-system.cpu.committedOps                         15175                       # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
+system.cpu.committedInsts                       15162                       # Number of instructions committed
+system.cpu.committedOps                         15162                       # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses                 12219                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         385                       # number of times a function call or return occured
-system.cpu.num_conditional_control_insts         2435                       # number of instructions that are conditional controls
-system.cpu.num_int_insts                        12231                       # number of integer instructions
+system.cpu.num_conditional_control_insts         2434                       # number of instructions that are conditional controls
+system.cpu.num_int_insts                        12219                       # number of integer instructions
 system.cpu.num_fp_insts                             0                       # number of float instructions
-system.cpu.num_int_register_reads               29059                       # number of times the integer registers were read
-system.cpu.num_int_register_writes              13831                       # number of times the integer registers were written
+system.cpu.num_int_register_reads               29037                       # number of times the integer registers were read
+system.cpu.num_int_register_writes              13818                       # number of times the integer registers were written
 system.cpu.num_fp_register_reads                    0                       # number of times the floating registers were read
 system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
-system.cpu.num_mem_refs                          3684                       # number of memory refs
-system.cpu.num_load_insts                        2232                       # Number of load instructions
+system.cpu.num_mem_refs                          3683                       # number of memory refs
+system.cpu.num_load_insts                        2231                       # Number of load instructions
 system.cpu.num_store_insts                       1452                       # Number of store instructions
 system.cpu.num_idle_cycles                          0                       # Number of idle cycles
-system.cpu.num_busy_cycles                      86240                       # Number of busy cycles
+system.cpu.num_busy_cycles                      86212                       # Number of busy cycles
 system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                            0                       # Percentage of idle cycles
 system.cpu.icache.replacements                      0                       # number of replacements
-system.cpu.icache.tagsinuse                152.912665                       # Cycle average of tags in use
-system.cpu.icache.total_refs                    14941                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                152.957781                       # Cycle average of tags in use
+system.cpu.icache.total_refs                    14928                       # Total number of references to valid blocks.
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  53.314286                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst     152.912665                       # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst      0.074664                       # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total         0.074664                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst        14941                       # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total           14941                       # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst         14941                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total            14941                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst        14941                       # number of overall hits
-system.cpu.icache.overall_hits::total           14941                       # number of overall hits
+system.cpu.icache.occ_blocks::cpu.inst     152.957781                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.074686                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.074686                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst        14928                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total           14928                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst         14928                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total            14928                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst        14928                       # number of overall hits
+system.cpu.icache.overall_hits::total           14928                       # number of overall hits
 system.cpu.icache.ReadReq_misses::cpu.inst          280                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total           280                       # number of ReadReq misses
 system.cpu.icache.demand_misses::cpu.inst          280                       # number of demand (read+write) misses
@@ -77,18 +77,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst     15596000
 system.cpu.icache.demand_miss_latency::total     15596000                       # number of demand (read+write) miss cycles
 system.cpu.icache.overall_miss_latency::cpu.inst     15596000                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     15596000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst        15221                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total        15221                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst        15221                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total        15221                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst        15221                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total        15221                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018396                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total     0.018396                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst     0.018396                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     0.018396                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst     0.018396                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     0.018396                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst        15208                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total        15208                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst        15208                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total        15208                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst        15208                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total        15208                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018411                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_miss_rate::total     0.018411                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.018411                       # miss rate for demand accesses
+system.cpu.icache.demand_miss_rate::total     0.018411                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.018411                       # miss rate for overall accesses
+system.cpu.icache.overall_miss_rate::total     0.018411                       # miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55700                       # average ReadReq miss latency
 system.cpu.icache.ReadReq_avg_miss_latency::total        55700                       # average ReadReq miss latency
 system.cpu.icache.demand_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
@@ -115,12 +115,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14756000
 system.cpu.icache.demand_mshr_miss_latency::total     14756000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14756000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     14756000                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.018396                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.018396                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.018396                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total     0.018411                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total     0.018411                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018411                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate::total     0.018411                       # mshr miss rate for overall accesses
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        52700                       # average ReadReq mshr miss latency
 system.cpu.icache.ReadReq_avg_mshr_miss_latency::total        52700                       # average ReadReq mshr miss latency
 system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
@@ -129,24 +129,24 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700
 system.cpu.icache.overall_avg_mshr_miss_latency::total        52700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
-system.cpu.dcache.tagsinuse                 97.642881                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                     3536                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                 97.669722                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                     3535                       # Total number of references to valid blocks.
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
-system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                  25.615942                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::cpu.data      97.642881                       # Average occupied blocks per requestor
-system.cpu.dcache.occ_percent::cpu.data      0.023839                       # Average percentage of cache occupancy
-system.cpu.dcache.occ_percent::total         0.023839                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::cpu.data         2173                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total            2173                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data      97.669722                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023845                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023845                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2172                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2172                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total           1357                       # number of WriteReq hits
 system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
 system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data          3530                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total             3530                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data         3530                       # number of overall hits
-system.cpu.dcache.overall_hits::total            3530                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data          3529                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3529                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3529                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3529                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total            53                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data           85                       # number of WriteReq misses
@@ -163,24 +163,24 @@ system.cpu.dcache.demand_miss_latency::cpu.data      7728000
 system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data         2225                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2225                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
 system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data         3668                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total         3668                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data         3668                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023810                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total     0.023810                       # miss rate for ReadReq accesses
+system.cpu.dcache.demand_accesses::cpu.data         3667                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3667                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3667                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3667                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023820                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total     0.023820                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.058946                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data     0.037623                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     0.037623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data     0.037623                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     0.037623                       # miss rate for overall accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037633                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total     0.037633                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037633                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total     0.037633                       # miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total        56000                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
@@ -213,14 +213,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000
 system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023820                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.023820                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.037623                       # mshr miss rate for overall accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total     0.037633                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037633                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total     0.037633                       # mshr miss rate for overall accesses
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total        53000                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
@@ -231,16 +231,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000
 system.cpu.dcache.overall_avg_mshr_miss_latency::total        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
-system.cpu.l2cache.tagsinuse               183.636297                       # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse               183.688794                       # Cycle average of tags in use
 system.cpu.l2cache.total_refs                       2                       # Total number of references to valid blocks.
 system.cpu.l2cache.sampled_refs                   331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::cpu.inst    152.238639                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_blocks::cpu.data     31.397658                       # Average occupied blocks per requestor
-system.cpu.l2cache.occ_percent::cpu.inst     0.004646                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::cpu.inst    152.283537                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.405257                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004647                       # Average percentage of cache occupancy
 system.cpu.l2cache.occ_percent::cpu.data     0.000958                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::total        0.005604                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005606                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
 system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
index e18da5544f9113cda19187e46573ba510af5ec37..8f654c19e7b42555a633ac2704a386ade450840d 100644 (file)
@@ -1774,7 +1774,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
index 2447cd00ce09dce96783e25d4e9fc3c62d8a7ed9..63ee30b34dc28064e0ab28f458599d5eda423412 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:31:33
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:31
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
@@ -29,40 +29,40 @@ Iteration 2 completed
 [Iteration 3, Thread 3] Got lock
 [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 3 completed
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 4, Thread 1] Got lock
 [Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 4 completed
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 5, Thread 3] Got lock
 [Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 5 completed
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 6, Thread 2] Got lock
-[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 6 completed
 [Iteration 7, Thread 2] Got lock
 [Iteration 7, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 8 completed
 [Iteration 9, Thread 3] Got lock
 [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
@@ -73,10 +73,10 @@ Iteration 8 completed
 Iteration 9 completed
 [Iteration 10, Thread 2] Got lock
 [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 10, Thread 3] Got lock
+[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 113941500 because target called exit()
+Exiting @ tick 113910500 because target called exit()
index 08b3d0977d62e43255a5305a54760165860d73b4..a13e5619358c9667894eaa212104cc947faf296b 100644 (file)
@@ -1,17 +1,17 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000114                       # Number of seconds simulated
-sim_ticks                                   113941500                       # Number of ticks simulated
-final_tick                                  113941500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   113910500                       # Number of ticks simulated
+final_tick                                  113910500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 130117                       # Simulator instruction rate (inst/s)
-host_op_rate                                   130117                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                               13474596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 234988                       # Number of bytes of host memory used
-host_seconds                                     8.46                       # Real time elapsed on the host
-sim_insts                                     1100269                       # Number of instructions simulated
-sim_ops                                       1100269                       # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst            23232                       # Number of bytes read from this memory
+host_inst_rate                                 141669                       # Simulator instruction rate (inst/s)
+host_op_rate                                   141669                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               14682125                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 244464                       # Number of bytes of host memory used
+host_seconds                                     7.76                       # Real time elapsed on the host
+sim_insts                                     1099129                       # Number of instructions simulated
+sim_ops                                       1099129                       # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst            23168                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10752                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             5376                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data             1280                       # Number of bytes read from this memory
@@ -19,13 +19,13 @@ system.physmem.bytes_read::cpu2.inst              320                       # Nu
 system.physmem.bytes_read::cpu2.data              832                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.inst              384                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu3.data              832                       # Number of bytes read from this memory
-system.physmem.bytes_read::total                43008                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst        23232                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total                42944                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst        23168                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst         5376                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu2.inst          320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu3.inst          384                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total           29312                       # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst               363                       # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::total           29248                       # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst               362                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.data               168                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst                84                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data                20                       # Number of read requests responded to by this memory
@@ -33,340 +33,339 @@ system.physmem.num_reads::cpu2.inst                 5                       # Nu
 system.physmem.num_reads::cpu2.data                13                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.inst                 6                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total                   672                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           203894104                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            94364213                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            47182107                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            11233835                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             2808459                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             7301993                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             3370150                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             7301993                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               377456853                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      203894104                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       47182107                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        2808459                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        3370150                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          257254819                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          203894104                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           94364213                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           47182107                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           11233835                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            2808459                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            3370150                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            7301993                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              377456853                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.num_reads::total                   671                       # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst           203387747                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            94389894                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            47194947                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            11236892                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             2809223                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             7303980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             3371068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             7303980                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               376997731                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      203387747                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       47194947                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        2809223                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        3371068                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          256762985                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          203387747                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           94389894                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           47194947                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           11236892                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            2809223                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            7303980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            3371068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            7303980                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              376997731                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          227884                       # number of cpu cycles simulated
+system.cpu0.numCycles                          227822                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                   88195                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted             85894                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect              1314                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups                85741                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                   83416                       # Number of BTB hits
+system.cpu0.BPredUnit.lookups                   88179                       # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted             85929                       # Number of conditional branches predicted
+system.cpu0.BPredUnit.condIncorrect              1290                       # Number of conditional branches incorrect
+system.cpu0.BPredUnit.BTBLookups                85894                       # Number of BTB lookups
+system.cpu0.BPredUnit.BTBHits                   83486                       # Number of BTB hits
 system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
 system.cpu0.BPredUnit.usedRAS                     517                       # Number of times the RAS was used to get a target.
 system.cpu0.BPredUnit.RASInCorrect                132                       # Number of incorrect RAS predictions.
-system.cpu0.fetch.icacheStallCycles             17885                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts                        523742                       # Number of instructions fetch has processed
-system.cpu0.fetch.Branches                      88195                       # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches             83933                       # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles                       172058                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles                   4069                       # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles                 15014                       # Number of cycles fetch has spent blocked
+system.cpu0.fetch.icacheStallCycles             17727                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts                        523680                       # Number of instructions fetch has processed
+system.cpu0.fetch.Branches                      88179                       # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches             84003                       # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles                       172095                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles                   4009                       # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles                 15408                       # Number of cycles fetch has spent blocked
 system.cpu0.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles         1439                       # Number of stall cycles due to pending traps
-system.cpu0.fetch.CacheLines                     6122                       # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes                  517                       # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples            209007                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean             2.505859                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev            2.211450                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.PendingTrapStallCycles         1281                       # Number of stall cycles due to pending traps
+system.cpu0.fetch.CacheLines                     6036                       # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes                  519                       # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples            209087                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean             2.504603                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev            2.209881                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0                   36949     17.68%     17.68% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1                   85270     40.80%     58.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2                     593      0.28%     58.76% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3                    1005      0.48%     59.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4                     500      0.24%     59.48% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5                   81190     38.85%     98.33% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6                     659      0.32%     98.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7                     361      0.17%     98.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8                    2480      1.19%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0                   36992     17.69%     17.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1                   85294     40.79%     58.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2                     585      0.28%     58.77% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3                    1000      0.48%     59.24% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4                     484      0.23%     59.48% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5                   81297     38.88%     98.36% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6                     665      0.32%     98.68% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7                     355      0.17%     98.84% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8                    2415      1.16%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu0.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total              209007                       # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate                 0.387017                       # Number of branch fetches per cycle
-system.cpu0.fetch.rate                       2.298283                       # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles                   18552                       # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles                16516                       # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles                   170985                       # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles                  348                       # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles                  2606                       # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts                520718                       # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles                  2606                       # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles                   19281                       # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles                   2206                       # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles         13583                       # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles                   170639                       # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles                  692                       # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts                517471                       # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents                     4                       # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents                  300                       # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands             353567                       # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups              1032190                       # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups         1032190                       # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps               339600                       # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps                   13967                       # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts               909                       # count of serializing insts renamed
+system.cpu0.fetch.rateDist::total              209087                       # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate                 0.387052                       # Number of branch fetches per cycle
+system.cpu0.fetch.rate                       2.298637                       # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles                   18268                       # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles                16880                       # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles                   171017                       # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles                  351                       # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles                  2571                       # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts                520658                       # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles                  2571                       # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles                   18993                       # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles                   2288                       # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles         13870                       # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles                   170679                       # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles                  686                       # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts                517484                       # Number of instructions processed by rename
+system.cpu0.rename.LSQFullEvents                  297                       # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands             353459                       # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups              1032335                       # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups         1032335                       # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps               339779                       # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps                   13680                       # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts               904                       # count of serializing insts renamed
 system.cpu0.rename.tempSerializingInsts           933                       # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts                     4082                       # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads              165924                       # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores              83735                       # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads            81055                       # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores           80764                       # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded                    432543                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded                950                       # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued                   429278                       # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued              221                       # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined          11501                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined        11387                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved           391                       # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples       209007                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean        2.053893                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev       1.097042                       # Number of insts issued each cycle
+system.cpu0.rename.skidInsts                     4009                       # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads              165974                       # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores              83785                       # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads            81138                       # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores           80830                       # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded                    432592                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded                951                       # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued                   429324                       # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued              270                       # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined          11361                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined        11323                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved           392                       # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples       209087                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean        2.053327                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev       1.097112                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0              36203     17.32%     17.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1               5360      2.56%     19.89% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2              82686     39.56%     59.45% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3              82056     39.26%     98.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4               1635      0.78%     99.49% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5                680      0.33%     99.81% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6                282      0.13%     99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0              36280     17.35%     17.35% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1               5325      2.55%     19.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2              82668     39.54%     59.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3              82134     39.28%     98.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4               1638      0.78%     99.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5                661      0.32%     99.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6                275      0.13%     99.95% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::7                 94      0.04%     99.99% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8                 11      0.01%    100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8                 12      0.01%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu0.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total         209007                       # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total         209087                       # Number of insts issued each cycle
 system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu                     43     16.23%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult                     0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv                      0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult                   0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift                   0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     16.23% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead                   110     41.51%     57.74% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite                  112     42.26%    100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu                     52     18.77%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv                      0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult                   0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift                   0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc               0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     18.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead                   113     40.79%     59.57% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite                  112     40.43%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu0.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu               180966     42.16%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.16% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead              165240     38.49%     80.65% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite              83072     19.35%    100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu               180924     42.14%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult                   0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv                    0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc                0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu                   0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc             0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     42.14% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead              165296     38.50%     80.64% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite              83104     19.36%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total                429278                       # Type of FU issued
-system.cpu0.iq.rate                          1.883757                       # Inst issue rate
-system.cpu0.iq.fu_busy_cnt                        265                       # FU busy when requested
-system.cpu0.iq.fu_busy_rate                  0.000617                       # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads           1068049                       # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes           445050                       # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses       427325                       # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total                429324                       # Type of FU issued
+system.cpu0.iq.rate                          1.884471                       # Inst issue rate
+system.cpu0.iq.fu_busy_cnt                        277                       # FU busy when requested
+system.cpu0.iq.fu_busy_rate                  0.000645                       # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads           1068282                       # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes           444960                       # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses       427393                       # Number of integer instruction queue wakeup accesses
 system.cpu0.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu0.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu0.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses                429543                       # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses                429601                       # Number of integer alu accesses
 system.cpu0.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads           80408                       # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads           80458                       # Number of loads that had data forwarded from stores
 system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads         2540                       # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.squashedLoads         2495                       # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses            4                       # Number of memory responses ignored because the instruction is squashed
 system.cpu0.iew.lsq.thread0.memOrderViolation           56                       # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores         1537                       # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores         1539                       # Number of stores squashed
 system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu0.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu0.iew.lsq.thread0.cacheBlocked            8                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles                  2606                       # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles                   1701                       # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles                   86                       # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts             515038                       # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts              368                       # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts               165924                       # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts               83735                       # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts               837                       # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents                    90                       # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles                  2571                       # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles                   1789                       # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles                   88                       # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts             515149                       # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts              291                       # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts               165974                       # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts               83785                       # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts               838                       # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents                    95                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents            56                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect           370                       # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect         1149                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts                1519                       # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts               428170                       # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts               164921                       # Number of load instructions executed
+system.cpu0.iew.predictedTakenIncorrect           383                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect         1113                       # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts                1496                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts               428216                       # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts               164977                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts             1108                       # Number of squashed instructions skipped in execute
 system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu0.iew.exec_nop                        81545                       # number of nop insts executed
-system.cpu0.iew.exec_refs                      247840                       # number of memory reference insts executed
-system.cpu0.iew.exec_branches                   85100                       # Number of branches executed
-system.cpu0.iew.exec_stores                     82919                       # Number of stores executed
-system.cpu0.iew.exec_rate                    1.878895                       # Inst execution rate
-system.cpu0.iew.wb_sent                        427676                       # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count                       427325                       # cumulative count of insts written-back
-system.cpu0.iew.wb_producers                   253224                       # num instructions producing a value
-system.cpu0.iew.wb_consumers                   255650                       # num instructions consuming a value
+system.cpu0.iew.exec_nop                        81606                       # number of nop insts executed
+system.cpu0.iew.exec_refs                      247935                       # number of memory reference insts executed
+system.cpu0.iew.exec_branches                   85106                       # Number of branches executed
+system.cpu0.iew.exec_stores                     82958                       # Number of stores executed
+system.cpu0.iew.exec_rate                    1.879608                       # Inst execution rate
+system.cpu0.iew.wb_sent                        427739                       # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count                       427393                       # cumulative count of insts written-back
+system.cpu0.iew.wb_producers                   253334                       # num instructions producing a value
+system.cpu0.iew.wb_consumers                   255736                       # num instructions consuming a value
 system.cpu0.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate                      1.875186                       # insts written-back per cycle
-system.cpu0.iew.wb_fanout                    0.990510                       # average fanout of values written-back
+system.cpu0.iew.wb_rate                      1.875995                       # insts written-back per cycle
+system.cpu0.iew.wb_fanout                    0.990608                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts        501745                       # The number of committed instructions
-system.cpu0.commit.commitCommittedOps          501745                       # The number of committed instructions
-system.cpu0.commit.commitSquashedInsts          13260                       # The number of squashed insts skipped by commit
+system.cpu0.commit.commitCommittedInsts        502020                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps          502020                       # The number of committed instructions
+system.cpu0.commit.commitSquashedInsts          13085                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts             1314                       # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples       206418                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean     2.430723                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev     2.136815                       # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts             1290                       # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples       206533                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean     2.430701                       # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev     2.136521                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0        36760     17.81%     17.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1        84779     41.07%     58.88% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2         2446      1.18%     60.07% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3          715      0.35%     60.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4          578      0.28%     60.69% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5        80055     38.78%     99.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6          554      0.27%     99.74% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7          230      0.11%     99.85% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0        36757     17.80%     17.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1        84830     41.07%     58.87% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2         2489      1.21%     60.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3          701      0.34%     60.42% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4          579      0.28%     60.70% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5        80093     38.78%     99.48% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6          561      0.27%     99.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7          222      0.11%     99.85% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::8          301      0.15%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total       206418                       # Number of insts commited each cycle
-system.cpu0.commit.committedInsts              501745                       # Number of instructions committed
-system.cpu0.commit.committedOps                501745                       # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total       206533                       # Number of insts commited each cycle
+system.cpu0.commit.committedInsts              502020                       # Number of instructions committed
+system.cpu0.commit.committedOps                502020                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu0.commit.refs                        245582                       # Number of memory references committed
-system.cpu0.commit.loads                       163384                       # Number of loads committed
+system.cpu0.commit.refs                        245725                       # Number of memory references committed
+system.cpu0.commit.loads                       163479                       # Number of loads committed
 system.cpu0.commit.membars                         84                       # Number of memory barriers committed
-system.cpu0.commit.branches                     84086                       # Number of branches committed
+system.cpu0.commit.branches                     84133                       # Number of branches committed
 system.cpu0.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu0.commit.int_insts                   337930                       # Number of committed integer instructions.
+system.cpu0.commit.int_insts                   338110                       # Number of committed integer instructions.
 system.cpu0.commit.function_calls                 223                       # Number of function calls committed.
 system.cpu0.commit.bw_lim_events                  301                       # number cycles where commit BW limit reached
 system.cpu0.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads                      719961                       # The number of ROB reads
-system.cpu0.rob.rob_writes                    1032633                       # The number of ROB writes
-system.cpu0.timesIdled                            343                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles                          18877                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts                     420844                       # Number of Instructions Simulated
-system.cpu0.committedOps                       420844                       # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total               420844                       # Number of Instructions Simulated
-system.cpu0.cpi                              0.541493                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        0.541493                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              1.846747                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        1.846747                       # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads                  766075                       # number of integer regfile reads
-system.cpu0.int_regfile_writes                 345063                       # number of integer regfile writes
+system.cpu0.rob.rob_reads                      720176                       # The number of ROB reads
+system.cpu0.rob.rob_writes                    1032801                       # The number of ROB writes
+system.cpu0.timesIdled                            336                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles                          18735                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts                     421071                       # Number of Instructions Simulated
+system.cpu0.committedOps                       421071                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total               421071                       # Number of Instructions Simulated
+system.cpu0.cpi                              0.541054                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                        0.541054                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              1.848246                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        1.848246                       # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads                  766308                       # number of integer regfile reads
+system.cpu0.int_regfile_writes                 345106                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                      192                       # number of floating regfile reads
-system.cpu0.misc_regfile_reads                 249668                       # number of misc regfile reads
+system.cpu0.misc_regfile_reads                 249733                       # number of misc regfile reads
 system.cpu0.misc_regfile_writes                   564                       # number of misc regfile writes
-system.cpu0.icache.replacements                   308                       # number of replacements
-system.cpu0.icache.tagsinuse               248.197747                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                    5361                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                   601                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                  8.920133                       # Average number of references to valid blocks.
+system.cpu0.icache.replacements                   302                       # number of replacements
+system.cpu0.icache.tagsinuse               247.706871                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                    5276                       # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs                   594                       # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs                  8.882155                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   248.197747                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.484761                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.484761                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst         5361                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total           5361                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst         5361                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total            5361                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst         5361                       # number of overall hits
-system.cpu0.icache.overall_hits::total           5361                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst          761                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total          761                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst          761                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total           761                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst          761                       # number of overall misses
-system.cpu0.icache.overall_misses::total          761                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     29540500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total     29540500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst     29540500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total     29540500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst     29540500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total     29540500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst         6122                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total         6122                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst         6122                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total         6122                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst         6122                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total         6122                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.124306                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.124306                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.124306                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.124306                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.124306                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.124306                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38818.002628                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38818.002628                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38818.002628                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38818.002628                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38818.002628                       # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst   247.706871                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.483802                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.483802                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst         5276                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           5276                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         5276                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            5276                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         5276                       # number of overall hits
+system.cpu0.icache.overall_hits::total           5276                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          760                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          760                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          760                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           760                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          760                       # number of overall misses
+system.cpu0.icache.overall_misses::total          760                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     29374500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     29374500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     29374500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     29374500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     29374500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     29374500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         6036                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         6036                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         6036                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         6036                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         6036                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         6036                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.125911                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.125911                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.125911                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.125911                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.125911                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.125911                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38650.657895                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38650.657895                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38650.657895                       # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38650.657895                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38650.657895                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38650.657895                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs        13500                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -375,476 +374,476 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs        13500
 system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          159                       # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total          159                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst          159                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total          159                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst          159                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total          159                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          602                       # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total          602                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst          602                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total          602                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst          602                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total          602                       # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22436000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total     22436000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total     22436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22436000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total     22436000                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.098334                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     0.098334                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.098334                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     0.098334                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37269.102990                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37269.102990                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 37269.102990                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          165                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          165                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          165                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          165                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          165                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          165                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          595                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          595                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          595                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          595                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          595                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          595                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     22317000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     22317000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     22317000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     22317000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     22317000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     22317000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.098575                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.098575                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.098575                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total     0.098575                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.098575                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total     0.098575                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37507.563025                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37507.563025                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37507.563025                       # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 37507.563025                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37507.563025                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 37507.563025                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     2                       # number of replacements
-system.cpu0.dcache.tagsinuse               144.386808                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                  165433                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               144.389455                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                  165484                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                973.135294                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                973.435294                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   144.386808                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.282005                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.282005                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        83919                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          83919                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data        81593                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total         81593                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data           18                       # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data       165512                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total          165512                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data       165512                       # number of overall hits
-system.cpu0.dcache.overall_hits::total         165512                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data          525                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total          525                       # number of ReadReq misses
+system.cpu0.dcache.occ_blocks::cpu0.data   144.389455                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.282011                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.282011                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        83924                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          83924                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        81641                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         81641                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           17                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             17                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       165565                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          165565                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       165565                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         165565                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          532                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          532                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          563                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total          563                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data           24                       # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total           24                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data         1088                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total          1088                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data         1088                       # number of overall misses
-system.cpu0.dcache.overall_misses::total         1088                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16325500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total     16325500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     28838494                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total     28838494                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       480000                       # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total       480000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data     45163994                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total     45163994                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data     45163994                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total     45163994                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        84444                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        84444                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data        82156                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total        82156                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_misses::cpu0.data           25                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           25                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1095                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1095                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1095                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1095                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     16935000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     16935000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     28694494                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     28694494                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       516500                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       516500                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     45629494                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     45629494                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     45629494                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     45629494                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        84456                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        84456                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        82204                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        82204                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data       166600                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total       166600                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data       166600                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total       166600                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006217                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.006217                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006853                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total     0.006853                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.571429                       # miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_miss_rate::total     0.571429                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006531                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     0.006531                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006531                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     0.006531                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31096.190476                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31096.190476                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 51222.902309                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 51222.902309                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        20000                       # average SwapReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency::total        20000                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 41511.023897                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41511.023897                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 41511.023897                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs       119500                       # number of cycles access was blocked
+system.cpu0.dcache.demand_accesses::cpu0.data       166660                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       166660                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       166660                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       166660                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006299                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.006299                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006849                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total     0.006849                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.595238                       # miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::total     0.595238                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006570                       # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total     0.006570                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006570                       # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total     0.006570                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31832.706767                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 31832.706767                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50967.129663                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 50967.129663                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data        20660                       # average SwapReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::total        20660                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41670.770776                       # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 41670.770776                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41670.770776                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 41670.770776                       # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs       112000                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               18                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs  6638.888889                       # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs  6222.222222                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          345                       # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total          345                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          392                       # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total          392                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data          737                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total          737                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data          737                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total          737                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          180                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total          180                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          171                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total          171                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           24                       # number of SwapReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses::total           24                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data          351                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data          351                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total          351                       # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5693511                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5693511                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6731000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6731000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       405000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency::total       405000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12424511                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total     12424511                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12424511                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total     12424511                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002132                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002132                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002081                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002081                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.571429                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.571429                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     0.002107                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002107                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     0.002107                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 31630.616667                       # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 31630.616667                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39362.573099                       # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39362.573099                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        16875                       # average SwapReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        16875                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35397.467236                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35397.467236                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          351                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          351                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          394                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          394                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          745                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          745                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          745                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          745                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          181                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          181                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          169                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          169                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           25                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           25                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          350                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          350                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          350                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5844010                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5844010                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6652500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6652500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       438500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       438500                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     12496510                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     12496510                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     12496510                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     12496510                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002143                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.002143                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002056                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.002056                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.595238                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::total     0.595238                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002100                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total     0.002100                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002100                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total     0.002100                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 32287.348066                       # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 32287.348066                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39363.905325                       # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39363.905325                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data        17540                       # average SwapReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total        17540                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 35704.314286                       # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 35704.314286                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 35704.314286                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 35704.314286                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          191339                       # number of cpu cycles simulated
+system.cpu1.numCycles                          191317                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                   49631                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted             46572                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect              1528                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups                42950                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                   41997                       # Number of BTB hits
+system.cpu1.BPredUnit.lookups                   53059                       # Number of BP lookups
+system.cpu1.BPredUnit.condPredicted             50011                       # Number of conditional branches predicted
+system.cpu1.BPredUnit.condIncorrect              1521                       # Number of conditional branches incorrect
+system.cpu1.BPredUnit.BTBLookups                46382                       # Number of BTB lookups
+system.cpu1.BPredUnit.BTBHits                   45427                       # Number of BTB hits
 system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                     805                       # Number of times the RAS was used to get a target.
+system.cpu1.BPredUnit.usedRAS                     803                       # Number of times the RAS was used to get a target.
 system.cpu1.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu1.fetch.icacheStallCycles             33375                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts                        271825                       # Number of instructions fetch has processed
-system.cpu1.fetch.Branches                      49631                       # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches             42802                       # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles                        98758                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles                   4453                       # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles                 42292                       # Number of cycles fetch has spent blocked
+system.cpu1.fetch.icacheStallCycles             31318                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts                        294530                       # Number of instructions fetch has processed
+system.cpu1.fetch.Branches                      53059                       # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches             46230                       # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles                       104588                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles                   4407                       # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles                 38684                       # Number of cycles fetch has spent blocked
 system.cpu1.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.NoActiveThreadStallCycles         6725                       # Number of stall cycles due to no active thread to fetch from
+system.cpu1.fetch.NoActiveThreadStallCycles         6733                       # Number of stall cycles due to no active thread to fetch from
 system.cpu1.fetch.PendingTrapStallCycles         1070                       # Number of stall cycles due to pending traps
-system.cpu1.fetch.CacheLines                    23889                       # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples            185079                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean             1.468697                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev            2.066601                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines                    21833                       # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes                  319                       # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples            185209                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean             1.590257                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev            2.119058                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0                   86321     46.64%     46.64% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1                   51121     27.62%     74.26% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2                    7925      4.28%     78.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3                    3336      1.80%     80.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4                     734      0.40%     80.74% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5                   30013     16.22%     96.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6                    1151      0.62%     97.58% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7                     885      0.48%     98.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8                    3593      1.94%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0                   80621     43.53%     43.53% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1                   53529     28.90%     72.43% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2                    6903      3.73%     76.16% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3                    3276      1.77%     77.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4                     732      0.40%     78.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5                   34514     18.64%     96.96% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6                    1160      0.63%     97.58% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7                     883      0.48%     98.06% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8                    3591      1.94%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu1.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total              185079                       # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate                 0.259388                       # Number of branch fetches per cycle
-system.cpu1.fetch.rate                       1.420646                       # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles                   40472                       # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles                37211                       # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles                    91012                       # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles                 6805                       # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles                  2854                       # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts                267804                       # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles                  2854                       # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles                   41302                       # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles                  21637                       # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles         14674                       # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles                    84497                       # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles                13390                       # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts                265308                       # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents                    16                       # Number of times rename has blocked due to IQ full
+system.cpu1.fetch.rateDist::total              185209                       # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate                 0.277336                       # Number of branch fetches per cycle
+system.cpu1.fetch.rate                       1.539487                       # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles                   37437                       # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles                34588                       # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles                    97784                       # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles                 5856                       # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles                  2811                       # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts                290465                       # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles                  2811                       # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles                   38251                       # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles                  18737                       # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles         14962                       # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles                    92242                       # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles                11473                       # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts                288015                       # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents                    15                       # Number of times rename has blocked due to IQ full
 system.cpu1.rename.LSQFullEvents                   60                       # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands             184298                       # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups               499771                       # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups          499771                       # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps               168579                       # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps                   15719                       # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts              1236                       # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts          1367                       # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts                    16177                       # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads               72909                       # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores              33507                       # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads            35450                       # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores           28267                       # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded                    217311                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded               8226                       # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued                   220400                       # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued              173                       # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined          13138                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined        12222                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved           799                       # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples       185079                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean        1.190843                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev       1.296813                       # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands             201252                       # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups               549512                       # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups          549512                       # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps               185544                       # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps                   15708                       # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts              1231                       # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts          1359                       # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts                    14237                       # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads               80834                       # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores              37999                       # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads            38862                       # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores           32764                       # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded                    237666                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded               7151                       # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued                   239902                       # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued              128                       # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined          12973                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined        11962                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved           719                       # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples       185209                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean        1.295304                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev       1.311031                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0              84217     45.50%     45.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1              27917     15.08%     60.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2              33688     18.20%     78.79% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3              34243     18.50%     97.29% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4               3324      1.80%     99.09% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5               1232      0.67%     99.75% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6                345      0.19%     99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7                 52      0.03%     99.97% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0              78322     42.29%     42.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1              24974     13.48%     55.77% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2              38132     20.59%     76.36% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3              38761     20.93%     97.29% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4               3339      1.80%     99.09% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5               1231      0.66%     99.76% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6                341      0.18%     99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7                 48      0.03%     99.97% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::8                 61      0.03%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu1.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total         185079                       # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total         185209                       # Number of insts issued each cycle
 system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu                     21      6.60%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.60% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead                    87     27.36%     33.96% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite                  210     66.04%    100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu                     21      6.44%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv                      0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt                     0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift                   0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%      6.44% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead                    95     29.14%     35.58% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite                  210     64.42%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu1.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu               108844     49.38%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.38% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead               78735     35.72%     85.11% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite              32821     14.89%    100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu               116849     48.71%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv                    0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead               85748     35.74%     84.45% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite              37305     15.55%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total                220400                       # Type of FU issued
-system.cpu1.iq.rate                          1.151882                       # Inst issue rate
-system.cpu1.iq.fu_busy_cnt                        318                       # FU busy when requested
-system.cpu1.iq.fu_busy_rate                  0.001443                       # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads            626370                       # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes           238714                       # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses       218326                       # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total                239902                       # Type of FU issued
+system.cpu1.iq.rate                          1.253950                       # Inst issue rate
+system.cpu1.iq.fu_busy_cnt                        326                       # FU busy when requested
+system.cpu1.iq.fu_busy_rate                  0.001359                       # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads            665467                       # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes           257831                       # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses       237819                       # Number of integer instruction queue wakeup accesses
 system.cpu1.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu1.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu1.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses                220718                       # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses                240228                       # Number of integer alu accesses
 system.cpu1.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads           28122                       # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads           32613                       # Number of loads that had data forwarded from stores
 system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads         2824                       # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads         2758                       # Number of loads squashed
 system.cpu1.iew.lsq.thread0.ignoredResponses            8                       # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation           39                       # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores         1558                       # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation           41                       # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores         1567                       # Number of stores squashed
 system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu1.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu1.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles                  2854                       # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles                   2376                       # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles                   88                       # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts             261974                       # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts              434                       # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts                72909                       # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts               33507                       # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts              1131                       # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents                    89                       # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles                  2811                       # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles                   2340                       # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles                  107                       # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts             284663                       # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts              401                       # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts                80834                       # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts               37999                       # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts              1126                       # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents                   105                       # Number of times the IQ has become full, causing a stall
 system.cpu1.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents            39                       # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect           510                       # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect         1187                       # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts                1697                       # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts               219051                       # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts                71704                       # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts             1349                       # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents            41                       # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect           509                       # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect         1185                       # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts                1694                       # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts               238552                       # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts                79712                       # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts             1350                       # Number of squashed instructions skipped in execute
 system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu1.iew.exec_nop                        36437                       # number of nop insts executed
-system.cpu1.iew.exec_refs                      104435                       # number of memory reference insts executed
-system.cpu1.iew.exec_branches                   45735                       # Number of branches executed
-system.cpu1.iew.exec_stores                     32731                       # Number of stores executed
-system.cpu1.iew.exec_rate                    1.144832                       # Inst execution rate
-system.cpu1.iew.wb_sent                        218612                       # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count                       218326                       # cumulative count of insts written-back
-system.cpu1.iew.wb_producers                   121254                       # num instructions producing a value
-system.cpu1.iew.wb_consumers                   126110                       # num instructions consuming a value
+system.cpu1.iew.exec_nop                        39846                       # number of nop insts executed
+system.cpu1.iew.exec_refs                      116931                       # number of memory reference insts executed
+system.cpu1.iew.exec_branches                   49232                       # Number of branches executed
+system.cpu1.iew.exec_stores                     37219                       # Number of stores executed
+system.cpu1.iew.exec_rate                    1.246894                       # Inst execution rate
+system.cpu1.iew.wb_sent                        238105                       # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count                       237819                       # cumulative count of insts written-back
+system.cpu1.iew.wb_producers                   133762                       # num instructions producing a value
+system.cpu1.iew.wb_consumers                   138617                       # num instructions consuming a value
 system.cpu1.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate                      1.141043                       # insts written-back per cycle
-system.cpu1.iew.wb_fanout                    0.961494                       # average fanout of values written-back
+system.cpu1.iew.wb_rate                      1.243063                       # insts written-back per cycle
+system.cpu1.iew.wb_fanout                    0.964975                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts        246738                       # The number of committed instructions
-system.cpu1.commit.commitCommittedOps          246738                       # The number of committed instructions
-system.cpu1.commit.commitSquashedInsts          15223                       # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls           7427                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts             1528                       # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples       175501                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean     1.405907                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev     1.932846                       # Number of insts commited each cycle
+system.cpu1.commit.commitCommittedInsts        269706                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps          269706                       # The number of committed instructions
+system.cpu1.commit.commitSquashedInsts          14936                       # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls           6432                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts             1521                       # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples       175666                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean     1.535334                       # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev     1.989786                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0        84843     48.34%     48.34% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1        43671     24.88%     73.23% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2         6232      3.55%     76.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3         8331      4.75%     81.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4         1551      0.88%     82.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5        28453     16.21%     98.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6          613      0.35%     98.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7          993      0.57%     99.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0        78046     44.43%     44.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1        47129     26.83%     71.26% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2         6230      3.55%     74.80% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3         7351      4.18%     78.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4         1552      0.88%     79.87% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5        32915     18.74%     98.61% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6          634      0.36%     98.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7          995      0.57%     99.54% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::8          814      0.46%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total       175501                       # Number of insts commited each cycle
-system.cpu1.commit.committedInsts              246738                       # Number of instructions committed
-system.cpu1.commit.committedOps                246738                       # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total       175666                       # Number of insts commited each cycle
+system.cpu1.commit.committedInsts              269706                       # Number of instructions committed
+system.cpu1.commit.committedOps                269706                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu1.commit.refs                        102034                       # Number of memory references committed
-system.cpu1.commit.loads                        70085                       # Number of loads committed
-system.cpu1.commit.membars                       6711                       # Number of memory barriers committed
-system.cpu1.commit.branches                     44619                       # Number of branches committed
+system.cpu1.commit.refs                        114508                       # Number of memory references committed
+system.cpu1.commit.loads                        78076                       # Number of loads committed
+system.cpu1.commit.membars                       5720                       # Number of memory barriers committed
+system.cpu1.commit.branches                     48115                       # Number of branches committed
 system.cpu1.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu1.commit.int_insts                   168775                       # Number of committed integer instructions.
+system.cpu1.commit.int_insts                   184747                       # Number of committed integer instructions.
 system.cpu1.commit.function_calls                 322                       # Number of function calls committed.
 system.cpu1.commit.bw_lim_events                  814                       # number cycles where commit BW limit reached
 system.cpu1.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads                      436061                       # The number of ROB reads
-system.cpu1.rob.rob_writes                     526790                       # The number of ROB writes
+system.cpu1.rob.rob_reads                      458907                       # The number of ROB reads
+system.cpu1.rob.rob_writes                     572109                       # The number of ROB writes
 system.cpu1.timesIdled                            250                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles                           6260                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles                       36543                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                     204620                       # Number of Instructions Simulated
-system.cpu1.committedOps                       204620                       # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total               204620                       # Number of Instructions Simulated
-system.cpu1.cpi                              0.935094                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        0.935094                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              1.069411                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        1.069411                       # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads                  373202                       # number of integer regfile reads
-system.cpu1.int_regfile_writes                 174771                       # number of integer regfile writes
+system.cpu1.idleCycles                           6108                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles                       36503                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts                     225079                       # Number of Instructions Simulated
+system.cpu1.committedOps                       225079                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total               225079                       # Number of Instructions Simulated
+system.cpu1.cpi                              0.849999                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        0.849999                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              1.176472                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        1.176472                       # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads                  410678                       # number of integer regfile reads
+system.cpu1.int_regfile_writes                 191757                       # number of integer regfile writes
 system.cpu1.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu1.misc_regfile_reads                 106146                       # number of misc regfile reads
+system.cpu1.misc_regfile_reads                 118640                       # number of misc regfile reads
 system.cpu1.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu1.icache.replacements                   322                       # number of replacements
-system.cpu1.icache.tagsinuse                90.902674                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                   23372                       # Total number of references to valid blocks.
+system.cpu1.icache.tagsinuse                90.918932                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                   21316                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   436                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 53.605505                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 48.889908                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst    90.902674                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.177544                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.177544                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst        23372                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total          23372                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst        23372                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total           23372                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst        23372                       # number of overall hits
-system.cpu1.icache.overall_hits::total          23372                       # number of overall hits
+system.cpu1.icache.occ_blocks::cpu1.inst    90.918932                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.177576                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.177576                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst        21316                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          21316                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        21316                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           21316                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        21316                       # number of overall hits
+system.cpu1.icache.overall_hits::total          21316                       # number of overall hits
 system.cpu1.icache.ReadReq_misses::cpu1.inst          517                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total          517                       # number of ReadReq misses
 system.cpu1.icache.demand_misses::cpu1.inst          517                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total           517                       # number of demand (read+write) misses
 system.cpu1.icache.overall_misses::cpu1.inst          517                       # number of overall misses
 system.cpu1.icache.overall_misses::total          517                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11874500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total     11874500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst     11874500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total     11874500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst     11874500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total     11874500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst        23889                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total        23889                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst        23889                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total        23889                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst        23889                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total        23889                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.021642                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total     0.021642                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst     0.021642                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     0.021642                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst     0.021642                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     0.021642                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22968.085106                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 22968.085106                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 22968.085106                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22968.085106                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 22968.085106                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst     11871000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total     11871000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst     11871000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total     11871000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst     11871000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total     11871000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        21833                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        21833                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        21833                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        21833                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        21833                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        21833                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.023680                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total     0.023680                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.023680                       # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total     0.023680                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.023680                       # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total     0.023680                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22961.315280                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 22961.315280                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22961.315280                       # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 22961.315280                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22961.315280                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 22961.315280                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs        32000                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -865,94 +864,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst          436
 system.cpu1.icache.demand_mshr_misses::total          436                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.overall_mshr_misses::cpu1.inst          436                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_misses::total          436                       # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8863000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total      8863000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8863000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total      8863000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8863000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total      8863000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.018251                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     0.018251                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018251                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     0.018251                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20327.981651                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20327.981651                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 20327.981651                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      8857500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      8857500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      8857500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      8857500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      8857500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      8857500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.019970                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.019970                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.019970                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total     0.019970                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.019970                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total     0.019970                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20315.366972                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 20315.366972                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 20315.366972                       # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 20315.366972                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 20315.366972                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 20315.366972                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     0                       # number of replacements
-system.cpu1.dcache.tagsinuse                27.508331                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                   38240                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs               1318.620690                       # Average number of references to valid blocks.
+system.cpu1.dcache.tagsinuse                27.526466                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                   42609                       # Total number of references to valid blocks.
+system.cpu1.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
+system.cpu1.dcache.avg_refs               1521.750000                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data    27.508331                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.053727                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.053727                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::cpu1.data        43171                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total          43171                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data        31745                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total         31745                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data           15                       # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data        74916                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total           74916                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data        74916                       # number of overall hits
-system.cpu1.dcache.overall_hits::total          74916                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data          395                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total          395                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data          134                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total          134                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data           55                       # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data          529                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total           529                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data          529                       # number of overall misses
-system.cpu1.dcache.overall_misses::total          529                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     11922500                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total     11922500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3308000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total      3308000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1319000                       # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total      1319000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data     15230500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total     15230500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data     15230500                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total     15230500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data        43566                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total        43566                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data        31879                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total        31879                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data        75445                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total        75445                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data        75445                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total        75445                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009067                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total     0.009067                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.004203                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total     0.004203                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.785714                       # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total     0.785714                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007012                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     0.007012                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007012                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     0.007012                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 30183.544304                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 30183.544304                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24686.567164                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 24686.567164                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23981.818182                       # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 23981.818182                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 28791.115312                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28791.115312                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 28791.115312                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    27.526466                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.053763                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.053763                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        46637                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          46637                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        36226                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         36226                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        82863                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           82863                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        82863                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          82863                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          446                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          446                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          140                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           52                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          586                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           586                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          586                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          586                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     12735500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total     12735500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      3574500                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      3574500                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1329500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total      1329500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     16310000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     16310000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     16310000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     16310000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        47083                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        47083                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        36366                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        36366                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           66                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        83449                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        83449                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        83449                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        83449                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.009473                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total     0.009473                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003850                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total     0.003850                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.787879                       # miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::total     0.787879                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007022                       # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total     0.007022                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007022                       # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total     0.007022                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 28554.932735                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 28554.932735                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25532.142857                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25532.142857                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 25567.307692                       # average SwapReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::total 25567.307692                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27832.764505                       # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 27832.764505                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27832.764505                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 27832.764505                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -961,366 +960,366 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          229                       # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total          229                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          286                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          286                       # number of ReadReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           34                       # number of WriteReq MSHR hits
 system.cpu1.dcache.WriteReq_mshr_hits::total           34                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data          263                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total          263                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data          263                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total          263                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          166                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total          166                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          100                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total          100                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           55                       # number of SwapReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          320                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          320                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          320                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          320                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          160                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          160                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
 system.cpu1.dcache.demand_mshr_misses::cpu1.data          266                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.demand_mshr_misses::total          266                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.overall_mshr_misses::cpu1.data          266                       # number of overall MSHR misses
 system.cpu1.dcache.overall_mshr_misses::total          266                       # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3273504                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3273504                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1639000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1639000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1148500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1148500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4912504                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total      4912504                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4912504                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total      4912504                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003810                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003810                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.003137                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.003137                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.785714                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     0.003526                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003526                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     0.003526                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19719.903614                       # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19719.903614                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data        16390                       # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total        16390                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20881.818182                       # average SwapReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20881.818182                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18468.060150                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18468.060150                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3164503                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3164503                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1890000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1890000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data      1168500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total      1168500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      5054503                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      5054503                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      5054503                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      5054503                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003398                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.003398                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002915                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.002915                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.787879                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total     0.787879                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003188                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total     0.003188                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003188                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total     0.003188                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 19778.143750                       # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 19778.143750                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17830.188679                       # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17830.188679                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 22471.153846                       # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 22471.153846                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19001.890977                       # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19001.890977                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19001.890977                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19001.890977                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          191032                       # number of cpu cycles simulated
+system.cpu2.numCycles                          191010                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.BPredUnit.lookups                   57390                       # Number of BP lookups
-system.cpu2.BPredUnit.condPredicted             54193                       # Number of conditional branches predicted
-system.cpu2.BPredUnit.condIncorrect              1550                       # Number of conditional branches incorrect
-system.cpu2.BPredUnit.BTBLookups                50681                       # Number of BTB lookups
-system.cpu2.BPredUnit.BTBHits                   49645                       # Number of BTB hits
+system.cpu2.BPredUnit.lookups                   57179                       # Number of BP lookups
+system.cpu2.BPredUnit.condPredicted             53988                       # Number of conditional branches predicted
+system.cpu2.BPredUnit.condIncorrect              1553                       # Number of conditional branches incorrect
+system.cpu2.BPredUnit.BTBLookups                50487                       # Number of BTB lookups
+system.cpu2.BPredUnit.BTBHits                   49441                       # Number of BTB hits
 system.cpu2.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.BPredUnit.usedRAS                     804                       # Number of times the RAS was used to get a target.
+system.cpu2.BPredUnit.usedRAS                     815                       # Number of times the RAS was used to get a target.
 system.cpu2.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu2.fetch.icacheStallCycles             29539                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts                        321276                       # Number of instructions fetch has processed
-system.cpu2.fetch.Branches                      57390                       # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches             50449                       # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles                       112230                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles                   4473                       # Number of cycles fetch has spent squashing
-system.cpu2.fetch.BlockedCycles                 35583                       # Number of cycles fetch has spent blocked
+system.cpu2.fetch.icacheStallCycles             29527                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts                        320031                       # Number of instructions fetch has processed
+system.cpu2.fetch.Branches                      57179                       # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches             50256                       # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles                       111848                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles                   4474                       # Number of cycles fetch has spent squashing
+system.cpu2.fetch.BlockedCycles                 35937                       # Number of cycles fetch has spent blocked
 system.cpu2.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.NoActiveThreadStallCycles         6761                       # Number of stall cycles due to no active thread to fetch from
+system.cpu2.fetch.NoActiveThreadStallCycles         6751                       # Number of stall cycles due to no active thread to fetch from
 system.cpu2.fetch.PendingTrapStallCycles         1077                       # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines                    20533                       # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes                  334                       # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples            188044                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean             1.708515                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev            2.158633                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.CacheLines                    20539                       # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes                  333                       # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples            187993                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean             1.702356                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev            2.156955                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0                   75814     40.32%     40.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1                   56962     30.29%     70.61% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2                    6138      3.26%     73.87% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3                    3348      1.78%     75.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4                     769      0.41%     76.06% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5                   39287     20.89%     96.95% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6                    1207      0.64%     97.60% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7                     911      0.48%     98.08% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8                    3608      1.92%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0                   76145     40.50%     40.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1                   56782     30.20%     70.71% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2                    6165      3.28%     73.99% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3                    3347      1.78%     75.77% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4                     731      0.39%     76.16% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5                   39077     20.79%     96.94% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6                    1243      0.66%     97.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7                     913      0.49%     98.09% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8                    3590      1.91%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu2.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total              188044                       # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate                 0.300421                       # Number of branch fetches per cycle
-system.cpu2.fetch.rate                       1.681792                       # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles                   35225                       # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles                31967                       # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles                   106013                       # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles                 5229                       # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles                  2849                       # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts                316907                       # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles                  2849                       # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles                   36004                       # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles                  16323                       # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles         14784                       # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles                   101094                       # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles                10229                       # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts                314547                       # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents                    23                       # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LSQFullEvents                   56                       # Number of times rename has blocked due to LSQ full
-system.cpu2.rename.RenamedOperands             220052                       # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups               605102                       # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups          605102                       # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps               204228                       # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps                   15824                       # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts              1236                       # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts          1356                       # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts                    12873                       # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads               89800                       # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores              42907                       # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads            42940                       # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores           37601                       # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded                    260749                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded               6485                       # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued                   262481                       # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued              146                       # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined          13131                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined        11780                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved           687                       # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples       188044                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean        1.395849                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev       1.314415                       # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total              187993                       # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate                 0.299351                       # Number of branch fetches per cycle
+system.cpu2.fetch.rate                       1.675467                       # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles                   35252                       # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles                32290                       # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles                   105597                       # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles                 5255                       # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles                  2848                       # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts                315625                       # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles                  2848                       # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles                   36036                       # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles                  16472                       # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles         14955                       # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles                   100655                       # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles                10276                       # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts                313299                       # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents                    22                       # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LSQFullEvents                   57                       # Number of times rename has blocked due to LSQ full
+system.cpu2.rename.RenamedOperands             219155                       # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups               602465                       # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups          602465                       # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps               203359                       # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps                   15796                       # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts              1243                       # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts          1365                       # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts                    12944                       # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads               89370                       # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores              42679                       # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads            42734                       # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores           37374                       # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded                    259618                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded               6531                       # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued                   261379                       # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued              134                       # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined          13068                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined        11786                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved           697                       # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples       187993                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean        1.390366                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev       1.314588                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0              73292     38.98%     38.98% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1              23055     12.26%     51.24% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2              43065     22.90%     74.14% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3              43582     23.18%     97.31% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4               3340      1.78%     99.09% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5               1248      0.66%     99.75% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6                346      0.18%     99.94% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0              73641     39.17%     39.17% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1              23139     12.31%     51.48% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2              42800     22.77%     74.25% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3              43353     23.06%     97.31% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4               3352      1.78%     99.09% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5               1252      0.67%     99.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6                341      0.18%     99.94% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu2.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total         188044                       # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total         187993                       # Number of insts issued each cycle
 system.cpu2.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu                     21      6.65%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.65% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead                    85     26.90%     33.54% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite                  210     66.46%    100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu                     21      6.71%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult                     0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv                      0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult                   0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt                   0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd                     0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc                  0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu                     0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp                     0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt                     0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc                 0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift                   0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt                    0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv                0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc               0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult               0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc            0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt               0      0.00%      6.71% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead                    82     26.20%     32.91% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite                  210     67.09%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu2.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu               126143     48.06%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.06% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead               94161     35.87%     83.93% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite              42177     16.07%    100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu               125670     48.08%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult                   0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv                    0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult                 0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt                 0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd                   0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc                0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu                   0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp                   0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt                   0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc               0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift                 0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt                  0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult             0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.08% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead               93767     35.87%     83.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite              41942     16.05%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu2.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total                262481                       # Type of FU issued
-system.cpu2.iq.rate                          1.374016                       # Inst issue rate
-system.cpu2.iq.fu_busy_cnt                        316                       # FU busy when requested
-system.cpu2.iq.fu_busy_rate                  0.001204                       # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads            713468                       # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes           280402                       # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses       260315                       # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total                261379                       # Type of FU issued
+system.cpu2.iq.rate                          1.368405                       # Inst issue rate
+system.cpu2.iq.fu_busy_cnt                        313                       # FU busy when requested
+system.cpu2.iq.fu_busy_rate                  0.001197                       # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads            711198                       # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes           279252                       # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses       259224                       # Number of integer instruction queue wakeup accesses
 system.cpu2.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu2.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu2.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses                262797                       # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses                261692                       # Number of integer alu accesses
 system.cpu2.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads           37443                       # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads           37218                       # Number of loads that had data forwarded from stores
 system.cpu2.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads         2702                       # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads         2690                       # Number of loads squashed
 system.cpu2.iew.lsq.thread0.ignoredResponses            6                       # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation           37                       # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores         1644                       # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation           35                       # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores         1641                       # Number of stores squashed
 system.cpu2.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu2.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu2.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu2.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu2.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles                  2849                       # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles                   1860                       # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles                   77                       # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts             311245                       # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts              407                       # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts                89800                       # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts               42907                       # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts              1163                       # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents                    74                       # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles                  2848                       # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles                   1926                       # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles                   75                       # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts             309970                       # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts              424                       # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts                89370                       # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts               42679                       # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts              1173                       # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents                    72                       # Number of times the IQ has become full, causing a stall
 system.cpu2.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents            37                       # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect           516                       # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect         1201                       # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts                1717                       # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts               261072                       # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts                88760                       # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts             1409                       # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents            35                       # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect           514                       # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect         1208                       # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts                1722                       # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts               259980                       # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts                88335                       # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts             1399                       # Number of squashed instructions skipped in execute
 system.cpu2.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu2.iew.exec_nop                        44011                       # number of nop insts executed
-system.cpu2.iew.exec_refs                      130847                       # number of memory reference insts executed
-system.cpu2.iew.exec_branches                   53503                       # Number of branches executed
-system.cpu2.iew.exec_stores                     42087                       # Number of stores executed
-system.cpu2.iew.exec_rate                    1.366640                       # Inst execution rate
-system.cpu2.iew.wb_sent                        260613                       # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count                       260315                       # cumulative count of insts written-back
-system.cpu2.iew.wb_producers                   147697                       # num instructions producing a value
-system.cpu2.iew.wb_consumers                   152590                       # num instructions consuming a value
+system.cpu2.iew.exec_nop                        43821                       # number of nop insts executed
+system.cpu2.iew.exec_refs                      130189                       # number of memory reference insts executed
+system.cpu2.iew.exec_branches                   53302                       # Number of branches executed
+system.cpu2.iew.exec_stores                     41854                       # Number of stores executed
+system.cpu2.iew.exec_rate                    1.361081                       # Inst execution rate
+system.cpu2.iew.wb_sent                        259524                       # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count                       259224                       # cumulative count of insts written-back
+system.cpu2.iew.wb_producers                   147020                       # num instructions producing a value
+system.cpu2.iew.wb_consumers                   151915                       # num instructions consuming a value
 system.cpu2.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate                      1.362677                       # insts written-back per cycle
-system.cpu2.iew.wb_fanout                    0.967934                       # average fanout of values written-back
+system.cpu2.iew.wb_rate                      1.357123                       # insts written-back per cycle
+system.cpu2.iew.wb_fanout                    0.967778                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitCommittedInsts        296145                       # The number of committed instructions
-system.cpu2.commit.commitCommittedOps          296145                       # The number of committed instructions
-system.cpu2.commit.commitSquashedInsts          15092                       # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls           5798                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts             1550                       # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples       178435                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean     1.659680                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev     2.032759                       # Number of insts commited each cycle
+system.cpu2.commit.commitCommittedInsts        294930                       # The number of committed instructions
+system.cpu2.commit.commitCommittedOps          294930                       # The number of committed instructions
+system.cpu2.commit.commitSquashedInsts          15032                       # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls           5834                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts             1553                       # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples       178395                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean     1.653241                       # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev     2.030877                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0        72400     40.57%     40.57% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1        51371     28.79%     69.36% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2         6245      3.50%     72.86% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3         6660      3.73%     76.60% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4         1539      0.86%     77.46% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5        37793     21.18%     98.64% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6          621      0.35%     98.99% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7          991      0.56%     99.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0        72759     40.79%     40.79% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1        51159     28.68%     69.46% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2         6241      3.50%     72.96% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3         6697      3.75%     76.72% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4         1549      0.87%     77.58% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5        37557     21.05%     98.64% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6          629      0.35%     98.99% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7          989      0.55%     99.54% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::8          815      0.46%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total       178435                       # Number of insts commited each cycle
-system.cpu2.commit.committedInsts              296145                       # Number of instructions committed
-system.cpu2.commit.committedOps                296145                       # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total       178395                       # Number of insts commited each cycle
+system.cpu2.commit.committedInsts              294930                       # Number of instructions committed
+system.cpu2.commit.committedOps                294930                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu2.commit.refs                        128361                       # Number of memory references committed
-system.cpu2.commit.loads                        87098                       # Number of loads committed
-system.cpu2.commit.membars                       5084                       # Number of memory barriers committed
-system.cpu2.commit.branches                     52312                       # Number of branches committed
+system.cpu2.commit.refs                        127718                       # Number of memory references committed
+system.cpu2.commit.loads                        86680                       # Number of loads committed
+system.cpu2.commit.membars                       5119                       # Number of memory barriers committed
+system.cpu2.commit.branches                     52122                       # Number of branches committed
 system.cpu2.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu2.commit.int_insts                   202794                       # Number of committed integer instructions.
+system.cpu2.commit.int_insts                   201960                       # Number of committed integer instructions.
 system.cpu2.commit.function_calls                 322                       # Number of function calls committed.
 system.cpu2.commit.bw_lim_events                  815                       # number cycles where commit BW limit reached
 system.cpu2.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads                      488270                       # The number of ROB reads
-system.cpu2.rob.rob_writes                     625337                       # The number of ROB writes
-system.cpu2.timesIdled                            230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles                           2988                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu2.quiesceCycles                       36850                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts                     247959                       # Number of Instructions Simulated
-system.cpu2.committedOps                       247959                       # Number of Ops (including micro ops) Simulated
-system.cpu2.committedInsts_total               247959                       # Number of Instructions Simulated
-system.cpu2.cpi                              0.770418                       # CPI: Cycles Per Instruction
-system.cpu2.cpi_total                        0.770418                       # CPI: Total CPI of All Threads
-system.cpu2.ipc                              1.297997                       # IPC: Instructions Per Cycle
-system.cpu2.ipc_total                        1.297997                       # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads                  452595                       # number of integer regfile reads
-system.cpu2.int_regfile_writes                 210629                       # number of integer regfile writes
+system.cpu2.rob.rob_reads                      486955                       # The number of ROB reads
+system.cpu2.rob.rob_writes                     622786                       # The number of ROB writes
+system.cpu2.timesIdled                            227                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles                           3017                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.quiesceCycles                       36810                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.committedInsts                     246900                       # Number of Instructions Simulated
+system.cpu2.committedOps                       246900                       # Number of Ops (including micro ops) Simulated
+system.cpu2.committedInsts_total               246900                       # Number of Instructions Simulated
+system.cpu2.cpi                              0.773633                       # CPI: Cycles Per Instruction
+system.cpu2.cpi_total                        0.773633                       # CPI: Total CPI of All Threads
+system.cpu2.ipc                              1.292602                       # IPC: Instructions Per Cycle
+system.cpu2.ipc_total                        1.292602                       # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads                  450556                       # number of integer regfile reads
+system.cpu2.int_regfile_writes                 209704                       # number of integer regfile writes
 system.cpu2.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu2.misc_regfile_reads                 132559                       # number of misc regfile reads
+system.cpu2.misc_regfile_reads                 131893                       # number of misc regfile reads
 system.cpu2.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu2.icache.replacements                   322                       # number of replacements
-system.cpu2.icache.tagsinuse                84.182173                       # Cycle average of tags in use
-system.cpu2.icache.total_refs                   20037                       # Total number of references to valid blocks.
+system.cpu2.icache.tagsinuse                84.177245                       # Cycle average of tags in use
+system.cpu2.icache.total_refs                   20042                       # Total number of references to valid blocks.
 system.cpu2.icache.sampled_refs                   438                       # Sample count of references to valid blocks.
-system.cpu2.icache.avg_refs                 45.746575                       # Average number of references to valid blocks.
+system.cpu2.icache.avg_refs                 45.757991                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst    84.182173                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.164418                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.164418                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits::cpu2.inst        20037                       # number of ReadReq hits
-system.cpu2.icache.ReadReq_hits::total          20037                       # number of ReadReq hits
-system.cpu2.icache.demand_hits::cpu2.inst        20037                       # number of demand (read+write) hits
-system.cpu2.icache.demand_hits::total           20037                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits::cpu2.inst        20037                       # number of overall hits
-system.cpu2.icache.overall_hits::total          20037                       # number of overall hits
-system.cpu2.icache.ReadReq_misses::cpu2.inst          496                       # number of ReadReq misses
-system.cpu2.icache.ReadReq_misses::total          496                       # number of ReadReq misses
-system.cpu2.icache.demand_misses::cpu2.inst          496                       # number of demand (read+write) misses
-system.cpu2.icache.demand_misses::total           496                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses::cpu2.inst          496                       # number of overall misses
-system.cpu2.icache.overall_misses::total          496                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7608500                       # number of ReadReq miss cycles
-system.cpu2.icache.ReadReq_miss_latency::total      7608500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency::cpu2.inst      7608500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.demand_miss_latency::total      7608500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency::cpu2.inst      7608500                       # number of overall miss cycles
-system.cpu2.icache.overall_miss_latency::total      7608500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses::cpu2.inst        20533                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.ReadReq_accesses::total        20533                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses::cpu2.inst        20533                       # number of demand (read+write) accesses
-system.cpu2.icache.demand_accesses::total        20533                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses::cpu2.inst        20533                       # number of overall (read+write) accesses
-system.cpu2.icache.overall_accesses::total        20533                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024156                       # miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_miss_rate::total     0.024156                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024156                       # miss rate for demand accesses
-system.cpu2.icache.demand_miss_rate::total     0.024156                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024156                       # miss rate for overall accesses
-system.cpu2.icache.overall_miss_rate::total     0.024156                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15339.717742                       # average ReadReq miss latency
-system.cpu2.icache.ReadReq_avg_miss_latency::total 15339.717742                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
-system.cpu2.icache.demand_avg_miss_latency::total 15339.717742                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15339.717742                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 15339.717742                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    84.177245                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.164409                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.164409                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst        20042                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          20042                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        20042                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           20042                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        20042                       # number of overall hits
+system.cpu2.icache.overall_hits::total          20042                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          497                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          497                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          497                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           497                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          497                       # number of overall misses
+system.cpu2.icache.overall_misses::total          497                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      7614500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      7614500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      7614500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      7614500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      7614500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      7614500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        20539                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        20539                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        20539                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        20539                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        20539                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        20539                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.024198                       # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total     0.024198                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.024198                       # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total     0.024198                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.024198                       # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total     0.024198                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15320.925553                       # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 15320.925553                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15320.925553                       # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 15320.925553                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15320.925553                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 15320.925553                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1329,106 +1328,106 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           58                       # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total           58                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst           58                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total           58                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst           58                       # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total           58                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           59                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           59                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           59                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           59                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           59                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           59                       # number of overall MSHR hits
 system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          438                       # number of ReadReq MSHR misses
 system.cpu2.icache.ReadReq_mshr_misses::total          438                       # number of ReadReq MSHR misses
 system.cpu2.icache.demand_mshr_misses::cpu2.inst          438                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.demand_mshr_misses::total          438                       # number of demand (read+write) MSHR misses
 system.cpu2.icache.overall_mshr_misses::cpu2.inst          438                       # number of overall MSHR misses
 system.cpu2.icache.overall_mshr_misses::total          438                       # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5673500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total      5673500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5673500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total      5673500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5673500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total      5673500                       # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021332                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total     0.021332                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021332                       # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total     0.021332                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12953.196347                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12953.196347                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 12953.196347                       # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      5672000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      5672000                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      5672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      5672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      5672000                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      5672000                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.021325                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total     0.021325                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.021325                       # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total     0.021325                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.021325                       # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total     0.021325                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12949.771689                       # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12949.771689                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12949.771689                       # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 12949.771689                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12949.771689                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 12949.771689                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     0                       # number of replacements
-system.cpu2.dcache.tagsinuse                24.868946                       # Cycle average of tags in use
-system.cpu2.dcache.total_refs                   47444                       # Total number of references to valid blocks.
+system.cpu2.dcache.tagsinuse                24.875323                       # Cycle average of tags in use
+system.cpu2.dcache.total_refs                   47216                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu2.dcache.avg_refs               1694.428571                       # Average number of references to valid blocks.
+system.cpu2.dcache.avg_refs               1686.285714                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data    24.868946                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.048572                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.048572                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits::cpu2.data        50906                       # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total          50906                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data        41055                       # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total         41055                       # number of WriteReq hits
+system.cpu2.dcache.occ_blocks::cpu2.data    24.875323                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.048585                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.048585                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        50709                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          50709                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        40830                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         40830                       # number of WriteReq hits
 system.cpu2.dcache.SwapReq_hits::cpu2.data           12                       # number of SwapReq hits
 system.cpu2.dcache.SwapReq_hits::total             12                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data        91961                       # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total           91961                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data        91961                       # number of overall hits
-system.cpu2.dcache.overall_hits::total          91961                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data          392                       # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total          392                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data          140                       # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data           56                       # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data          532                       # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total           532                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data          532                       # number of overall misses
-system.cpu2.dcache.overall_misses::total          532                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10132000                       # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total     10132000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3391500                       # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total      3391500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1227500                       # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total      1227500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data     13523500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total     13523500                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data     13523500                       # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total     13523500                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data        51298                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total        51298                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data        41195                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total        41195                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total           68                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data        92493                       # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total        92493                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data        92493                       # number of overall (read+write) accesses
-system.cpu2.dcache.overall_accesses::total        92493                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007642                       # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total     0.007642                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003398                       # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total     0.003398                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.823529                       # miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_miss_rate::total     0.823529                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005752                       # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total     0.005752                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005752                       # miss rate for overall accesses
-system.cpu2.dcache.overall_miss_rate::total     0.005752                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 25846.938776                       # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 25846.938776                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data        24225                       # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total        24225                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21919.642857                       # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 21919.642857                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 25420.112782                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25420.112782                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 25420.112782                       # average overall miss latency
+system.cpu2.dcache.demand_hits::cpu2.data        91539                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           91539                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        91539                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          91539                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          389                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          389                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          139                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          139                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           57                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          528                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           528                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          528                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          528                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10172000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total     10172000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      3390500                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      3390500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1234500                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total      1234500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     13562500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     13562500                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     13562500                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     13562500                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        51098                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        51098                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        40969                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        40969                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        92067                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        92067                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        92067                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        92067                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.007613                       # miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_miss_rate::total     0.007613                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003393                       # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::total     0.003393                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.826087                       # miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::total     0.826087                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.005735                       # miss rate for demand accesses
+system.cpu2.dcache.demand_miss_rate::total     0.005735                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.005735                       # miss rate for overall accesses
+system.cpu2.dcache.overall_miss_rate::total     0.005735                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 26149.100257                       # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 26149.100257                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24392.086331                       # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 24392.086331                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21657.894737                       # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 21657.894737                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 25686.553030                       # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 25686.553030                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 25686.553030                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 25686.553030                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1437,366 +1436,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu2.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          241                       # number of ReadReq MSHR hits
-system.cpu2.dcache.ReadReq_mshr_hits::total          241                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          234                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          234                       # number of ReadReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           35                       # number of WriteReq MSHR hits
 system.cpu2.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits::cpu2.data          276                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.demand_mshr_hits::total          276                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits::cpu2.data          276                       # number of overall MSHR hits
-system.cpu2.dcache.overall_mshr_hits::total          276                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          151                       # number of ReadReq MSHR misses
-system.cpu2.dcache.ReadReq_mshr_misses::total          151                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses::total          105                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           56                       # number of SwapReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses::cpu2.data          256                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.demand_mshr_misses::total          256                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses::cpu2.data          256                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_misses::total          256                       # number of overall MSHR misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2456507                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2456507                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1732500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1732500                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1052000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1052000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4189007                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency::total      4189007                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4189007                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency::total      4189007                       # number of overall MSHR miss cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.002944                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002549                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002549                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.823529                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.823529                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for demand accesses
-system.cpu2.dcache.demand_mshr_miss_rate::total     0.002768                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002768                       # mshr miss rate for overall accesses
-system.cpu2.dcache.overall_mshr_miss_rate::total     0.002768                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16268.258278                       # average ReadReq mshr miss latency
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16268.258278                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data        16500                       # average WriteReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total        16500                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18785.714286                       # average SwapReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18785.714286                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16363.308594                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16363.308594                       # average overall mshr miss latency
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          269                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          269                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          269                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          269                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          155                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          104                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          104                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           57                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           57                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          259                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          259                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          259                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          259                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2539505                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2539505                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1736500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1736500                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1057000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1057000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4276005                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      4276005                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4276005                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      4276005                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003033                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.ReadReq_mshr_miss_rate::total     0.003033                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002539                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::total     0.002539                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.826087                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::total     0.826087                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.002813                       # mshr miss rate for demand accesses
+system.cpu2.dcache.demand_mshr_miss_rate::total     0.002813                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.002813                       # mshr miss rate for overall accesses
+system.cpu2.dcache.overall_mshr_miss_rate::total     0.002813                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16383.903226                       # average ReadReq mshr miss latency
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16383.903226                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16697.115385                       # average WriteReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16697.115385                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18543.859649                       # average SwapReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18543.859649                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16509.671815                       # average overall mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16509.671815                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16509.671815                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16509.671815                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          190752                       # number of cpu cycles simulated
+system.cpu3.numCycles                          190730                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.BPredUnit.lookups                   53643                       # Number of BP lookups
-system.cpu3.BPredUnit.condPredicted             50394                       # Number of conditional branches predicted
-system.cpu3.BPredUnit.condIncorrect              1547                       # Number of conditional branches incorrect
-system.cpu3.BPredUnit.BTBLookups                46912                       # Number of BTB lookups
-system.cpu3.BPredUnit.BTBHits                   45897                       # Number of BTB hits
+system.cpu3.BPredUnit.lookups                   50135                       # Number of BP lookups
+system.cpu3.BPredUnit.condPredicted             46886                       # Number of conditional branches predicted
+system.cpu3.BPredUnit.condIncorrect              1563                       # Number of conditional branches incorrect
+system.cpu3.BPredUnit.BTBLookups                43380                       # Number of BTB lookups
+system.cpu3.BPredUnit.BTBHits                   42368                       # Number of BTB hits
 system.cpu3.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.BPredUnit.usedRAS                     838                       # Number of times the RAS was used to get a target.
+system.cpu3.BPredUnit.usedRAS                     844                       # Number of times the RAS was used to get a target.
 system.cpu3.BPredUnit.RASInCorrect                232                       # Number of incorrect RAS predictions.
-system.cpu3.fetch.icacheStallCycles             31381                       # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts                        296607                       # Number of instructions fetch has processed
-system.cpu3.fetch.Branches                      53643                       # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches             46735                       # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles                       105748                       # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles                   4379                       # Number of cycles fetch has spent squashing
-system.cpu3.fetch.BlockedCycles                 39758                       # Number of cycles fetch has spent blocked
+system.cpu3.fetch.icacheStallCycles             33373                       # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts                        273510                       # Number of instructions fetch has processed
+system.cpu3.fetch.Branches                      50135                       # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches             43212                       # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles                        99693                       # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles                   4441                       # Number of cycles fetch has spent squashing
+system.cpu3.fetch.BlockedCycles                 43703                       # Number of cycles fetch has spent blocked
 system.cpu3.fetch.MiscStallCycles                   5                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.NoActiveThreadStallCycles         6743                       # Number of stall cycles due to no active thread to fetch from
+system.cpu3.fetch.NoActiveThreadStallCycles         6715                       # Number of stall cycles due to no active thread to fetch from
 system.cpu3.fetch.PendingTrapStallCycles         1058                       # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines                    22503                       # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes                  317                       # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples            187456                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean             1.582275                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev            2.112091                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.CacheLines                    24485                       # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes                  321                       # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples            187356                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean             1.459841                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev            2.059659                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0                   81708     43.59%     43.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1                   54260     28.95%     72.53% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2                    7170      3.82%     76.36% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3                    3258      1.74%     78.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4                     706      0.38%     78.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5                   34710     18.52%     96.99% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6                    1204      0.64%     97.63% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7                     885      0.47%     98.10% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8                    3555      1.90%    100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0                   87663     46.79%     46.79% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1                   51707     27.60%     74.39% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2                    8154      4.35%     78.74% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3                    3276      1.75%     80.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4                     745      0.40%     80.89% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5                   30183     16.11%     97.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6                    1182      0.63%     97.63% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7                     888      0.47%     98.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8                    3558      1.90%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
 system.cpu3.fetch.rateDist::max_value               8                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total              187456                       # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate                 0.281219                       # Number of branch fetches per cycle
-system.cpu3.fetch.rate                       1.554935                       # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles                   37941                       # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles                35250                       # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles                    98653                       # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles                 6106                       # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles                  2763                       # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts                292333                       # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles                  2763                       # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles                   38724                       # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles                  18900                       # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles         15518                       # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles                    92845                       # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles                11963                       # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts                289904                       # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents                     5                       # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LSQFullEvents                   41                       # Number of times rename has blocked due to LSQ full
-system.cpu3.rename.RenamedOperands             201915                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups               552179                       # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups          552179                       # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps               186764                       # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps                   15151                       # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts              1285                       # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts          1418                       # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts                    14719                       # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads               81367                       # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores              38245                       # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads            39205                       # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores           32957                       # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded                    238924                       # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded               7473                       # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued                   241868                       # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued              117                       # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined          12521                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined        10991                       # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved           722                       # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples       187456                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean        1.290265                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev       1.307286                       # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total              187356                       # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate                 0.262858                       # Number of branch fetches per cycle
+system.cpu3.fetch.rate                       1.434017                       # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles                   40875                       # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles                38262                       # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles                    91696                       # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles                 6999                       # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles                  2809                       # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts                269218                       # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles                  2809                       # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles                   41677                       # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles                  21676                       # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles         15745                       # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles                    84975                       # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles                13759                       # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts                266737                       # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents                     9                       # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LSQFullEvents                   40                       # Number of times rename has blocked due to LSQ full
+system.cpu3.rename.RenamedOperands             184789                       # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups               501822                       # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups          501822                       # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps               169578                       # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps                   15211                       # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts              1292                       # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts          1426                       # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts                    16516                       # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads               73298                       # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores              33720                       # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads            35666                       # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores           28418                       # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded                    218299                       # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded               8477                       # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued                   222114                       # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued              113                       # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined          12726                       # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined        11163                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved           773                       # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples       187356                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean        1.185518                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev       1.293170                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0              79218     42.26%     42.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1              25849     13.79%     56.05% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2              38415     20.49%     76.54% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3              38999     20.80%     97.35% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4               3297      1.76%     99.10% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5               1241      0.66%     99.77% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6                322      0.17%     99.94% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7                 53      0.03%     99.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0              85320     45.54%     45.54% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1              28690     15.31%     60.85% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2              33902     18.09%     78.95% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3              34456     18.39%     97.34% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4               3309      1.77%     99.10% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5               1236      0.66%     99.76% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6                327      0.17%     99.94% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7                 54      0.03%     99.97% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::8                 62      0.03%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::max_value            8                       # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total         187456                       # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total         187356                       # Number of insts issued each cycle
 system.cpu3.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu                     22      7.19%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult                     0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv                      0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult                   0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift                   0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      7.19% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead                    74     24.18%     31.37% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite                  210     68.63%    100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu                     22      7.17%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult                     0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv                      0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult                   0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt                   0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd                     0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc                  0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu                     0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp                     0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt                     0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc                 0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift                   0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt                    0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv                0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc               0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult               0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc            0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt               0      0.00%      7.17% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead                    75     24.43%     31.60% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite                  210     68.40%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
 system.cpu3.iq.FU_type_0::No_OpClass                0      0.00%      0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu               117603     48.62%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     48.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead               86736     35.86%     84.48% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite              37529     15.52%    100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu               109540     49.32%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult                   0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv                    0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult                 0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt                 0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd                   0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc                0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu                   0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp                   0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt                   0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc               0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift                 0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt                  0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv              0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc             0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult             0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt             0      0.00%     49.32% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead               79567     35.82%     85.14% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite              33007     14.86%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
 system.cpu3.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total                241868                       # Type of FU issued
-system.cpu3.iq.rate                          1.267971                       # Inst issue rate
-system.cpu3.iq.fu_busy_cnt                        306                       # FU busy when requested
-system.cpu3.iq.fu_busy_rate                  0.001265                       # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads            671615                       # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes           258950                       # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses       239863                       # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total                222114                       # Type of FU issued
+system.cpu3.iq.rate                          1.164547                       # Inst issue rate
+system.cpu3.iq.fu_busy_cnt                        307                       # FU busy when requested
+system.cpu3.iq.fu_busy_rate                  0.001382                       # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads            632004                       # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes           239536                       # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses       220090                       # Number of integer instruction queue wakeup accesses
 system.cpu3.iq.fp_inst_queue_reads                  0                       # Number of floating instruction queue reads
 system.cpu3.iq.fp_inst_queue_writes                 0                       # Number of floating instruction queue writes
 system.cpu3.iq.fp_inst_queue_wakeup_accesses            0                       # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses                242174                       # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses                222421                       # Number of integer alu accesses
 system.cpu3.iq.fp_alu_accesses                      0                       # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads           32833                       # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads           28294                       # Number of loads that had data forwarded from stores
 system.cpu3.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads         2526                       # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads         2578                       # Number of loads squashed
 system.cpu3.iew.lsq.thread0.ignoredResponses            3                       # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation           32                       # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores         1583                       # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation           34                       # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores         1587                       # Number of stores squashed
 system.cpu3.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
 system.cpu3.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
 system.cpu3.iew.lsq.thread0.rescheduledLoads            0                       # Number of loads that were rescheduled
 system.cpu3.iew.lsq.thread0.cacheBlocked            0                       # Number of times an access to memory failed due to the cache being blocked
 system.cpu3.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles                  2763                       # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles                   1788                       # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles                   60                       # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts             286739                       # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts              413                       # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts                81367                       # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts               38245                       # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts              1210                       # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents                    58                       # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles                  2809                       # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles                   1854                       # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles                   59                       # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts             263586                       # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts              366                       # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts                73298                       # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts               33720                       # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts              1219                       # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents                    53                       # Number of times the IQ has become full, causing a stall
 system.cpu3.iew.iewLSQFullEvents                    0                       # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents            32                       # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect           503                       # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect         1210                       # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts                1713                       # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts               240581                       # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts                80413                       # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts             1287                       # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents            34                       # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect           509                       # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect         1217                       # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts                1726                       # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts               220807                       # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts                72290                       # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts             1307                       # Number of squashed instructions skipped in execute
 system.cpu3.iew.exec_swp                            0                       # number of swp insts executed
-system.cpu3.iew.exec_nop                        40342                       # number of nop insts executed
-system.cpu3.iew.exec_refs                      117868                       # number of memory reference insts executed
-system.cpu3.iew.exec_branches                   49825                       # Number of branches executed
-system.cpu3.iew.exec_stores                     37455                       # Number of stores executed
-system.cpu3.iew.exec_rate                    1.261224                       # Inst execution rate
-system.cpu3.iew.wb_sent                        240146                       # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count                       239863                       # cumulative count of insts written-back
-system.cpu3.iew.wb_producers                   134653                       # num instructions producing a value
-system.cpu3.iew.wb_consumers                   139524                       # num instructions consuming a value
+system.cpu3.iew.exec_nop                        36810                       # number of nop insts executed
+system.cpu3.iew.exec_refs                      105220                       # number of memory reference insts executed
+system.cpu3.iew.exec_branches                   46242                       # Number of branches executed
+system.cpu3.iew.exec_stores                     32930                       # Number of stores executed
+system.cpu3.iew.exec_rate                    1.157694                       # Inst execution rate
+system.cpu3.iew.wb_sent                        220376                       # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count                       220090                       # cumulative count of insts written-back
+system.cpu3.iew.wb_producers                   122048                       # num instructions producing a value
+system.cpu3.iew.wb_consumers                   126919                       # num instructions consuming a value
 system.cpu3.iew.wb_penalized                        0                       # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate                      1.257460                       # insts written-back per cycle
-system.cpu3.iew.wb_fanout                    0.965088                       # average fanout of values written-back
+system.cpu3.iew.wb_rate                      1.153935                       # insts written-back per cycle
+system.cpu3.iew.wb_fanout                    0.961621                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitCommittedInsts        272332                       # The number of committed instructions
-system.cpu3.commit.commitCommittedOps          272332                       # The number of committed instructions
-system.cpu3.commit.commitSquashedInsts          14381                       # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls           6751                       # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts             1547                       # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples       177951                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean     1.530376                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev     1.985731                       # Number of insts commited each cycle
+system.cpu3.commit.commitCommittedInsts        248929                       # The number of committed instructions
+system.cpu3.commit.commitCommittedOps          248929                       # The number of committed instructions
+system.cpu3.commit.commitSquashedInsts          14631                       # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls           7704                       # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts             1563                       # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples       177833                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean     1.399791                       # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev     1.928963                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0        79207     44.51%     44.51% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1        47739     26.83%     71.34% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2         6222      3.50%     74.83% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3         7617      4.28%     79.11% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4         1549      0.87%     79.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5        33224     18.67%     98.66% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6          582      0.33%     98.98% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7          998      0.56%     99.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0        86250     48.50%     48.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1        44177     24.84%     73.34% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2         6214      3.49%     76.84% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3         8561      4.81%     81.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4         1535      0.86%     82.51% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5        28697     16.14%     98.65% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6          590      0.33%     98.98% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7          996      0.56%     99.54% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::8          813      0.46%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total       177951                       # Number of insts commited each cycle
-system.cpu3.commit.committedInsts              272332                       # Number of instructions committed
-system.cpu3.commit.committedOps                272332                       # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total       177833                       # Number of insts commited each cycle
+system.cpu3.commit.committedInsts              248929                       # Number of instructions committed
+system.cpu3.commit.committedOps                248929                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
-system.cpu3.commit.refs                        115503                       # Number of memory references committed
-system.cpu3.commit.loads                        78841                       # Number of loads committed
-system.cpu3.commit.membars                       6036                       # Number of memory barriers committed
-system.cpu3.commit.branches                     48661                       # Number of branches committed
+system.cpu3.commit.refs                        102853                       # Number of memory references committed
+system.cpu3.commit.loads                        70720                       # Number of loads committed
+system.cpu3.commit.membars                       6986                       # Number of memory barriers committed
+system.cpu3.commit.branches                     45078                       # Number of branches committed
 system.cpu3.commit.fp_insts                         0                       # Number of committed floating point instructions.
-system.cpu3.commit.int_insts                   186284                       # Number of committed integer instructions.
+system.cpu3.commit.int_insts                   170050                       # Number of committed integer instructions.
 system.cpu3.commit.function_calls                 322                       # Number of function calls committed.
 system.cpu3.commit.bw_lim_events                  813                       # number cycles where commit BW limit reached
 system.cpu3.commit.bw_limited                       0                       # number of insts not committed due to BW limits
-system.cpu3.rob.rob_reads                      463264                       # The number of ROB reads
-system.cpu3.rob.rob_writes                     576197                       # The number of ROB writes
-system.cpu3.timesIdled                            226                       # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles                           3296                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles                       37130                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts                     226846                       # Number of Instructions Simulated
-system.cpu3.committedOps                       226846                       # Number of Ops (including micro ops) Simulated
-system.cpu3.committedInsts_total               226846                       # Number of Instructions Simulated
-system.cpu3.cpi                              0.840888                       # CPI: Cycles Per Instruction
-system.cpu3.cpi_total                        0.840888                       # CPI: Total CPI of All Threads
-system.cpu3.ipc                              1.189220                       # IPC: Instructions Per Cycle
-system.cpu3.ipc_total                        1.189220                       # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads                  413495                       # number of integer regfile reads
-system.cpu3.int_regfile_writes                 192863                       # number of integer regfile writes
+system.cpu3.rob.rob_reads                      439993                       # The number of ROB reads
+system.cpu3.rob.rob_writes                     529937                       # The number of ROB writes
+system.cpu3.timesIdled                            228                       # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles                           3374                       # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles                       37090                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts                     206079                       # Number of Instructions Simulated
+system.cpu3.committedOps                       206079                       # Number of Ops (including micro ops) Simulated
+system.cpu3.committedInsts_total               206079                       # Number of Instructions Simulated
+system.cpu3.cpi                              0.925519                       # CPI: Cycles Per Instruction
+system.cpu3.cpi_total                        0.925519                       # CPI: Total CPI of All Threads
+system.cpu3.ipc                              1.080475                       # IPC: Instructions Per Cycle
+system.cpu3.ipc_total                        1.080475                       # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads                  375615                       # number of integer regfile reads
+system.cpu3.int_regfile_writes                 175714                       # number of integer regfile writes
 system.cpu3.fp_regfile_writes                      64                       # number of floating regfile writes
-system.cpu3.misc_regfile_reads                 119579                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads                 106918                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                   646                       # number of misc regfile writes
 system.cpu3.icache.replacements                   323                       # number of replacements
-system.cpu3.icache.tagsinuse                88.254899                       # Cycle average of tags in use
-system.cpu3.icache.total_refs                   21999                       # Total number of references to valid blocks.
+system.cpu3.icache.tagsinuse                88.249587                       # Cycle average of tags in use
+system.cpu3.icache.total_refs                   23982                       # Total number of references to valid blocks.
 system.cpu3.icache.sampled_refs                   439                       # Sample count of references to valid blocks.
-system.cpu3.icache.avg_refs                 50.111617                       # Average number of references to valid blocks.
+system.cpu3.icache.avg_refs                 54.628702                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst    88.254899                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.172373                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.172373                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits::cpu3.inst        21999                       # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total          21999                       # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst        21999                       # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total           21999                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst        21999                       # number of overall hits
-system.cpu3.icache.overall_hits::total          21999                       # number of overall hits
-system.cpu3.icache.ReadReq_misses::cpu3.inst          504                       # number of ReadReq misses
-system.cpu3.icache.ReadReq_misses::total          504                       # number of ReadReq misses
-system.cpu3.icache.demand_misses::cpu3.inst          504                       # number of demand (read+write) misses
-system.cpu3.icache.demand_misses::total           504                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses::cpu3.inst          504                       # number of overall misses
-system.cpu3.icache.overall_misses::total          504                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7701000                       # number of ReadReq miss cycles
-system.cpu3.icache.ReadReq_miss_latency::total      7701000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency::cpu3.inst      7701000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.demand_miss_latency::total      7701000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency::cpu3.inst      7701000                       # number of overall miss cycles
-system.cpu3.icache.overall_miss_latency::total      7701000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses::cpu3.inst        22503                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.ReadReq_accesses::total        22503                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses::cpu3.inst        22503                       # number of demand (read+write) accesses
-system.cpu3.icache.demand_accesses::total        22503                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses::cpu3.inst        22503                       # number of overall (read+write) accesses
-system.cpu3.icache.overall_accesses::total        22503                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.022397                       # miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_miss_rate::total     0.022397                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate::cpu3.inst     0.022397                       # miss rate for demand accesses
-system.cpu3.icache.demand_miss_rate::total     0.022397                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate::cpu3.inst     0.022397                       # miss rate for overall accesses
-system.cpu3.icache.overall_miss_rate::total     0.022397                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15279.761905                       # average ReadReq miss latency
-system.cpu3.icache.ReadReq_avg_miss_latency::total 15279.761905                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
-system.cpu3.icache.demand_avg_miss_latency::total 15279.761905                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15279.761905                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency::total 15279.761905                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    88.249587                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.172362                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.172362                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst        23982                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          23982                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        23982                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           23982                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        23982                       # number of overall hits
+system.cpu3.icache.overall_hits::total          23982                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          503                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          503                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          503                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           503                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          503                       # number of overall misses
+system.cpu3.icache.overall_misses::total          503                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      7707000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      7707000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      7707000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      7707000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      7707000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      7707000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        24485                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        24485                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        24485                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        24485                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        24485                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        24485                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020543                       # miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_miss_rate::total     0.020543                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020543                       # miss rate for demand accesses
+system.cpu3.icache.demand_miss_rate::total     0.020543                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020543                       # miss rate for overall accesses
+system.cpu3.icache.overall_miss_rate::total     0.020543                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15322.067594                       # average ReadReq miss latency
+system.cpu3.icache.ReadReq_avg_miss_latency::total 15322.067594                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15322.067594                       # average overall miss latency
+system.cpu3.icache.demand_avg_miss_latency::total 15322.067594                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15322.067594                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::total 15322.067594                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1805,106 +1804,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           65                       # number of ReadReq MSHR hits
-system.cpu3.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits::cpu3.inst           65                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits::cpu3.inst           65                       # number of overall MSHR hits
-system.cpu3.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           64                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           64                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           64                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           64                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           64                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           64                       # number of overall MSHR hits
 system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          439                       # number of ReadReq MSHR misses
 system.cpu3.icache.ReadReq_mshr_misses::total          439                       # number of ReadReq MSHR misses
 system.cpu3.icache.demand_mshr_misses::cpu3.inst          439                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.demand_mshr_misses::total          439                       # number of demand (read+write) MSHR misses
 system.cpu3.icache.overall_mshr_misses::cpu3.inst          439                       # number of overall MSHR misses
 system.cpu3.icache.overall_mshr_misses::total          439                       # number of overall MSHR misses
-system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5678000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_latency::total      5678000                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5678000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency::total      5678000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5678000                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency::total      5678000                       # number of overall MSHR miss cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.019509                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for demand accesses
-system.cpu3.icache.demand_mshr_miss_rate::total     0.019509                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.019509                       # mshr miss rate for overall accesses
-system.cpu3.icache.overall_mshr_miss_rate::total     0.019509                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average ReadReq mshr miss latency
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12933.940774                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12933.940774                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency::total 12933.940774                       # average overall mshr miss latency
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      5684000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      5684000                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      5684000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      5684000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      5684000                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      5684000                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.017929                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.ReadReq_mshr_miss_rate::total     0.017929                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.017929                       # mshr miss rate for demand accesses
+system.cpu3.icache.demand_mshr_miss_rate::total     0.017929                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.017929                       # mshr miss rate for overall accesses
+system.cpu3.icache.overall_mshr_miss_rate::total     0.017929                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12947.608200                       # average ReadReq mshr miss latency
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12947.608200                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12947.608200                       # average overall mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::total 12947.608200                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12947.608200                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::total 12947.608200                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     0                       # number of replacements
-system.cpu3.dcache.tagsinuse                26.059158                       # Cycle average of tags in use
-system.cpu3.dcache.total_refs                   42792                       # Total number of references to valid blocks.
-system.cpu3.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
-system.cpu3.dcache.avg_refs               1528.285714                       # Average number of references to valid blocks.
+system.cpu3.dcache.tagsinuse                26.048284                       # Cycle average of tags in use
+system.cpu3.dcache.total_refs                   38388                       # Total number of references to valid blocks.
+system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
+system.cpu3.dcache.avg_refs               1323.724138                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data    26.059158                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.050897                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.050897                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits::cpu3.data        47204                       # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total          47204                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data        36453                       # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total         36453                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data        83657                       # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total           83657                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data        83657                       # number of overall hits
-system.cpu3.dcache.overall_hits::total          83657                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data          361                       # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total          361                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data          140                       # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total          140                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data          501                       # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total           501                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data          501                       # number of overall misses
-system.cpu3.dcache.overall_misses::total          501                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9450000                       # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total      9450000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3328500                       # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total      3328500                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1305500                       # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total      1305500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data     12778500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total     12778500                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data     12778500                       # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total     12778500                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data        47565                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total        47565                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data        36593                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total        36593                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data           69                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total           69                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data        84158                       # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total        84158                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses::cpu3.data        84158                       # number of overall (read+write) accesses
-system.cpu3.dcache.overall_accesses::total        84158                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.007590                       # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total     0.007590                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.003826                       # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_miss_rate::total     0.003826                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.797101                       # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total     0.797101                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate::cpu3.data     0.005953                       # miss rate for demand accesses
-system.cpu3.dcache.demand_miss_rate::total     0.005953                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate::cpu3.data     0.005953                       # miss rate for overall accesses
-system.cpu3.dcache.overall_miss_rate::total     0.005953                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 26177.285319                       # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 26177.285319                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        23775                       # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total        23775                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 23736.363636                       # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 23736.363636                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
-system.cpu3.dcache.demand_avg_miss_latency::total 25505.988024                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25505.988024                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 25505.988024                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    26.048284                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.050876                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.050876                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        43625                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          43625                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        31927                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         31927                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           16                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        75552                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           75552                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        75552                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          75552                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          356                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          356                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          134                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          134                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          490                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           490                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          490                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          490                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9997000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      9997000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      3151500                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      3151500                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1323000                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total      1323000                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     13148500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     13148500                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     13148500                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     13148500                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        43981                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        43981                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        32061                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        32061                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           72                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        76042                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        76042                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        76042                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        76042                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.008094                       # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total     0.008094                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004180                       # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total     0.004180                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.777778                       # miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::total     0.777778                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.006444                       # miss rate for demand accesses
+system.cpu3.dcache.demand_miss_rate::total     0.006444                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.006444                       # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total     0.006444                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 28081.460674                       # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 28081.460674                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23518.656716                       # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 23518.656716                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data        23625                       # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total        23625                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 26833.673469                       # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 26833.673469                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 26833.673469                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 26833.673469                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1913,81 +1912,81 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs          nan
 system.cpu3.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          206                       # number of ReadReq MSHR hits
-system.cpu3.dcache.ReadReq_mshr_hits::total          206                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           33                       # number of WriteReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits::total           33                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits::cpu3.data          239                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.demand_mshr_hits::total          239                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits::cpu3.data          239                       # number of overall MSHR hits
-system.cpu3.dcache.overall_mshr_hits::total          239                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          155                       # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total          107                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           55                       # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total           55                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data          262                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total          262                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data          262                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total          262                       # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2585504                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2585504                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1735000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1735000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1134500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1134500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4320504                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total      4320504                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4320504                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total      4320504                       # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003259                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003259                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.002924                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.002924                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.797101                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.797101                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total     0.003113                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003113                       # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total     0.003113                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16680.670968                       # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16680.670968                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16214.953271                       # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16214.953271                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20627.272727                       # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20627.272727                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16490.473282                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16490.473282                       # average overall mshr miss latency
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          195                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          195                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           32                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           32                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          227                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          227                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          227                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          227                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          161                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          161                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          102                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          263                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          263                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          263                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          263                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2771504                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2771504                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1583000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1583000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1148500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1148500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      4354504                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      4354504                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      4354504                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      4354504                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003661                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total     0.003661                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003181                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::total     0.003181                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.777778                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::total     0.777778                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.003459                       # mshr miss rate for demand accesses
+system.cpu3.dcache.demand_mshr_miss_rate::total     0.003459                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.003459                       # mshr miss rate for overall accesses
+system.cpu3.dcache.overall_mshr_miss_rate::total     0.003459                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17214.310559                       # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17214.310559                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15519.607843                       # average WriteReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15519.607843                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 20508.928571                       # average SwapReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 20508.928571                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16557.049430                       # average overall mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16557.049430                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16557.049430                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16557.049430                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       436.890326                       # Cycle average of tags in use
-system.l2c.total_refs                            1480                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                           538                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          2.750929                       # Average number of references to valid blocks.
+system.l2c.tagsinuse                       436.337885                       # Cycle average of tags in use
+system.l2c.total_refs                            1474                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                           537                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          2.744879                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks            0.838452                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           294.676580                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data            59.534459                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst            68.181124                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data             5.702984                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst             2.344879                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data             0.730463                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst             4.107761                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data             0.773625                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks            0.838584                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           294.109117                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            59.534191                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            68.191567                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             5.703860                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             2.346215                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.730565                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             4.110047                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.773739                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.000013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu0.inst            0.004496                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.004488                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.data            0.000908                       # Average percentage of cache occupancy
-system.l2c.occ_percent::cpu1.inst            0.001040                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.001041                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu1.data            0.000087                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu2.inst            0.000036                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu2.data            0.000011                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.inst            0.000063                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.data            0.000012                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.006666                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                239                       # number of ReadReq hits
+system.l2c.occ_percent::total                0.006658                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                233                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                350                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
@@ -1995,12 +1994,12 @@ system.l2c.ReadReq_hits::cpu2.inst                428                       # nu
 system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.inst                431                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1480                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1474                       # number of ReadReq hits
 system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
 system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 239                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 233                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.inst                 350                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
@@ -2008,8 +2007,8 @@ system.l2c.demand_hits::cpu2.inst                 428                       # nu
 system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.inst                 431                       # number of demand (read+write) hits
 system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1480                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                239                       # number of overall hits
+system.l2c.demand_hits::total                    1474                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                233                       # number of overall hits
 system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
 system.l2c.overall_hits::cpu1.inst                350                       # number of overall hits
 system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
@@ -2017,8 +2016,8 @@ system.l2c.overall_hits::cpu2.inst                428                       # nu
 system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
 system.l2c.overall_hits::cpu3.inst                431                       # number of overall hits
 system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
-system.l2c.overall_hits::total                   1480                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              363                       # number of ReadReq misses
+system.l2c.overall_hits::total                   1474                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst              362                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu0.data               74                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.inst               86                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
@@ -2026,18 +2025,18 @@ system.l2c.ReadReq_misses::cpu2.inst               10                       # nu
 system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu3.inst                8                       # number of ReadReq misses
 system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  550                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  549                       # number of ReadReq misses
 system.l2c.UpgradeReq_misses::cpu0.data            20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            15                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            21                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::cpu2.data            21                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                75                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            15                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                77                       # number of UpgradeReq misses
 system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               363                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               362                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu0.data               168                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.inst                86                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
@@ -2045,8 +2044,8 @@ system.l2c.demand_misses::cpu2.inst                10                       # nu
 system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.inst                 8                       # number of demand (read+write) misses
 system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   681                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              363                       # number of overall misses
+system.l2c.demand_misses::total                   680                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              362                       # number of overall misses
 system.l2c.overall_misses::cpu0.data              168                       # number of overall misses
 system.l2c.overall_misses::cpu1.inst               86                       # number of overall misses
 system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
@@ -2054,40 +2053,40 @@ system.l2c.overall_misses::cpu2.inst               10                       # nu
 system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
 system.l2c.overall_misses::cpu3.inst                8                       # number of overall misses
 system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  681                       # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.inst     19255500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data      4177000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.inst      4495500                       # number of ReadReq miss cycles
+system.l2c.overall_misses::total                  680                       # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0.inst     19202500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data      4170000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      4498000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu1.data       377500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.inst       449500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst       449000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu2.data        52500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.inst       388000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst       386000                       # number of ReadReq miss cycles
 system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total       29248000                       # number of ReadReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu0.data      5163500                       # number of ReadExReq miss cycles
+system.l2c.ReadReq_miss_latency::total       29188000                       # number of ReadReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      5156500                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu1.data       751000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu2.data       663000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_latency::cpu3.data       658499                       # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total      7235999                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu0.inst     19255500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu0.data      9340500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst      4495500                       # number of demand (read+write) miss cycles
+system.l2c.ReadExReq_miss_latency::total      7228999                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     19202500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data      9326500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      4498000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu1.data      1128500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst       449500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       449000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu2.data       715500                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst       388000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       386000                       # number of demand (read+write) miss cycles
 system.l2c.demand_miss_latency::cpu3.data       710999                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total        36483999                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu0.inst     19255500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu0.data      9340500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst      4495500                       # number of overall miss cycles
+system.l2c.demand_miss_latency::total        36416999                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     19202500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data      9326500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      4498000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu1.data      1128500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst       449500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       449000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu2.data       715500                       # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst       388000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       386000                       # number of overall miss cycles
 system.l2c.overall_miss_latency::cpu3.data       710999                       # number of overall miss cycles
-system.l2c.overall_miss_latency::total       36483999                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.inst            602                       # number of ReadReq accesses(hits+misses)
+system.l2c.overall_miss_latency::total       36416999                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst            595                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu0.data             79                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.inst            436                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
@@ -2095,20 +2094,20 @@ system.l2c.ReadReq_accesses::cpu2.inst            438                       # nu
 system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.inst            439                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               2030                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               2023                       # number of ReadReq accesses(hits+misses)
 system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu0.data           23                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           15                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           21                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::cpu2.data           21                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              78                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           15                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              80                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             602                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             595                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu0.data             173                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.inst             436                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
@@ -2116,8 +2115,8 @@ system.l2c.demand_accesses::cpu2.inst             438                       # nu
 system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.inst             439                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                2161                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            602                       # number of overall (read+write) accesses
+system.l2c.demand_accesses::total                2154                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            595                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu0.data            173                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.inst            436                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
@@ -2125,8 +2124,8 @@ system.l2c.overall_accesses::cpu2.inst            438                       # nu
 system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.inst            439                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               2161                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.602990                       # miss rate for ReadReq accesses
+system.l2c.overall_accesses::total               2154                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.608403                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu0.data      0.936709                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.inst      0.197248                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
@@ -2134,18 +2133,18 @@ system.l2c.ReadReq_miss_rate::cpu2.inst      0.022831                       # mi
 system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu3.inst      0.018223                       # miss rate for ReadReq accesses
 system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.270936                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.271379                       # miss rate for ReadReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu0.data     0.869565                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.961538                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.962500                       # miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.602990                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.608403                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu0.data       0.971098                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.inst       0.197248                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
@@ -2153,8 +2152,8 @@ system.l2c.demand_miss_rate::cpu2.inst       0.022831                       # mi
 system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.inst       0.018223                       # miss rate for demand accesses
 system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.315132                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.602990                       # miss rate for overall accesses
+system.l2c.demand_miss_rate::total           0.315692                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.608403                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu0.data      0.971098                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.inst      0.197248                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
@@ -2162,39 +2161,39 @@ system.l2c.overall_miss_rate::cpu2.inst      0.022831                       # mi
 system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.inst      0.018223                       # miss rate for overall accesses
 system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.315132                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.454545                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu0.data 56445.945946                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52273.255814                       # average ReadReq miss latency
+system.l2c.overall_miss_rate::total          0.315692                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53045.580110                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 56351.351351                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52302.325581                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu1.data 53928.571429                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.inst        44950                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst        44900                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu2.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48250                       # average ReadReq miss latency
 system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 53178.181818                       # average ReadReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54930.851064                       # average ReadExReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 53165.755920                       # average ReadReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 54856.382979                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu1.data 57769.230769                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu2.data        55250                       # average ReadExReq miss latency
 system.l2c.ReadExReq_avg_miss_latency::cpu3.data 54874.916667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 55236.633588                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 55183.198473                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 53045.580110                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 55514.880952                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52302.325581                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst        44900                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        48250                       # average overall miss latency
 system.l2c.demand_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 53574.154185                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 53045.454545                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.data 55598.214286                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 52273.255814                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 53554.410294                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 53045.580110                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 55514.880952                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52302.325581                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu1.data        56425                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst        44950                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst        44900                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu2.data 55038.461538                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst        48500                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        48250                       # average overall miss latency
 system.l2c.overall_avg_miss_latency::cpu3.data 54692.230769                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 53574.154185                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 53554.410294                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -2215,7 +2214,7 @@ system.l2c.overall_mshr_hits::cpu1.inst             2                       # nu
 system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::cpu3.inst             2                       # number of overall MSHR hits
 system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu0.inst          363                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst          362                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu0.data           74                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.inst           84                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
@@ -2223,18 +2222,18 @@ system.l2c.ReadReq_mshr_misses::cpu2.inst            5                       # n
 system.l2c.ReadReq_mshr_misses::cpu2.data            1                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu3.inst            6                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total             541                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             540                       # number of ReadReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu0.data           20                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data           15                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           21                       # number of UpgradeReq MSHR misses
 system.l2c.UpgradeReq_mshr_misses::cpu2.data           21                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data           19                       # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total           75                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           15                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           77                       # number of UpgradeReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu1.data           13                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu2.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
 system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses::cpu0.inst          363                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          362                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu0.data          168                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.inst           84                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu1.data           20                       # number of demand (read+write) MSHR misses
@@ -2242,8 +2241,8 @@ system.l2c.demand_mshr_misses::cpu2.inst            5                       # nu
 system.l2c.demand_mshr_misses::cpu2.data           13                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.inst            6                       # number of demand (read+write) MSHR misses
 system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total              672                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu0.inst          363                       # number of overall MSHR misses
+system.l2c.demand_mshr_misses::total              671                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          362                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu0.data          168                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.inst           84                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu1.data           20                       # number of overall MSHR misses
@@ -2251,45 +2250,45 @@ system.l2c.overall_mshr_misses::cpu2.inst            5                       # n
 system.l2c.overall_mshr_misses::cpu2.data           13                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.inst            6                       # number of overall MSHR misses
 system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total             672                       # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14840000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3282500                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3420000                       # number of ReadReq MSHR miss cycles
+system.l2c.overall_mshr_misses::total             671                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14801500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3274000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      3420500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu1.data       291500                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       200000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu2.data        40000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.inst       240000                       # number of ReadReq MSHR miss cycles
 system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total     22354000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     22307500                       # number of ReadReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       800000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       600000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       840000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       844000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       765000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total      3009000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4019000                       # number of ReadExReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       605000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      3089000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      4012500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       593500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       516500                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       511500                       # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total      5640500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst     14840000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data      7301500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst      3420000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      5634000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     14801500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data      7286500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      3420500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu1.data       885000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.inst       200000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu2.data       556500                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.inst       240000                       # number of demand (read+write) MSHR miss cycles
 system.l2c.demand_mshr_miss_latency::cpu3.data       551500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total     27994500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst     14840000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data      7301500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst      3420000                       # number of overall MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     27941500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     14801500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      7286500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      3420500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu1.data       885000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.inst       200000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu2.data       556500                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.inst       240000                       # number of overall MSHR miss cycles
 system.l2c.overall_mshr_miss_latency::cpu3.data       551500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total     27994500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for ReadReq accesses
+system.l2c.overall_mshr_miss_latency::total     27941500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.608403                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.936709                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.583333                       # mshr miss rate for ReadReq accesses
@@ -2297,18 +2296,18 @@ system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.011416
 system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.083333                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for ReadReq accesses
 system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.083333                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.266502                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total     0.266930                       # mshr miss rate for ReadReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.869565                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
 system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total     0.961538                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total     0.962500                       # mshr miss rate for UpgradeReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
 system.l2c.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.608403                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for demand accesses
@@ -2316,8 +2315,8 @@ system.l2c.demand_mshr_miss_rate::cpu2.inst     0.011416                       #
 system.l2c.demand_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for demand accesses
 system.l2c.demand_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      0.310967                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst     0.602990                       # mshr miss rate for overall accesses
+system.l2c.demand_mshr_miss_rate::total      0.311513                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.608403                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu0.data     0.971098                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.inst     0.192661                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for overall accesses
@@ -2325,44 +2324,44 @@ system.l2c.overall_mshr_miss_rate::cpu2.inst     0.011416
 system.l2c.overall_mshr_miss_rate::cpu2.data     0.541667                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.inst     0.013667                       # mshr miss rate for overall accesses
 system.l2c.overall_mshr_miss_rate::cpu3.data     0.541667                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     0.310967                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44358.108108                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average ReadReq mshr miss latency
+system.l2c.overall_mshr_miss_rate::total     0.311513                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40888.121547                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44243.243243                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40720.238095                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 41642.857143                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 41319.778189                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 41310.185185                       # average ReadReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40190.476190                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40263.157895                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total        40120                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42755.319149                       # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40333.333333                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40116.883117                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42686.170213                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 45653.846154                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43041.666667                       # average ReadExReq mshr miss latency
 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        42625                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 43057.251908                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43007.633588                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40888.121547                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 43372.023810                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40720.238095                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
 system.l2c.demand_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40881.542700                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43461.309524                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.285714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 41641.579732                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40888.121547                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 43372.023810                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40720.238095                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu1.data        44250                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.inst        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42807.692308                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_miss_latency::cpu3.data 42423.076923                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 41658.482143                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 41641.579732                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f048ede7efda19c5946d078ef6721b0336254ed0..85ad1df6b18758a9ab2be46d25164e94617811aa 100644 (file)
@@ -465,8 +465,8 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
-master=system.physmem.port[0]
+width=8
+master=system.physmem.port
 slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
@@ -487,7 +487,7 @@ block_size=64
 clock=1000
 header_cycles=1
 use_default_range=false
-width=64
+width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
index 4b3a2eb90a188d859bfa22a6ce146be22b1173ca..77c22c00828a0eea0d47ab4120fb7f60f6b31ac1 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun 28 2012 22:06:58
-gem5 started Jun 28 2012 22:54:10
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:36
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
@@ -79,4 +79,4 @@ Iteration 9 completed
 [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 87713500 because target called exit()
+Exiting @ tick 87707000 because target called exit()
index 382c1c71b8387cfb6c32cdbd7f002c992efa6e1d..a86401b307016b689146c0b9c35b5a925a2f4df8 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000088                       # Number of seconds simulated
-sim_ticks                                    87713500                       # Number of ticks simulated
-final_tick                                   87713500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                    87707000                       # Number of ticks simulated
+final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1588944                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1588869                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              205745598                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1148436                       # Number of bytes of host memory used
-host_seconds                                     0.43                       # Real time elapsed on the host
-sim_insts                                      677340                       # Number of instructions simulated
-sim_ops                                        677340                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1518076                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1518015                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              196560583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1157868                       # Number of bytes of host memory used
+host_seconds                                     0.45                       # Real time elapsed on the host
+sim_insts                                      677327                       # Number of instructions simulated
+sim_ops                                        677327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            18048                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             3968                       # Number of bytes read from this memory
@@ -34,85 +34,85 @@ system.physmem.num_reads::cpu2.data                13                       # Nu
 system.physmem.num_reads::cpu3.inst                 2                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                13                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   559                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst           205760801                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data           120391958                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            45238190                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data            14592965                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst             1459296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             9485427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1459296                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             9485427                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               407873360                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      205760801                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       45238190                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst        1459296                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1459296                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          253917584                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          205760801                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data          120391958                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           45238190                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data           14592965                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst            1459296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            9485427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1459296                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            9485427                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              407873360                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           205776050                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data           120400880                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            45241543                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data            14594046                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst             1459405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             9486130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             1459405                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             9486130                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               407903588                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      205776050                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       45241543                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst        1459405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        1459405                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          253936402                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          205776050                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data          120400880                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           45241543                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data           14594046                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst            1459405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            1459405                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            9486130                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              407903588                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
+system.cpu0.numCycles                          175415                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     175339                       # Number of instructions committed
-system.cpu0.committedOps                       175339                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               120388                       # Number of integer alu accesses
+system.cpu0.committedInsts                     175326                       # Number of instructions committed
+system.cpu0.committedOps                       175326                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               120376                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        28825                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      120388                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        28824                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      120376                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             349308                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            121996                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             349286                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            121983                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        82398                       # number of memory refs
-system.cpu0.num_load_insts                      54592                       # Number of load instructions
+system.cpu0.num_mem_refs                        82397                       # number of memory refs
+system.cpu0.num_load_insts                      54591                       # Number of load instructions
 system.cpu0.num_store_insts                     27806                       # Number of store instructions
 system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    175428                       # Number of busy cycles
+system.cpu0.num_busy_cycles                    175415                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.icache.replacements                   215                       # number of replacements
-system.cpu0.icache.tagsinuse               222.757301                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                  174934                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               222.772698                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  174921                       # Total number of references to valid blocks.
 system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                374.591006                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                374.563169                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   222.757301                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.435073                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.435073                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       174934                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         174934                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       174934                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          174934                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       174934                       # number of overall hits
-system.cpu0.icache.overall_hits::total         174934                       # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst   222.772698                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          174921                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       174921                       # number of overall hits
+system.cpu0.icache.overall_hits::total         174921                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
 system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
 system.cpu0.icache.overall_misses::total          467                       # number of overall misses
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       175401                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       175401                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       175401                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       175401                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       175401                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       175401                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002662                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total     0.002662                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002662                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     0.002662                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002662                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     0.002662                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       175388                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       175388                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       175388                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       175388                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       175388                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       175388                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002663                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total     0.002663                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002663                       # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total     0.002663                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002663                       # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total     0.002663                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -123,24 +123,24 @@ system.cpu0.icache.fast_writes                      0                       # nu
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     2                       # number of replacements
-system.cpu0.dcache.tagsinuse               150.735434                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                   81884                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               150.745494                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   81883                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                490.323353                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                490.317365                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   150.735434                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.294405                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.294405                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        54431                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          54431                       # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   150.745494                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.294425                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.294425                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        54430                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          54430                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total         27578                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           15                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        82009                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           82009                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        82009                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          82009                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        82008                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           82008                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        82008                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          82008                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          151                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          177                       # number of WriteReq misses
@@ -151,18 +151,18 @@ system.cpu0.dcache.demand_misses::cpu0.data          328                       #
 system.cpu0.dcache.demand_misses::total           328                       # number of demand (read+write) misses
 system.cpu0.dcache.overall_misses::cpu0.data          328                       # number of overall misses
 system.cpu0.dcache.overall_misses::total          328                       # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        54582                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        54582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        54581                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        54581                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data        27755                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total        27755                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        82337                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        82337                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        82337                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        82337                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002766                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.002766                       # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        82336                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        82336                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        82336                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        82336                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002767                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.002767                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006377                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.006377                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.642857                       # miss rate for SwapReq accesses
@@ -182,7 +182,7 @@ system.cpu0.dcache.cache_copies                     0                       # nu
 system.cpu0.dcache.writebacks::writebacks            1                       # number of writebacks
 system.cpu0.dcache.writebacks::total                1                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu1.numCycles                          173295                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                     167398                       # Number of instructions committed
@@ -200,19 +200,19 @@ system.cpu1.num_fp_register_writes                  0                       # nu
 system.cpu1.num_mem_refs                        53394                       # number of memory refs
 system.cpu1.num_load_insts                      40652                       # Number of load instructions
 system.cpu1.num_store_insts                     12742                       # Number of store instructions
-system.cpu1.num_idle_cycles               7886.574443                       # Number of idle cycles
-system.cpu1.num_busy_cycles              165421.425557                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.954494                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.045506                       # Percentage of idle cycles
+system.cpu1.num_idle_cycles               7873.724337                       # Number of idle cycles
+system.cpu1.num_busy_cycles              165421.275663                       # Number of busy cycles
+system.cpu1.not_idle_fraction                0.954565                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.045435                       # Percentage of idle cycles
 system.cpu1.icache.replacements                   278                       # number of replacements
-system.cpu1.icache.tagsinuse                76.746014                       # Cycle average of tags in use
+system.cpu1.icache.tagsinuse                76.751702                       # Cycle average of tags in use
 system.cpu1.icache.total_refs                  167072                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                466.681564                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst    76.746014                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.149895                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.149895                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::cpu1.inst    76.751702                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.149906                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.149906                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst       167072                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         167072                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       167072                       # number of demand (read+write) hits
@@ -247,14 +247,14 @@ system.cpu1.icache.fast_writes                      0                       # nu
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     0                       # number of replacements
-system.cpu1.dcache.tagsinuse                30.314752                       # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse                30.316999                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                   26731                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    26                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs               1028.115385                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data    30.314752                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.059208                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.059208                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::cpu1.data    30.316999                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.059213                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.059213                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data        40470                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          40470                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        12563                       # number of WriteReq hits
@@ -304,7 +304,7 @@ system.cpu1.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          173308                       # number of cpu cycles simulated
+system.cpu2.numCycles                          173295                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.committedInsts                     167334                       # Number of instructions committed
@@ -322,19 +322,19 @@ system.cpu2.num_fp_register_writes                  0                       # nu
 system.cpu2.num_mem_refs                        58537                       # number of memory refs
 system.cpu2.num_load_insts                      42362                       # Number of load instructions
 system.cpu2.num_store_insts                     16175                       # Number of store instructions
-system.cpu2.num_idle_cycles               7949.801380                       # Number of idle cycles
-system.cpu2.num_busy_cycles              165358.198620                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.954129                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.045871                       # Percentage of idle cycles
+system.cpu2.num_idle_cycles               7936.951217                       # Number of idle cycles
+system.cpu2.num_busy_cycles              165358.048783                       # Number of busy cycles
+system.cpu2.not_idle_fraction                0.954200                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.045800                       # Percentage of idle cycles
 system.cpu2.icache.replacements                   278                       # number of replacements
-system.cpu2.icache.tagsinuse                74.775474                       # Cycle average of tags in use
+system.cpu2.icache.tagsinuse                74.781015                       # Cycle average of tags in use
 system.cpu2.icache.total_refs                  167008                       # Total number of references to valid blocks.
 system.cpu2.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
 system.cpu2.icache.avg_refs                466.502793                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst    74.775474                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.146046                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.146046                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::cpu2.inst    74.781015                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.146057                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.146057                       # Average percentage of cache occupancy
 system.cpu2.icache.ReadReq_hits::cpu2.inst       167008                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         167008                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       167008                       # number of demand (read+write) hits
@@ -369,14 +369,14 @@ system.cpu2.icache.fast_writes                      0                       # nu
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     0                       # number of replacements
-system.cpu2.dcache.tagsinuse                29.603311                       # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse                29.605505                       # Cycle average of tags in use
 system.cpu2.dcache.total_refs                   33613                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    26                       # Sample count of references to valid blocks.
 system.cpu2.dcache.avg_refs               1292.807692                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data    29.603311                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.057819                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.057819                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::cpu2.data    29.605505                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.057823                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.057823                       # Average percentage of cache occupancy
 system.cpu2.dcache.ReadReq_hits::cpu2.data        42194                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          42194                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        15998                       # number of WriteReq hits
@@ -426,7 +426,7 @@ system.cpu2.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          173307                       # number of cpu cycles simulated
+system.cpu3.numCycles                          173294                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu3.committedInsts                     167269                       # Number of instructions committed
@@ -444,19 +444,19 @@ system.cpu3.num_fp_register_writes                  0                       # nu
 system.cpu3.num_mem_refs                        55900                       # number of memory refs
 system.cpu3.num_load_insts                      41466                       # Number of load instructions
 system.cpu3.num_store_insts                     14434                       # Number of store instructions
-system.cpu3.num_idle_cycles               8013.969997                       # Number of idle cycles
-system.cpu3.num_busy_cycles              165293.030003                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.953759                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.046241                       # Percentage of idle cycles
+system.cpu3.num_idle_cycles               8001.119846                       # Number of idle cycles
+system.cpu3.num_busy_cycles              165292.880154                       # Number of busy cycles
+system.cpu3.not_idle_fraction                0.953829                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.046171                       # Percentage of idle cycles
 system.cpu3.icache.replacements                   279                       # number of replacements
-system.cpu3.icache.tagsinuse                72.869097                       # Cycle average of tags in use
+system.cpu3.icache.tagsinuse                72.874497                       # Cycle average of tags in use
 system.cpu3.icache.total_refs                  166942                       # Total number of references to valid blocks.
 system.cpu3.icache.sampled_refs                   359                       # Sample count of references to valid blocks.
 system.cpu3.icache.avg_refs                465.019499                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst    72.869097                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.142322                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.142322                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::cpu3.inst    72.874497                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.142333                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.142333                       # Average percentage of cache occupancy
 system.cpu3.icache.ReadReq_hits::cpu3.inst       166942                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         166942                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       166942                       # number of demand (read+write) hits
@@ -491,14 +491,14 @@ system.cpu3.icache.fast_writes                      0                       # nu
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     0                       # number of replacements
-system.cpu3.dcache.tagsinuse                28.793270                       # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse                28.795404                       # Cycle average of tags in use
 system.cpu3.dcache.total_refs                   30236                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    27                       # Sample count of references to valid blocks.
 system.cpu3.dcache.avg_refs               1119.851852                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data    28.793270                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.056237                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.056237                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::cpu3.data    28.795404                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.056241                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.056241                       # Average percentage of cache occupancy
 system.cpu3.dcache.ReadReq_hits::cpu3.data        41301                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          41301                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        14260                       # number of WriteReq hits
@@ -549,20 +549,20 @@ system.cpu3.dcache.fast_writes                      0                       # nu
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       366.557230                       # Cycle average of tags in use
+system.l2c.tagsinuse                       366.582542                       # Cycle average of tags in use
 system.l2c.total_refs                            1220                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                           421                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.897862                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks            0.966368                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           239.409595                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data            55.204245                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst            59.507442                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data             6.720647                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst             1.930518                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data             0.935341                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst             0.977501                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data             0.905573                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks            0.966439                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           239.426226                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            55.207595                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            59.511852                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             6.721145                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             1.930661                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.935410                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             0.977573                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.905640                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.000015                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.inst            0.003653                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.data            0.000842                       # Average percentage of cache occupancy
@@ -572,7 +572,7 @@ system.l2c.occ_percent::cpu2.inst            0.000029                       # Av
 system.l2c.occ_percent::cpu2.data            0.000014                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.inst            0.000015                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.data            0.000014                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.005593                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.005594                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
index 55888365a5606cd2a5910fc5f95e17cc4e0e0763..636fc646c94c68bec5c2119935ac69972932517a 100644 (file)
@@ -450,7 +450,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=8
-master=system.physmem.port[0]
+master=system.physmem.port
 slave=system.l2c.mem_side system.system_port
 
 [system.physmem]
index 900805018e1663bc783a4b5d74f315ae06c590c5..d61ea072e3638595d0dfb0d2f2b6ad6658d9e9ae 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jul  2 2012 08:54:18
-gem5 started Jul  2 2012 11:32:06
+gem5 compiled Aug 13 2012 17:04:37
+gem5 started Aug 13 2012 18:13:39
 gem5 executing on zizzer
-command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
@@ -79,4 +79,4 @@ Iteration 9 completed
 [Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 268912000 because target called exit()
+Exiting @ tick 268898000 because target called exit()
index ea05c2e9c8a6de32ff1bfd88074acd3c4ecd0ea8..1523ab302d0a7c2d4c9529aa985cac466b834c94 100644 (file)
@@ -1,16 +1,16 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.000269                       # Number of seconds simulated
-sim_ticks                                   268912000                       # Number of ticks simulated
-final_tick                                  268912000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                   268898000                       # Number of ticks simulated
+final_tick                                  268898000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 548575                       # Simulator instruction rate (inst/s)
-host_op_rate                                   548567                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              220132321                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 230896                       # Number of bytes of host memory used
-host_seconds                                     1.22                       # Real time elapsed on the host
-sim_insts                                      670117                       # Number of instructions simulated
-sim_ops                                        670117                       # Number of ops (including micro ops) simulated
+host_inst_rate                                1131883                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1131850                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              454173870                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 240368                       # Number of bytes of host memory used
+host_seconds                                     0.59                       # Real time elapsed on the host
+sim_insts                                      670104                       # Number of instructions simulated
+sim_ops                                        670104                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            18240                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.data            10560                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst             3776                       # Number of bytes read from this memory
@@ -34,67 +34,67 @@ system.physmem.num_reads::cpu2.data                15                       # Nu
 system.physmem.num_reads::cpu3.inst                 8                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu3.data                16                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                   572                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst            67828881                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data            39269352                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst            14041768                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data             5235914                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst              475992                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data             3569941                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst             1903969                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data             3807937                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               136133754                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst       67828881                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst       14041768                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst         475992                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst        1903969                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total           84250610                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst           67828881                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data           39269352                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst           14041768                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data            5235914                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst             475992                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data            3569941                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst            1903969                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data            3807937                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              136133754                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst            67832412                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data            39271397                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst            14042499                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data             5236186                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst              476017                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data             3570127                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst             1904068                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data             3808135                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               136140842                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst       67832412                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst       14042499                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst         476017                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst        1904068                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total           84254996                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst           67832412                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data           39271397                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst           14042499                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data            5236186                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst             476017                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data            3570127                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst            1904068                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data            3808135                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              136140842                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu0.workload.num_syscalls                  89                       # Number of system calls
-system.cpu0.numCycles                          537824                       # number of cpu cycles simulated
+system.cpu0.numCycles                          537796                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                     160927                       # Number of instructions committed
-system.cpu0.committedOps                       160927                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses               110780                       # Number of integer alu accesses
+system.cpu0.committedInsts                     160914                       # Number of instructions committed
+system.cpu0.committedOps                       160914                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses               110768                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts        26423                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                      110780                       # number of integer instructions
+system.cpu0.num_conditional_control_insts        26422                       # number of instructions that are conditional controls
+system.cpu0.num_int_insts                      110768                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads             320484                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes            112387                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads             320462                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes            112374                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                        75192                       # number of memory refs
-system.cpu0.num_load_insts                      49788                       # Number of load instructions
+system.cpu0.num_mem_refs                        75191                       # number of memory refs
+system.cpu0.num_load_insts                      49787                       # Number of load instructions
 system.cpu0.num_store_insts                     25404                       # Number of store instructions
 system.cpu0.num_idle_cycles                         0                       # Number of idle cycles
-system.cpu0.num_busy_cycles                    537824                       # Number of busy cycles
+system.cpu0.num_busy_cycles                    537796                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
 system.cpu0.icache.replacements                   215                       # number of replacements
-system.cpu0.icache.tagsinuse               212.253377                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                  160523                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               212.263647                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                  160510                       # Total number of references to valid blocks.
 system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                343.732334                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                343.704497                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst   212.253377                       # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst     0.414557                       # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total        0.414557                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst       160523                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total         160523                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst       160523                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total          160523                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst       160523                       # number of overall hits
-system.cpu0.icache.overall_hits::total         160523                       # number of overall hits
+system.cpu0.icache.occ_blocks::cpu0.inst   212.263647                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.414577                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.414577                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst       160510                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         160510                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       160510                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          160510                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       160510                       # number of overall hits
+system.cpu0.icache.overall_hits::total         160510                       # number of overall hits
 system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
 system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
@@ -107,12 +107,12 @@ system.cpu0.icache.demand_miss_latency::cpu0.inst     18554000
 system.cpu0.icache.demand_miss_latency::total     18554000                       # number of demand (read+write) miss cycles
 system.cpu0.icache.overall_miss_latency::cpu0.inst     18554000                       # number of overall miss cycles
 system.cpu0.icache.overall_miss_latency::total     18554000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst       160990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total       160990                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst       160990                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total       160990                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst       160990                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total       160990                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       160977                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       160977                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       160977                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       160977                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       160977                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       160977                       # number of overall (read+write) accesses
 system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002901                       # miss rate for ReadReq accesses
 system.cpu0.icache.ReadReq_miss_rate::total     0.002901                       # miss rate for ReadReq accesses
 system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002901                       # miss rate for demand accesses
@@ -159,24 +159,24 @@ system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36730.192719
 system.cpu0.icache.overall_avg_mshr_miss_latency::total 36730.192719                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     2                       # number of replacements
-system.cpu0.dcache.tagsinuse               145.513886                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                   74668                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               145.520681                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                   74667                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                447.113772                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                447.107784                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data   145.513886                       # Average occupied blocks per requestor
-system.cpu0.dcache.occ_percent::cpu0.data     0.284207                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::total        0.284207                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::cpu0.data        49616                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total          49616                       # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   145.520681                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.284220                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.284220                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        49615                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          49615                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        25170                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total         25170                       # number of WriteReq hits
 system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
 system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data        74786                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total           74786                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data        74786                       # number of overall hits
-system.cpu0.dcache.overall_hits::total          74786                       # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data        74785                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           74785                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        74785                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          74785                       # number of overall hits
 system.cpu0.dcache.ReadReq_misses::cpu0.data          162                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
 system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
@@ -197,18 +197,18 @@ system.cpu0.dcache.demand_miss_latency::cpu0.data     12481000
 system.cpu0.dcache.demand_miss_latency::total     12481000                       # number of demand (read+write) miss cycles
 system.cpu0.dcache.overall_miss_latency::cpu0.data     12481000                       # number of overall miss cycles
 system.cpu0.dcache.overall_miss_latency::total     12481000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data        49778                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total        49778                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        49777                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        49777                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::cpu0.data        25353                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total        25353                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
 system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data        75131                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total        75131                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data        75131                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total        75131                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003254                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total     0.003254                       # miss rate for ReadReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data        75130                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        75130                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        75130                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        75130                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003255                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total     0.003255                       # miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007218                       # miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_miss_rate::total     0.007218                       # miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
@@ -257,8 +257,8 @@ system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11445001
 system.cpu0.dcache.demand_mshr_miss_latency::total     11445001                       # number of demand (read+write) MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11445001                       # number of overall MSHR miss cycles
 system.cpu0.dcache.overall_mshr_miss_latency::total     11445001                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003254                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003254                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003255                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.003255                       # mshr miss rate for ReadReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007218                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.007218                       # mshr miss rate for WriteReq accesses
 system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
@@ -278,7 +278,7 @@ system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33173.915942
 system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33173.915942                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33173.915942                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.numCycles                          537824                       # number of cpu cycles simulated
+system.cpu1.numCycles                          537796                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu1.committedInsts                     159902                       # Number of instructions committed
@@ -296,19 +296,19 @@ system.cpu1.num_fp_register_writes                  0                       # nu
 system.cpu1.num_mem_refs                        64016                       # number of memory refs
 system.cpu1.num_load_insts                      42937                       # Number of load instructions
 system.cpu1.num_store_insts                     21079                       # Number of store instructions
-system.cpu1.num_idle_cycles              71606.001734                       # Number of idle cycles
+system.cpu1.num_idle_cycles              71578.001734                       # Number of idle cycles
 system.cpu1.num_busy_cycles              466217.998266                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.866860                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.133140                       # Percentage of idle cycles
+system.cpu1.not_idle_fraction                0.866905                       # Percentage of non-idle cycles
+system.cpu1.idle_fraction                    0.133095                       # Percentage of idle cycles
 system.cpu1.icache.replacements                   280                       # number of replacements
-system.cpu1.icache.tagsinuse                69.902178                       # Cycle average of tags in use
+system.cpu1.icache.tagsinuse                69.905818                       # Cycle average of tags in use
 system.cpu1.icache.total_refs                  159569                       # Total number of references to valid blocks.
 system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                435.980874                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst    69.902178                       # Average occupied blocks per requestor
-system.cpu1.icache.occ_percent::cpu1.inst     0.136528                       # Average percentage of cache occupancy
-system.cpu1.icache.occ_percent::total        0.136528                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::cpu1.inst    69.905818                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.136535                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.136535                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst       159569                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         159569                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       159569                       # number of demand (read+write) hits
@@ -379,14 +379,14 @@ system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18814.207650
 system.cpu1.icache.overall_avg_mshr_miss_latency::total 18814.207650                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     0                       # number of replacements
-system.cpu1.dcache.tagsinuse                27.730072                       # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse                27.731515                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                   44449                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs               1532.724138                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::cpu1.data    27.730072                       # Average occupied blocks per requestor
-system.cpu1.dcache.occ_percent::cpu1.data     0.054160                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::total        0.054160                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::cpu1.data    27.731515                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.054163                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.054163                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data        42776                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          42776                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        20903                       # number of WriteReq hits
@@ -496,7 +496,7 @@ system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18000.003861
 system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18000.003861                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18000.003861                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.numCycles                          537824                       # number of cpu cycles simulated
+system.cpu2.numCycles                          537796                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu2.committedInsts                     177221                       # Number of instructions committed
@@ -514,19 +514,19 @@ system.cpu2.num_fp_register_writes                  0                       # nu
 system.cpu2.num_mem_refs                        47896                       # number of memory refs
 system.cpu2.num_load_insts                      40447                       # Number of load instructions
 system.cpu2.num_store_insts                      7449                       # Number of store instructions
-system.cpu2.num_idle_cycles              71882.001733                       # Number of idle cycles
+system.cpu2.num_idle_cycles              71854.001733                       # Number of idle cycles
 system.cpu2.num_busy_cycles              465941.998267                       # Number of busy cycles
-system.cpu2.not_idle_fraction                0.866347                       # Percentage of non-idle cycles
-system.cpu2.idle_fraction                    0.133653                       # Percentage of idle cycles
+system.cpu2.not_idle_fraction                0.866392                       # Percentage of non-idle cycles
+system.cpu2.idle_fraction                    0.133608                       # Percentage of idle cycles
 system.cpu2.icache.replacements                   281                       # number of replacements
-system.cpu2.icache.tagsinuse                67.531468                       # Cycle average of tags in use
+system.cpu2.icache.tagsinuse                67.534984                       # Cycle average of tags in use
 system.cpu2.icache.total_refs                  176887                       # Total number of references to valid blocks.
 system.cpu2.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
 system.cpu2.icache.avg_refs                481.980926                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::cpu2.inst    67.531468                       # Average occupied blocks per requestor
-system.cpu2.icache.occ_percent::cpu2.inst     0.131897                       # Average percentage of cache occupancy
-system.cpu2.icache.occ_percent::total        0.131897                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::cpu2.inst    67.534984                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.131904                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.131904                       # Average percentage of cache occupancy
 system.cpu2.icache.ReadReq_hits::cpu2.inst       176887                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         176887                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       176887                       # number of demand (read+write) hits
@@ -597,14 +597,14 @@ system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12557.220708
 system.cpu2.icache.overall_avg_mshr_miss_latency::total 12557.220708                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     0                       # number of replacements
-system.cpu2.dcache.tagsinuse                26.637011                       # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse                26.638398                       # Cycle average of tags in use
 system.cpu2.dcache.total_refs                   17171                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
 system.cpu2.dcache.avg_refs                592.103448                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::cpu2.data    26.637011                       # Average occupied blocks per requestor
-system.cpu2.dcache.occ_percent::cpu2.data     0.052025                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::total        0.052025                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::cpu2.data    26.638398                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.052028                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.052028                       # Average percentage of cache occupancy
 system.cpu2.dcache.ReadReq_hits::cpu2.data        40266                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          40266                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data         7273                       # number of WriteReq hits
@@ -714,7 +714,7 @@ system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19708.633094
 system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19708.633094                       # average overall mshr miss latency
 system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19708.633094                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.numCycles                          537824                       # number of cpu cycles simulated
+system.cpu3.numCycles                          537796                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
 system.cpu3.committedInsts                     172067                       # Number of instructions committed
@@ -732,19 +732,19 @@ system.cpu3.num_fp_register_writes                  0                       # nu
 system.cpu3.num_mem_refs                        52937                       # number of memory refs
 system.cpu3.num_load_insts                      41268                       # Number of load instructions
 system.cpu3.num_store_insts                     11669                       # Number of store instructions
-system.cpu3.num_idle_cycles              72158.001732                       # Number of idle cycles
+system.cpu3.num_idle_cycles              72130.001732                       # Number of idle cycles
 system.cpu3.num_busy_cycles              465665.998268                       # Number of busy cycles
-system.cpu3.not_idle_fraction                0.865833                       # Percentage of non-idle cycles
-system.cpu3.idle_fraction                    0.134167                       # Percentage of idle cycles
+system.cpu3.not_idle_fraction                0.865879                       # Percentage of non-idle cycles
+system.cpu3.idle_fraction                    0.134121                       # Percentage of idle cycles
 system.cpu3.icache.replacements                   280                       # number of replacements
-system.cpu3.icache.tagsinuse                65.342080                       # Cycle average of tags in use
+system.cpu3.icache.tagsinuse                65.345482                       # Cycle average of tags in use
 system.cpu3.icache.total_refs                  171734                       # Total number of references to valid blocks.
 system.cpu3.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
 system.cpu3.icache.avg_refs                469.218579                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::cpu3.inst    65.342080                       # Average occupied blocks per requestor
-system.cpu3.icache.occ_percent::cpu3.inst     0.127621                       # Average percentage of cache occupancy
-system.cpu3.icache.occ_percent::total        0.127621                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::cpu3.inst    65.345482                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.127628                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.127628                       # Average percentage of cache occupancy
 system.cpu3.icache.ReadReq_hits::cpu3.inst       171734                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         171734                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       171734                       # number of demand (read+write) hits
@@ -815,14 +815,14 @@ system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12423.497268
 system.cpu3.icache.overall_avg_mshr_miss_latency::total 12423.497268                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     0                       # number of replacements
-system.cpu3.dcache.tagsinuse                25.848817                       # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse                25.850163                       # Cycle average of tags in use
 system.cpu3.dcache.total_refs                   25744                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
 system.cpu3.dcache.avg_refs                858.133333                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::cpu3.data    25.848817                       # Average occupied blocks per requestor
-system.cpu3.dcache.occ_percent::cpu3.data     0.050486                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::total        0.050486                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::cpu3.data    25.850163                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.050489                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.050489                       # Average percentage of cache occupancy
 system.cpu3.dcache.ReadReq_hits::cpu3.data        41084                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          41084                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        11491                       # number of WriteReq hits
@@ -933,20 +933,20 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 19284.697509
 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 19284.697509                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
-system.l2c.tagsinuse                       348.808930                       # Cycle average of tags in use
+system.l2c.tagsinuse                       348.825789                       # Cycle average of tags in use
 system.l2c.total_refs                            1221                       # Total number of references to valid blocks.
 system.l2c.sampled_refs                           429                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.846154                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks            0.888060                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.inst           231.678051                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu0.data            54.187452                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.inst            51.469392                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu1.data             6.113383                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.inst             1.770981                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu2.data             0.842116                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.inst             1.030371                       # Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu3.data             0.829126                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::writebacks            0.888106                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           231.689332                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            54.189752                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            51.472071                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             6.113701                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             1.771073                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.842159                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             1.030424                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.829169                       # Average occupied blocks per requestor
 system.l2c.occ_percent::writebacks           0.000014                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.inst            0.003535                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
@@ -956,7 +956,7 @@ system.l2c.occ_percent::cpu2.inst            0.000027                       # Av
 system.l2c.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.inst            0.000016                       # Average percentage of cache occupancy
 system.l2c.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
-system.l2c.occ_percent::total                0.005322                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.005323                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits