add stlinkv2 photos

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 0dcff636e753ca3ad767ae76f2a07ecb514908ec..65d43012218b3c545c69bde95fa73a766511d922 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -163,6 +163,12 @@ Luke do the labels of PCLK[C|T]0_[0|1] and GR_PCLK0_[0|1] have any significance?
 
 Additionally, does the note in the schematic about needing to swap EVEN and ODD pin numbers if using MALE VERTICAL header instead of FEMALE 90° ANGLED header apply to us?
 
+# STLinkV2 connector
+
+[[!img 2020-11-03_14-08.png size="900x" ]] 
+
+[[!img 2020-11-03_14-09.png size="900x" ]] 
+
 # VERSA ECP5 Connections
 
 Table of connections: