## Abstract: Can you explain the whole project and its expected outcome(s).
+This project, a collaboration between RED Semiconductor and LibreSOC, aims to build on the work already completed in bringing a new vectorised microprocessor architecture to proof of concept, and opening it up to the global RISC-V community so that they can access an open-source ISA that truly competes with the costly high-end incumbents like ARM, Intel and IBM. This is a vital step in bringing open-source High Performance Computing to all developers, no matter the size of their organisation, and will enable the next wave of open innovation. The outcome of the project will be the validation of LibreSoC's Simple-V/SVP64 architecture on RISC-V base architecture, demonstrated in a software simulator.
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+The largest single open-source global community for microprocessor architecture is RISC-V, where developers can create unique instructions to solve their specific computational challenges, and develop their own SoC hardware implementations. IP cores are available commercially, or developers can start from scratch. RISC-V is ideal for simple microcontroller type of applications, and in a very few cases well-resourced organisations are developing hyperscaled RISC-V cores in SoCs, or combining RISC-V with other core functions like GPU, DSP in homogeneous computing SoCs. There is a massive gap that needs filling. Open-source RISC-V High Performance Computing needs to be made available to the world’s innovators seeking to solve the global challenges of freedom of information, yet maintaining personal privacy and security – challenges being exposed by global megatrends like AI, metaverse and social media, as well as social issues like healthcare and critical infrastructure.
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# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
projects / libreriscv.git / commitdiff