ARM: Ignore/warn access to the bpimva registers.

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 8ba46960ab7cba2a063e29fcbc0edd8b2504d251..7d58350a47f21ac9d851378fdb4e59b3e40f9dc8 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -119,6 +119,9 @@ def format McrMrc15() {{
           case MISCREG_ICIMVAU:
             return new WarnUnimplemented(
                     isRead ? "mrc icimvau" : "mcr icimvau", machInst);
+          case MISCREG_BPIMVA:
+            return new WarnUnimplemented(
+                    isRead ? "mrc bpimva" : "mcr bpimva", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index df3d0094614b00e114ed347091d7a025ef2e45a3..d66ce0f78ccb4c428ed5624221b147e278232f36 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -97,6 +97,7 @@ namespace ArmISA
         MISCREG_ICIALLUIS,
         MISCREG_ICIALLU,
         MISCREG_ICIMVAU,
+        MISCREG_BPIMVA,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -136,7 +137,6 @@ namespace ArmISA
         MISCREG_RGNR,
         MISCREG_BPIALLIS,
         MISCREG_BPIALL,
-        MISCREG_BPIMVA,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
         MISCREG_MCCSW,
@@ -161,7 +161,7 @@ namespace ArmISA
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
-        "icialluis", "iciallu", "icimvau",
+        "icialluis", "iciallu", "icimvau", "bpimva",
         "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@@ -170,7 +170,7 @@ namespace ArmISA
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
         "rgnr", "bpiallis",
-        "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw",
+        "bpiall", "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nop", "raz"
     };