#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_wm.h"
/**
* Helper function to emit depth related command packets.
hiz, width, height, depth, lod, min_array_element);
}
+/**
+ * Should we set the PMA FIX ENABLE bit?
+ *
+ * To avoid unnecessary depth related stalls, we need to set this bit.
+ * However, there is a very complicated formula which governs when it
+ * is legal to do so. This function computes that.
+ *
+ * See the documenation for the CACHE_MODE_1 register, bit 11.
+ */
+static bool
+pma_fix_enable(const struct brw_context *brw)
+{
+ const struct gl_context *ctx = &brw->ctx;
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct gl_fragment_program *fp = brw->fragment_program;
+ /* _NEW_BUFFERS */
+ struct intel_renderbuffer *depth_irb =
+ intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
+
+ /* 3DSTATE_WM::ForceThreadDispatch is never used. */
+ const bool wm_force_thread_dispatch = false;
+
+ /* 3DSTATE_RASTER::ForceSampleCount is never used. */
+ const bool raster_force_sample_count_nonzero = false;
+
+ /* _NEW_BUFFERS:
+ * 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL &&
+ * 3DSTATE_DEPTH_BUFFER::HIZ Enable
+ */
+ const bool hiz_enabled = depth_irb && intel_renderbuffer_has_hiz(depth_irb);
+
+ /* 3DSTATE_WM::Early Depth/Stencil Control != EDSC_PREPS (2).
+ * We always leave this set to EDSC_NORMAL (0).
+ */
+ const bool edsc_not_preps = true;
+
+ /* 3DSTATE_PS_EXTRA::PixelShaderValid is always true. */
+ const bool pixel_shader_valid = true;
+
+ /* !(3DSTATE_WM_HZ_OP::DepthBufferClear ||
+ * 3DSTATE_WM_HZ_OP::DepthBufferResolve ||
+ * 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable ||
+ * 3DSTATE_WM_HZ_OP::StencilBufferClear)
+ *
+ * HiZ operations are done outside of the normal state upload, so they're
+ * definitely not happening now.
+ */
+ const bool in_hiz_op = false;
+
+ /* _NEW_DEPTH:
+ * DEPTH_STENCIL_STATE::DepthTestEnable
+ */
+ const bool depth_test_enabled = depth_irb && ctx->Depth.Test;
+
+ /* _NEW_DEPTH:
+ * 3DSTATE_WM_DEPTH_STENCIL::DepthWriteEnable &&
+ * 3DSTATE_DEPTH_BUFFER::DEPTH_WRITE_ENABLE.
+ */
+ const bool depth_writes_enabled = ctx->Depth.Mask;
+
+ /* _NEW_STENCIL:
+ * !DEPTH_STENCIL_STATE::Stencil Buffer Write Enable ||
+ * !3DSTATE_DEPTH_BUFFER::Stencil Buffer Enable ||
+ * !3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable
+ */
+ const bool stencil_writes_enabled = ctx->Stencil._WriteEnabled;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM:
+ * 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode == PSCDEPTH_OFF
+ */
+ const bool ps_computes_depth =
+ (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) &&
+ fp->FragDepthLayout != FRAG_DEPTH_LAYOUT_UNCHANGED;
+
+ /* BRW_NEW_FRAGMENT_PROGRAM: 3DSTATE_PS_EXTRA::PixelShaderKillsPixels
+ * CACHE_NEW_WM_PROG: 3DSTATE_PS_EXTRA::oMask Present to RenderTarget
+ * _NEW_MULTISAMPLE: 3DSTATE_PS_BLEND::AlphaToCoverageEnable
+ * _NEW_COLOR: 3DSTATE_PS_BLEND::AlphaTestEnable
+ *
+ * 3DSTATE_WM_CHROMAKEY::ChromaKeyKillEnable is always false.
+ * 3DSTATE_WM::ForceKillPix != ForceOff is always true.
+ */
+ const bool kill_pixel =
+ fp->UsesKill ||
+ brw->wm.prog_data->uses_omask ||
+ (ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToCoverage) ||
+ ctx->Color.AlphaEnabled;
+
+ /* The big formula in CACHE_MODE_1::NP PMA FIX ENABLE. */
+ return !wm_force_thread_dispatch &&
+ !raster_force_sample_count_nonzero &&
+ hiz_enabled &&
+ edsc_not_preps &&
+ pixel_shader_valid &&
+ !in_hiz_op &&
+ depth_test_enabled &&
+ (ps_computes_depth ||
+ (kill_pixel && (depth_writes_enabled || stencil_writes_enabled)));
+}
+
+static void
+write_pma_stall_bits(struct brw_context *brw, uint32_t pma_stall_bits)
+{
+ struct gl_context *ctx = &brw->ctx;
+
+ /* If we haven't actually changed the value, bail now to avoid unnecessary
+ * pipeline stalls and register writes.
+ */
+ if (brw->pma_stall_bits == pma_stall_bits)
+ return;
+
+ brw->pma_stall_bits = pma_stall_bits;
+
+ /* According to the PIPE_CONTROL documentation, software should emit a
+ * PIPE_CONTROL with the CS Stall and Depth Cache Flush bits set prior
+ * to the LRI. If stencil buffer writes are enabled, then a Render Cache
+ * Flush is also necessary.
+ */
+ const uint32_t render_cache_flush =
+ ctx->Stencil._WriteEnabled ? PIPE_CONTROL_WRITE_FLUSH : 0;
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ render_cache_flush);
+
+ /* CACHE_MODE_1 is a non-privileged register. */
+ BEGIN_BATCH(3);
+ OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+ OUT_BATCH(GEN7_CACHE_MODE_1);
+ OUT_BATCH(GEN8_HIZ_PMA_MASK_BITS | pma_stall_bits);
+ ADVANCE_BATCH();
+
+ /* After the LRI, a PIPE_CONTROL with both the Depth Stall and Depth Cache
+ * Flush bits is often necessary. We do it regardless because it's easier.
+ * The render cache flush is also necessary if stencil writes are enabled.
+ */
+ brw_emit_pipe_control_flush(brw,
+ PIPE_CONTROL_DEPTH_STALL |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ render_cache_flush);
+
+}
+
+static void
+gen8_emit_pma_stall_workaround(struct brw_context *brw)
+{
+ uint32_t bits = 0;
+ if (pma_fix_enable(brw))
+ bits |= GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE;
+
+ write_pma_stall_bits(brw, bits);
+}
+
+const struct brw_tracked_state gen8_pma_fix = {
+ .dirty = {
+ .mesa = _NEW_BUFFERS |
+ _NEW_COLOR |
+ _NEW_DEPTH |
+ _NEW_MULTISAMPLE |
+ _NEW_STENCIL,
+ .brw = BRW_NEW_FRAGMENT_PROGRAM,
+ .cache = CACHE_NEW_WM_PROG,
+ },
+ .emit = gen8_emit_pma_stall_workaround
+};
+
/**
* Emit packets to perform a depth/HiZ resolve or fast depth/stencil clear.
*
if (op == GEN6_HIZ_OP_NONE)
return;
+ /* Disable the PMA stall fix since we're about to do a HiZ operation. */
+ write_pma_stall_bits(brw, 0);
+
assert(mt->first_level == 0);
assert(mt->logical_depth0 >= 1);
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