Reformat cache_ram

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/cache_ram.vhdl b/cache_ram.vhdl
index 4db8e0a08a32b75d00e079956310a6f629fbfe5d..8c8c495a4f6a430a8f30dc36dd6d55f25595297f 100644 (file)
--- a/cache_ram.vhdl
+++ b/cache_ram.vhdl
@@ -5,21 +5,21 @@ use ieee.math_real.all;
 
 entity cache_ram is
     generic(
-       ROW_BITS : integer := 16;
-       WIDTH    : integer := 64;
-       TRACE    : boolean := false;
-       ADD_BUF  : boolean := false
-       );
+        ROW_BITS : integer := 16;
+        WIDTH    : integer := 64;
+        TRACE    : boolean := false;
+        ADD_BUF  : boolean := false
+        );
 
     port(
-       clk     : in  std_logic;
-       rd_en   : in  std_logic;
-       rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
-       rd_data : out std_logic_vector(WIDTH - 1 downto 0);
-       wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
-       wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
-       wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
-       );
+        clk     : in  std_logic;
+        rd_en   : in  std_logic;
+        rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
+        rd_data : out std_logic_vector(WIDTH - 1 downto 0);
+        wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
+        wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
+        wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
+        );
 
 end cache_ram;
 
@@ -35,13 +35,13 @@ architecture rtl of cache_ram is
 
 begin
     process(clk)
-       variable lbit : integer range 0 to WIDTH - 1;
-       variable mbit : integer range 0 to WIDTH - 1;
-       variable widx : integer range 0 to SIZE - 1;
-       constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
+        variable lbit : integer range 0 to WIDTH - 1;
+        variable mbit : integer range 0 to WIDTH - 1;
+        variable widx : integer range 0 to SIZE - 1;
+        constant sel0 : std_logic_vector(WIDTH/8 - 1 downto 0)
             := (others => '0');
     begin
-       if rising_edge(clk) then
+        if rising_edge(clk) then
             if TRACE then
                 if wr_sel /= sel0 then
                     report "write a:" & to_hstring(wr_addr) &
@@ -57,29 +57,29 @@ begin
                     ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
                 end if;
             end loop;
-           if rd_en = '1' then
-               rd_data0 <= ram(to_integer(unsigned(rd_addr)));
-               if TRACE then
-                   report "read a:" & to_hstring(rd_addr) &
-                       " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
-               end if;
-           end if;
-       end if;
+            if rd_en = '1' then
+                rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+                if TRACE then
+                    report "read a:" & to_hstring(rd_addr) &
+                        " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
+                end if;
+            end if;
+        end if;
     end process;
 
     buf: if ADD_BUF generate
     begin
-       process(clk)
-       begin
-           if rising_edge(clk) then
-               rd_data <= rd_data0;
-           end if;
-       end process;
+        process(clk)
+        begin
+            if rising_edge(clk) then
+                rd_data <= rd_data0;
+            end if;
+        end process;
     end generate;
 
     nobuf: if not ADD_BUF generate
     begin
-       rd_data <= rd_data0;
+        rd_data <= rd_data0;
     end generate;
 
 end;