add saturate SVP64 RM mode decode

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 963f2cfbf7a13e88a83a9863ec4aa2f42e771aa6..981e51a8d20c1d1e002b7bc512dbd8201fe0b9a9 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -142,6 +142,16 @@ class SVP64RMModeDecode(Elaboratable):
                     comb += self.pred_sz.eq(mode[SVP64MODE.SZ])
                     comb += self.pred_dz.eq(mode[SVP64MODE.DZ])
 
+        # extract saturate
+        with m.Switch(mode2):
+            with m.Case(2):
+                with m.If(mode[SVP64MODE.N]):
+                    comb += self.saturate.eq(SVP64sat.UNSIGNED)
+                with m.Else():
+                    comb += self.saturate.eq(SVP64sat.SIGNED)
+            with m.Default():
+                comb += self.saturate.eq(SVP64sat.NONE)
+
         # extract src/dest predicate.  use EXTRA3.MASK because EXTRA2.MASK
         # is in exactly the same bits
         srcmask = sel(m, self.rm_in.extra, EXTRA3.MASK)