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diff --git a/nlnet_2023_simplev_riscv_binutils.mdwn b/nlnet_2023_simplev_riscv_binutils.mdwn
index fcf6a51a78f49643cc14c115a9e7a5f8e6f59a32..d9ab781b9c32447d8dd09428e4cdb256063c7e0c 100644 (file)
--- a/nlnet_2023_simplev_riscv_binutils.mdwn
+++ b/nlnet_2023_simplev_riscv_binutils.mdwn
@@ -9,10 +9,12 @@ Toplevel bugreport: https://bugs.libre-soc.org/
 This project is applying for funding through the NGI Zero Core Fund, a fund established by NLnet with financial support from the European Commission's Next Generation Internet programme under grant agreement No 101092990.
 
 ## Project name
-Binutils for SVP64 ISA Expansion Project
+
+Binutils for Simple-V ISA Expansion Project
 
 ## Website / wiki
-https://libre-soc.org/nlnet_2023_svp64_riscv
+
+https://libre-soc.org/nlnet_2023_simplev_riscv_binutils
 
 Please be short and to the point in your answers; focus primarily on the what and how, not so much on the why. Add longer descriptions as attachments (see below). If English isn't your first language, don't worry - our reviewers don't care about spelling errors, only about great ideas. We apologise for the inconvenience of having to submit in English. On the up side, you can be as technical as you need to be (but you don't have to). Do stay concrete. Use plain text in your reply only, if you need any HTML to make your point please include this as attachment.
 
@@ -22,38 +24,47 @@ This project is a collaboration between RED Semiconductor and LibreSOC to create
 
 The completed tools will be made available to developers via LibreSOC's website and git repositories.
 
-#Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
+# Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
+
 A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: https://libre-soc.org/nlnet_proposals/ they include recently:
 
 * https://libre-soc.org/nlnet_2022_opf_isa_wg/ - improving SVP64 and submitting it to the OpenPOWER ISA Technical Working Group.
 
 * https://libre-soc.org/nlnet_2021_crypto_router/ - proving, improving, and demonstrating that SVP64 is capable of handling cryptographic primitives in an extreme power-efficient compact way as the basis for higher security products
 
-#Requested Amount
-EUR 50,000.
+# Requested Amount
 
-#Explain what the requested budget will be used for?
-Key phases of this project are:
+EUR 50,000.
 
-* Definition of assembler and disassembler and other binutil tools for RISC-V instructions and also SVP64 in the Libre-SOC infrastructure.
+# Explain what the requested budget will be used for?
 
-* Creation of test code routines based on output of previous POWER ISA projects (cryptoprimitives, codecs), and testing and validation of the binutils
+Key phases of this project are:
 
+* Definition of assembler and disassembler and other binutil tools for RISC-V
+  instructions and also SVP32, 48 and 64 in the Libre-SOC infrastructure.
+* Creation of test code routines based on output of previous POWER ISA projects
+  (cryptoprimitives, codecs), and testing and validation of the binutils
 * Documentation, demonstrations and Conference Papers. 
 
-90% of the budget is attributed to labour costs of the team involved from RED Semiconductor and LibreSOC - the project is entirely software-based and no additional hardware requirements are anticipated. A small budget of €5k is allocated to travel for presentation of the project results at industry conferences.
 
-#Does the project have other funding sources, both past and present?
+# Does the project have other funding sources, both past and present?
+
 NGI Search, NGI POINTER, and NLnet Grants have been the sole source of funding for this development programme over the past five years, and for the project in this application. Four grants are at stages of completion at the time of writing (two nearing end).
 
 #Compare your own project with existing or historical efforts.
+
 ##What are significant technical challenges you expect to solve during the project, if any?
+
 The key technical challenge in this project is the creation of the binutil tool set that enables developers to take advantage of the Simple-V/SVP64 extensions and capabilities for RISC-V, and to successfully develop and debug complex code. The binutil tools will be comprehensively tested and verified with the newly developed instructions (developed within the separate project) in order to lead the way for its use in the widespread developer community.
 
 This project relies on the experience and expertise of a subset of the RED Semiconductor/LibreSOC team who have developed similar tools for use with other ISAs.
 
 ##Describe the ecosystem of the project, and how you will engage with relevant actors and promote the outcomes?
+
 The Libre-SoC has a full set of resources for Libre Project Management and development: mailing list, bugtracker, git repository, wiki and also will be doing linkedin posts in other outreach - all listed here: https://libre-soc.org/
 
 #Extra info to be submitted
-#Questions Received date: TODO
+
+#Questions Received date:
+
+TODO