Fix timings in simulation to prevent tDLLK errors

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index 984984533fd42fe7614e496d3e226a5e6269603e..047367886e73f1f22f0add728b9ab54f7b33d88e 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -149,14 +149,14 @@ module simsoctb;
       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
       wishbone_write(32'h00009004 >> 2, 8'h0F); // RAS|CAS|WE|CS
       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
-      #2000;
+      #6000; // tDLLK
 
       // ZQ calibration
-      wishbone_write(32'h0000900c >> 2, 32'h400); // p0 address
+      wishbone_write(32'h0000900c >> 2, 32'h400); // p0 address (A10=1)
       wishbone_write(32'h00009010 >> 2, 32'h0); // p0 baddress
       wishbone_write(32'h00009004 >> 2, 8'h03); // WE|CS
       wishbone_write(32'h00009008 >> 2, 8'h01); // Command issue strobe
-      #2000;
+      #6000; // tZQinit
 
       // Hardware control
       wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL