#include "arch/alpha/linux/linux.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable AlphaLinux::openFlagTable[] = {
#ifdef _MSC_VER
output header {{
#include <iostream>
- using namespace std;
/**
* Base class for instructions whose disassembly is not purely a
//
output header {{
#include <iostream>
- using namespace std;
/**
* Base class for integer operations.
*/
std::string inst2string(MachInst machInst)
{
- string str = "";
+ std::string str = "";
uint32_t mask = 0x80000000;
for(int i=0; i < 32; i++) {
#include "arch/mips/linux/linux.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable MipsLinux::openFlagTable[] = {
#ifdef _MSC_VER
Fault setReg(int floatReg, const FloatRegVal &val, int width)
{
- using namespace std;
switch(width)
{
case SingleWidth:
Fault setRegBits(int floatReg, const FloatRegBits &val, int width)
{
- using namespace std;
switch(width)
{
#ifndef __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
#define __ARCH_MIPS_REGFILE_MISC_REGFILE_HH__
-#include "arch/mips/isa_traits.hh"
#include "arch/mips/types.hh"
#include "sim/faults.hh"
#define __ARCH_MIPS_REGFILE_REGFILE_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
#include "arch/mips/regfile/int_regfile.hh"
#include "arch/mips/regfile/float_regfile.hh"
#include "arch/mips/regfile/misc_regfile.hh"
* Authors: Korey Sewell
*/
-#include "arch/mips/isa_traits.hh"
+#include "arch/mips/regfile.hh"
#include "arch/mips/utility.hh"
-#include "config/full_system.hh"
-#include "cpu/static_inst.hh"
-#include "sim/serialize.hh"
+#include "base/misc.hh"
#include "base/bitfield.hh"
using namespace MipsISA;
-using namespace std;
uint64_t
MipsISA::fpConvert(ConvertType cvt_type, double fp_val)
#define __ARCH_MIPS_UTILITY_HH__
#include "arch/mips/types.hh"
-#include "arch/mips/isa_traits.hh"
#include "base/misc.hh"
+#include "config/full_system.hh"
//XXX This is needed for size_t. We should use something other than size_t
-#include "kern/linux/linux.hh"
+//#include "kern/linux/linux.hh"
#include "sim/host.hh"
+class ThreadContext;
+
namespace MipsISA {
//Floating Point Utility Functions
*/
#include "arch/sparc/linux/linux.hh"
+#include <fcntl.h>
// open(2) flags translation table
OpenFlagTransTable SparcLinux::openFlagTable[] = {
#define __SPARC_LINUX_PROCESS_HH__
#include "arch/sparc/linux/linux.hh"
+#include "arch/sparc/syscallreturn.hh"
#include "arch/sparc/process.hh"
#include "sim/process.hh"
#include "arch/sparc/solaris/solaris.hh"
+#include <fcntl.h>
+
// open(2) flags translation table
OpenFlagTransTable SparcSolaris::openFlagTable[] = {
#ifdef _MSC_VER
#include <inttypes.h>
+#include "arch/sparc/regfile.hh"
+
class SyscallReturn
{
public:
#include "base/cprintf.hh"
#include "base/trace.hh"
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "cpu/exetrace.hh"
#include "mem/request.hh"
#include "cpu/base_dyn_inst.hh"
-using namespace std;
-using namespace TheISA;
-
#define NOHASH
#ifndef NOHASH
#endif
template <class Impl>
-BaseDynInst<Impl>::BaseDynInst(ExtMachInst machInst, Addr inst_PC,
+BaseDynInst<Impl>::BaseDynInst(TheISA::ExtMachInst machInst, Addr inst_PC,
Addr pred_PC, InstSeqNum seq_num,
ImplCPU *cpu)
: staticInst(machInst), traceData(NULL), cpu(cpu)
seqNum = seq_num;
PC = inst_PC;
- nextPC = PC + sizeof(MachInst);
- nextNPC = nextPC + sizeof(MachInst);
+ nextPC = PC + sizeof(TheISA::MachInst);
+ nextNPC = nextPC + sizeof(TheISA::MachInst);
predPC = pred_PC;
initVars();
BaseDynInst<Impl>::dump()
{
cprintf("T%d : %#08d `", threadNumber, PC);
- cout << staticInst->disassemble(PC);
+ std::cout << staticInst->disassemble(PC);
cprintf("'\n");
}
#ifndef __CPU_O3_2BIT_LOCAL_PRED_HH__
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include "sim/host.hh"
#include <vector>
#ifndef __CPU_O3_ALPHA_CPU_HH__
#define __CPU_O3_ALPHA_CPU_HH__
-#include "arch/isa_traits.hh"
+#include "arch/regfile.hh"
+#include "arch/types.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
#endif
-using namespace TheISA;
-
template <class Impl>
AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
#if FULL_SYSTEM
#ifndef __CPU_O3_BPRED_UNIT_HH__
#define __CPU_O3_BPRED_UNIT_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "cpu/o3/ras.hh"
#include "cpu/o3/tournament_pred.hh"
+#include "sim/host.hh"
+
#include <list>
/**
* Authors: Kevin Lim
*/
-#include <list>
-#include <vector>
-
+#include "arch/types.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/bpred_unit.hh"
-using namespace std;
-
template<class Impl>
BPredUnit<Impl>::BPredUnit(Params *params)
: BTB(params->BTBEntries,
#include "base/trace.hh"
#include "cpu/o3/btb.hh"
-using namespace TheISA;
-
DefaultBTB::DefaultBTB(unsigned _numEntries,
unsigned _tagBits,
unsigned _instShiftAmt)
#ifndef __CPU_O3_BTB_HH__
#define __CPU_O3_BTB_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "base/misc.hh"
+#include "sim/host.hh"
class DefaultBTB
{
#include <vector>
-#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "sim/faults.hh"
#include "cpu/inst_seq.hh"
#include "sim/host.hh"
#ifndef __CPU_O3_COMMIT_HH__
#define __CPU_O3_COMMIT_HH__
-#include "arch/faults.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/exetrace.hh"
#include "cpu/checker/cpu.hh"
#endif
-using namespace std;
-
template <class Impl>
DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
unsigned _tid)
{
_status = Active;
_nextStatus = Inactive;
- string policy = params->smtCommitPolicy;
+ std::string policy = params->smtCommitPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
template <class Impl>
void
-DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
+DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
{
thread = threads;
}
template<class Impl>
void
-DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
activeThreads = at_ptr;
DefaultCommit<Impl>::updateStatus()
{
// reset ROB changed variable
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
changedROBNumEntries[tid] = false;
{
int squashes = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
bool
DefaultCommit<Impl>::changedROBEntries()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
if ((*activeThreads).size() <= 0)
return;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check if any of the threads are done squashing. Change the
// status if they are done.
// Check for any possible squashes, handle them first
////////////////////////////////////
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
#if THE_ISA == ALPHA_ISA
// Read any renamed instructions and place them into the ROB.
- int insts_to_process = min((int)renameWidth, fromRename->size);
+ int insts_to_process = std::min((int)renameWidth, fromRename->size);
#else
// Read any renamed instructions and place them into the ROB.
- int insts_to_process = min((int)renameWidth,
+ int insts_to_process = std::min((int)renameWidth,
(int)(fromRename->size + skidBuffer.size()));
int rename_idx = 0;
bool
DefaultCommit<Impl>::robDoneSquashing()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultCommit<Impl>::roundRobin()
{
- list<unsigned>::iterator pri_iter = priority_list.begin();
- list<unsigned>::iterator end = priority_list.end();
+ std::list<unsigned>::iterator pri_iter = priority_list.begin();
+ std::list<unsigned>::iterator end = priority_list.end();
while (pri_iter != end) {
unsigned tid = *pri_iter;
unsigned oldest = 0;
bool first = true;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
#include <set>
#include <vector>
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "config/full_system.hh"
#include "cpu/o3/decode.hh"
-using namespace std;
-
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(Params *params)
: renameToDecodeDelay(params->renameToDecodeDelay),
template<class Impl>
void
-DefaultDecode<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultDecode<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Decode, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
bool
DefaultDecode<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
toRenameIndex = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
sortInsts();
#include <algorithm>
-using namespace std;
-using namespace TheISA;
-
template<class Impl>
Tick
DefaultFetch<Impl>::IcachePort::recvAtomic(PacketPtr pkt)
// Set fetch stage's status to inactive.
_status = Inactive;
- string policy = params->smtFetchPolicy;
+ std::string policy = params->smtFetchPolicy;
// Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
}
// Get the size of an instruction.
- instSize = sizeof(MachInst);
+ instSize = sizeof(TheISA::MachInst);
}
template <class Impl>
template<class Impl>
void
-DefaultFetch<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultFetch<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Fetch, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
DefaultFetch<Impl>::updateFetchStatus()
{
//Check Running
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
void
DefaultFetch<Impl>::tick()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
bool status_change = false;
wroteToTimeBuffer = false;
int
DefaultFetch<Impl>::roundRobin()
{
- list<unsigned>::iterator pri_iter = priorityList.begin();
- list<unsigned>::iterator end = priorityList.end();
+ std::list<unsigned>::iterator pri_iter = priorityList.begin();
+ std::list<unsigned>::iterator end = priorityList.end();
int high_pri;
int
DefaultFetch<Impl>::iqCount()
{
- priority_queue<unsigned> PQ;
+ std::priority_queue<unsigned> PQ;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultFetch<Impl>::lsqCount()
{
- priority_queue<unsigned> PQ;
+ std::priority_queue<unsigned> PQ;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
int
DefaultFetch<Impl>::branchCount()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
panic("Branch Count Fetch policy unimplemented\n");
return *threads;
}
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
-using namespace std;
-
template<class Impl>
DefaultIEW<Impl>::DefaultIEW(Params *params)
: issueToExecQueue(params->backComSize, params->forwardComSize),
template<class Impl>
void
-DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(IEW, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
{
int max=0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned thread_count = skidBuffer[*threads++].size();
bool
DefaultIEW<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
{
int inst = 0;
- cout << "Available Instructions: ";
+ std::cout << "Available Instructions: ";
while (fromIssue->insts[inst]) {
- if (inst%3==0) cout << "\n\t";
+ if (inst%3==0) std::cout << "\n\t";
- cout << "PC: " << fromIssue->insts[inst]->readPC()
+ std::cout << "PC: " << fromIssue->insts[inst]->readPC()
<< " TN: " << fromIssue->insts[inst]->threadNumber
<< " SN: " << fromIssue->insts[inst]->seqNum << " | ";
}
- cout << "\n";
+ std::cout << "\n";
}
template <class Impl>
wbNumInst = 0;
wbCycle = 0;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
// Free function units marked as being freed this cycle.
fuPool->processFreeUnits();
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check stall and squash signals, dispatch any instructions.
while (threads != (*activeThreads).end()) {
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
-using namespace std;
-
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
int fu_idx,
resetState();
- string policy = params->smtIQPolicy;
+ std::string policy = params->smtIQPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
;
for (int i=0; i<Num_OpClasses; ++i) {
- stringstream subname;
+ std::stringstream subname;
subname << opClassStrings[i] << "_delay";
issueDelayDist.subname(i, subname.str());
}
template <class Impl>
void
-InstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(IQ, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
if (iqPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
while (threads != list_end) {
if (iqPolicy == Partitioned) {
*/
#include <algorithm>
+#include <list>
#include <string>
#include "cpu/o3/lsq.hh"
-using namespace std;
-
template <class Impl>
Tick
LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
//**********************************************/
//************ Handle SMT Parameters ***********/
//**********************************************/
- string policy = params->smtLSQPolicy;
+ std::string policy = params->smtLSQPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
template<class Impl>
void
-LSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+LSQ<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
activeThreads = at_ptr;
assert(activeThreads != 0);
if (lsqPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
int maxEntries;
void
LSQ<Impl>::tick()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
void
LSQ<Impl>::writebackStores()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
LSQ<Impl>::violation()
{
/* Answers: Does Anybody Have a Violation?*/
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
{
unsigned total = 0;
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::isFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::lqFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::sqFull()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::isStalled()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
bool
LSQ<Impl>::hasStoresToWB()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
if ((*activeThreads).empty())
return false;
bool
LSQ<Impl>::willWB()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
void
LSQ<Impl>::dumpInsts()
{
- list<unsigned>::iterator active_threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator active_threads = (*activeThreads).begin();
while (active_threads != (*activeThreads).end()) {
unsigned tid = *active_threads++;
#ifndef __CPU_O3_MIPS_CPU_HH__
#define __CPU_O3_MIPS_CPU_HH__
-#include "arch/isa_traits.hh"
+#include "arch/mips/regfile.hh"
+#include "arch/mips/syscallreturn.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/cpu.hh"
#include "sim/byteswap.hh"
+#include "sim/faults.hh"
class EndQuiesceEvent;
namespace Kernel {
template <class Impl>
class MipsO3CPU : public FullO3CPU<Impl>
{
- protected:
- typedef TheISA::IntReg IntReg;
- typedef TheISA::FloatReg FloatReg;
- typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::MiscReg MiscReg;
- typedef TheISA::RegFile RegFile;
- typedef TheISA::MiscRegFile MiscRegFile;
-
public:
typedef O3ThreadState<Impl> ImplState;
typedef O3ThreadState<Impl> Thread;
}
/** Reads a miscellaneous register. */
- MiscReg readMiscReg(int misc_reg, unsigned tid);
+ TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
/** Reads a misc. register, including any side effects the read
* might have as defined by the architecture.
*/
- MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault, unsigned tid);
+ TheISA::MiscReg readMiscRegWithEffect(int misc_reg,
+ Fault &fault, unsigned tid);
/** Sets a miscellaneous register. */
- Fault setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
+ Fault setMiscReg(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
/** Sets a misc. register, including any side effects the write
* might have as defined by the architecture.
*/
- Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
+ Fault setMiscRegWithEffect(int misc_reg,
+ const TheISA::MiscReg &val, unsigned tid);
/** Initiates a squash of all in-flight instructions for a given
* thread. The source of the squash is an external update of
*/
void syscall(int64_t callnum, int tid);
/** Gets a syscall argument. */
- IntReg getSyscallArg(int i, int tid);
+ TheISA::IntReg getSyscallArg(int i, int tid);
/** Used to shift args for indirect syscall. */
- void setSyscallArg(int i, IntReg val, int tid);
+ void setSyscallArg(int i, TheISA::IntReg val, int tid);
/** Sets the return value of a syscall. */
void setSyscallReturn(SyscallReturn return_value, int tid);
#include "cpu/o3/comm.hh"
#include "cpu/o3/thread_state.hh"
-using namespace TheISA;
-
template <class Impl>
MipsO3CPU<Impl>::MipsO3CPU(Params *params)
: FullO3CPU<Impl>(params)
// check for error condition.
if (return_value.successful()) {
// no error
- this->setArchIntReg(SyscallSuccessReg, 0, tid);
- this->setArchIntReg(ReturnValueReg, return_value.value(), tid);
+ this->setArchIntReg(TheISA::SyscallSuccessReg, 0, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, return_value.value(), tid);
} else {
// got an error, return details
- this->setArchIntReg(SyscallSuccessReg, (IntReg) -1, tid);
- this->setArchIntReg(ReturnValueReg, -return_value.value(), tid);
+ this->setArchIntReg(TheISA::SyscallSuccessReg,
+ (TheISA::IntReg) -1, tid);
+ this->setArchIntReg(TheISA::ReturnValueReg, -return_value.value(), tid);
}
}
#endif
#ifndef __CPU_O3_RAS_HH__
#define __CPU_O3_RAS_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include <vector>
/** Return address stack class, implements a simple RAS. */
#define __CPU_O3_REGFILE_HH__
#include "arch/isa_traits.hh"
-#include "arch/faults.hh"
#include "arch/types.hh"
#include "base/trace.hh"
#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
+#include "sim/faults.hh"
#if FULL_SYSTEM
#include "kern/kernel_stats.hh"
#include "config/full_system.hh"
#include "cpu/o3/rename.hh"
-using namespace std;
-
template <class Impl>
DefaultRename<Impl>::DefaultRename(Params *params)
: iewToRenameDelay(params->iewToRenameDelay),
template<class Impl>
void
-DefaultRename<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+DefaultRename<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(Rename, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
{
// Clear any state, fix up the rename map.
for (int i = 0; i < numThreads; i++) {
- typename list<RenameHistory>::iterator hb_it = historyBuffer[i].begin();
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[i].begin();
while (!historyBuffer[i].empty()) {
assert(hb_it != historyBuffer[i].end());
sortInsts();
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
// Check stall and squash signals.
while (threads != (*activeThreads).end()) {
bool
DefaultRename<Impl>::skidsEmpty()
{
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
if (!skidBuffer[*threads++].empty())
{
bool any_unblocking = false;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
threads = (*activeThreads).begin();
void
DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, unsigned tid)
{
- typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].begin();
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[tid].begin();
// After a syscall squashes everything, the history buffer may be empty
// but the ROB may still be squashing instructions.
"history buffer %u (size=%i), until [sn:%lli].\n",
tid, tid, historyBuffer[tid].size(), inst_seq_num);
- typename list<RenameHistory>::iterator hb_it = historyBuffer[tid].end();
+ typename std::list<RenameHistory>::iterator hb_it =
+ historyBuffer[tid].end();
--hb_it;
void
DefaultRename<Impl>::dumpHistory()
{
- typename list<RenameHistory>::iterator buf_it;
+ typename std::list<RenameHistory>::iterator buf_it;
for (int i = 0; i < numThreads; i++) {
#include <vector>
#include "cpu/o3/free_list.hh"
-//For RegIndex
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
class SimpleRenameMap
{
#include "config/full_system.hh"
#include "cpu/o3/rob.hh"
-using namespace std;
+#include <list>
template <class Impl>
ROB<Impl>::ROB(unsigned _numEntries, unsigned _squashWidth,
- string _smtROBPolicy, unsigned _smtROBThreshold,
+ std::string _smtROBPolicy, unsigned _smtROBThreshold,
unsigned _numThreads)
: numEntries(_numEntries),
squashWidth(_squashWidth),
threadEntries[tid] = 0;
}
- string policy = _smtROBPolicy;
+ std::string policy = _smtROBPolicy;
//Convert string to lowercase
std::transform(policy.begin(), policy.end(), policy.begin(),
template <class Impl>
void
-ROB<Impl>::setActiveThreads(list<unsigned> *at_ptr)
+ROB<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
{
DPRINTF(ROB, "Setting active threads list pointer.\n");
activeThreads = at_ptr;
if (robPolicy != Dynamic || numThreads > 1) {
int active_threads = (*activeThreads).size();
- list<unsigned>::iterator threads = (*activeThreads).begin();
- list<unsigned>::iterator list_end = (*activeThreads).end();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator list_end = (*activeThreads).end();
while (threads != list_end) {
if (robPolicy == Partitioned) {
ROB<Impl>::canCommit()
{
//@todo: set ActiveThreads through ROB or CPU
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
bool first_valid = true;
// @todo: set ActiveThreads through ROB or CPU
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned thread_num = *threads++;
tail = instList[0].end();
bool first_valid = true;
- list<unsigned>::iterator threads = (*activeThreads).begin();
+ std::list<unsigned>::iterator threads = (*activeThreads).begin();
while (threads != (*activeThreads).end()) {
unsigned tid = *threads++;
#include <iostream>
#include <utility>
#include <vector>
-#include "arch/isa_traits.hh"
#include "base/trace.hh"
#include "base/traceflags.hh"
#include "cpu/o3/comm.hh"
#include <utility>
#include <vector>
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
struct ltseqnum {
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
-using namespace TheISA;
-
#if FULL_SYSTEM
template <class Impl>
VirtualPort *
#ifndef __CPU_O3_THREAD_STATE_HH__
#define __CPU_O3_THREAD_STATE_HH__
-#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#ifndef __CPU_O3_TOURNAMENT_PRED_HH__
#define __CPU_O3_TOURNAMENT_PRED_HH__
-// For Addr type.
-#include "arch/isa_traits.hh"
#include "cpu/o3/sat_counter.hh"
+#include "sim/host.hh"
#include <vector>
/**
#include "arch/faults.hh"
#include "arch/alpha/osfpal.hh"
#include "arch/alpha/tlb.hh"
+#include "arch/alpha/types.hh"
#include "arch/vtophys.hh"
#include "base/callback.hh"
//#include "base/remote_gdb.hh"
#define __CPU_OZONE_DYN_INST_HH__
#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/inst_seq.hh"
*/
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
#include "config/full_system.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "kern/kernel_stats.hh"
-using namespace TheISA;
-
template <class Impl>
OzoneDynInst<Impl>::OzoneDynInst(OzoneCPU *cpu)
: BaseDynInst<Impl>(0, 0, 0, 0, cpu)
#include <list>
#include <utility>
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
/**
* Simple class to hold onto a list of pairs, each pair having a memory
#include "arch/faults.hh"
#include "arch/isa_traits.hh"
+#include "arch/utility.hh"
#include "base/statistics.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
*/
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "cpu/ozone/inorder_back_end.hh"
#include "cpu/ozone/thread_state.hh"
-using namespace TheISA;
-
template <class Impl>
InorderBackEnd<Impl>::InorderBackEnd(Params *params)
: squashPending(false),
#include <algorithm>
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
* Authors: Kevin Lim
*/
-#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/str.hh"
#include "cpu/ozone/lsq_unit.hh"
#include <algorithm>
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "config/full_system.hh"
#include "base/hashmap.hh"
#include "cpu/inst_seq.hh"
#include "config/use_checker.hh"
-#include "arch/isa_traits.hh"
+#include "arch/faults.hh"
#include "base/str.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "cpu/checker/cpu.hh"
#ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
#define __CPU_OZONE_NULL_PREDICTOR_HH__
-#include "arch/isa_traits.hh"
#include "cpu/inst_seq.hh"
+#include "sim/host.hh"
template <class Impl>
class NullPredictor
#ifndef __CPU_OZONE_OZONE_IMPL_HH__
#define __CPU_OZONE_OZONE_IMPL_HH__
-#include "arch/alpha/isa_traits.hh"
#include "cpu/o3/bpred_unit.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/ozone/inst_queue.hh"
#ifndef __CPU_OZONE_SIMPLE_IMPL_HH__
#define __CPU_OZONE_SIMPLE_IMPL_HH__
-#include "arch/isa_traits.hh"
#include "cpu/o3/bpred_unit.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/ozone/front_end.hh"
#define __CPU_OZONE_THREAD_STATE_HH__
#include "arch/faults.hh"
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
+#include "arch/regfile.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "sim/process.hh"
#include <string>
#include "arch/isa_traits.hh"
-#include "arch/faults.hh"
#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
#include "cpu/o3/dyn_inst.hh"
+#include "sim/faults.hh"
#include "sim/host.hh"
// forward declarations
#ifndef __CPU_THREAD_STATE_HH__
#define __CPU_THREAD_STATE_HH__
-#include "arch/isa_traits.hh"
+#include "arch/types.hh"
#include "cpu/thread_context.hh"
#if !FULL_SYSTEM
#include "sim/sim_events.hh" // for SimExitEvent
-using namespace std;
-
template<class TagStore, class Buffering, class Coherence>
bool
Cache<TagStore,Buffering,Coherence>::
MSHR* mshr = missQueue->findMSHR(blk_addr, pkt->req->getAsid());
// There can be many matching outstanding writes.
- vector<MSHR*> writes;
+ std::vector<MSHR*> writes;
missQueue->findWrites(blk_addr, pkt->req->getAsid(), writes);
if (!update) {
#include "sim/eventq.hh" // for Event declaration.
#include "mem/request.hh"
-using namespace TheISA;
-
/**
* @todo Move writebacks into shared BaseBuffer class.
*/
* Describes a tagged prefetcher based on template policies.
*/
+#include "arch/isa_traits.hh"
#include "mem/cache/prefetch/tagged_prefetcher.hh"
template <class TagStore, class Buffering>
#define __MEM_PACKET_HH__
#include "mem/request.hh"
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include "sim/root.hh"
#include <list>
#include <string>
-#include "arch/faults.hh"
+#include "sim/faults.hh"
#include "arch/isa_traits.hh"
#include "base/hashmap.hh"
#include "base/trace.hh"
* Authors: Ali Saidi
*/
-#include "arch/isa_specific.hh"
-#include "arch/isa_traits.hh"
#include "mem/port.hh"
#include "sim/byteswap.hh"
void
FunctionalPort::writeHtoG(Addr addr, T d)
{
- d = TheISA::htog(d);
+ d = htog(d);
writeBlob(addr, (uint8_t*)&d, sizeof(T));
}
{
T d;
readBlob(addr, (uint8_t*)&d, sizeof(T));
- return TheISA::gtoh(d);
+ return gtoh(d);
}
#ifndef __MEM_REQUEST_HH__
#define __MEM_REQUEST_HH__
-#include "arch/isa_traits.hh"
+#include "sim/host.hh"
#include "sim/root.hh"
class Request;
class ThreadContext;
-//We need the "Tick" data type from here
+//We need the "Tick" and "Addr" data types from here
#include "sim/host.hh"
-//We need the "Addr" data type from here
-#include "arch/isa_traits.hh"
namespace AlphaPseudo
{
projects / gem5.git / commitdiff